201112203 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種驅動電路 用於顯示面板之移位暫存器。 Η系關於種 【先前技術】 請參照第i圖所示，其顯示 . 題干哭夕4交Λν Μ 士 搜^知用於液晶 ‘”，員不裔之移位暫存器。該移位 接之驅動級9U中各^ 益9包含複數串 ;叹w，再亍母一驅動級9ι罝 及一輸出端，每一驅動@ q ί '、 輸入細 母驅動級91之輪出端連拯5苴丁一 驅動級之輸入端以及一液晶顯示器 -二 每一驅動級91另接收一時y連、“听描線。 有相位差之時脈信號，g备 動級接收不二 動級91與其相鄰驅 功、.次钱收不同組時脈信號。 .. 請同時參照第2及3圖所示， 圖之移位暫存器之'級驅動級之電路同 弟1 示第2岡* L 路圖；第3圖顯 弟圖之-級驅動級之操作時序圖— '•及驅動級9 1做說明。 弟 於第一期間tl，一高準位幹 $ ^ λ .^ %入仏戒input輸入 輪入柒而開啟開關元件sw；j及 # 位被充電至古進H „弘 ό，卽點P之電 。电主问準位而開啟開問 信號CLK 5 w ι i ^ +SW!以耦合時脈 儿至輸出端1，由於 位，輸+ & q > 、、彳5说CLKt為低準 翰出碥1之電位呈低準位。 .於時脈信泸CLK糸一隹 、弟』間I ’由 "。為巧準位而開啟開關元件SW5， 3 i Cl 01417-TW/A09017 201112203 一直流電流將自電源vDD流至電源Vss而消耗不必 要的電流；此處開關元件SW6係設計成遠大於開關. 兀件SW5，因此節點P，之電位可被放電至低準位而 關閉開關元件S W2及s w4。 ·201112203 VI. Description of the Invention: [Technical Field] The present invention relates to a shift register for a display panel for a display panel. Η 关于 种 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 In the driver stage 9U, each of the benefits 9 includes a plurality of strings; the sigh w, then the 一 mother-driver stage 9 罝 and an output, each drive @ q ί ', the input fine mother drive stage 91 5 一 一 drive stage input and a liquid crystal display - two each drive stage 91 to receive a one-time y, "hear line. There is a phase difference clock signal, and the g standby stage receives the non-secondary stage 91 and its adjacent drive power, and the second time receives different sets of clock signals. .. Please also refer to the figures 2 and 3 at the same time. The circuit of the 'level drive stage of the shift register of the figure shows the 2nd gang* L road map; the 3rd figure shows the level-level drive stage Operation timing diagram - '• and driver stage 9 1 for explanation. In the first period tl, a high-level position of $ ^ λ . ^ % into the 仏 or input input wheel 柒 and open the switching element sw; j and # bits are charged to Gu Jin H „ Hong ό, 卽 point P The electric main asks the level and turns on the open signal CLK 5 w ι i ^ +SW! to couple the clock to the output 1. Because of the bit, the input + & q > , 彳 5 says CLKt is low The potential of John's 碥1 is low. In the clock, CLK 糸 隹 隹 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A DC current will flow from the power supply vDD to the power supply Vss and consume unnecessary current; here the switching element SW6 is designed to be much larger than the switch. The device SW5, so the potential of the node P can be discharged to the low level and the switch is turned off. Components S W2 and s w4.
於第二期間t2 ’輸入端轉換為低準位而關閉開 關元件SW3及SW6。時脈信號CLK3轉換為低準位 而關閉開關元件SW5。節點P，並未受到充電，因此 其電位仍維持低準位而關閉開關元件swj SW4。 日才脈心沉CLK!轉換為高準位，節點p之電位受到 時脈信號CLK1肖雜散電容之_合效應而提高（約 90%時脈信號CLKl之電位變化)；因此節‘點p仍維 持2高準位而開啟開關元件sWl，時脈信號CLKi 之门準位被耦合至輸出端丨而使輸出端1於此期間 輸出高準位之輸出信號。 一於第三期間輸入端仍為低準位而使得段 一仆SV/3及請6保持關閉。時脈信號CLK3仍I 準位而保持開關元件SW5之關閉狀態。節點py 2維持低準位而關閉開關Tt件SW2& sw4。a： i CLK】轉換為低準位並透過脈信號cLK 1之表 效f拉低節點P之電位(約90%時脈信號CLKy :夂化）’但節點p並沒經過其他路徑放電而仍气 =準“開啟開關元件SWi，時脈信號clk 低準位被耦合至輪出端1。 0141J-TW/A09017 201112203 於苐四期間“，輸入端維持為低準位而關閉開 關元件SW3及SW6且由於時脈信號CLK3再度轉換 為高準位而開啟開關元件SW5，節 位而開啟開關元件s™4;因此，== 出端1均被耦接至電源Vss而放電至低準位。 接著在第四期間t4以後的各期間，時脈信號 CLKLK〕將在連續期間依序轉換為高準位脈衝， $第3圖所示。輸出端i僅在時脈信號“I轉換為 :準位_接至電源Vss ’在時脈信號咖1及c% :兩準位期間則無連接至任何電源而呈現浮接 :ng)的情形，亦即輸出端 出妾的狀態;而電路浮接會導致輸 出卷位汗動而谷易出現誤動作的情形。.. 有鏜於此，有必要描φ 之移位u 々的用於嘴示面板 ^位暫h輯決或降低f知電路 )洋接及消耗額外功率之問題。 子在輸出 【發明内容】 本發明提出一種用於顯示面板之 该移位暫存器之輸出端具有較 .曰存為， 移位暫存器可有效降 、子乂犄間，且該 令双k低軚出信號之漣波。 本發明提出一種用於鞀 含複數串接之>〜、’、板之移位暫存器包 P丧之與动級。母' -輪出端充電單元、 輸入端、 早π及—充電驅動c, 01417-TW / A090 ] 7 201112203 單兀*。該充電單元根據一 μ 時脈信號對該輸出端充電。：：；，電位使'第-時脈信號同時將該第— 乂电早兀根據一第二 一第三時脈信號卩：該輸出端放電及根據 根據該輸入端及該第二亥充電驅動單元 節點之電位。 了脈彳5唬之電位控制該第一 償單ί::之移位暫存器之每-驅動級另包含-補 ==該第一時脈信號、該第-節點、該充 為低準位且^ 亥驅動級之輪出端 端之連波。ρ㈣信號為高準位時降低該輸出 本=另提出一種用於顯示面板之移位 端'-輸出二第動二 開關、；第四開關、：門=二_、—第三 第-開關具有一第—關及：弟六開關。該. 轉接該輸出端及—μ u # *7gp I —第二端 i而耦接一第一節點。該第二 I、有一第-端及-控制端耦接該輸入端及一第 第—節點。該第三開關具有一第—‘ 一第：日:—第-端耦接™電源及-控制端接收 第二：：脈2。該第四開關具有一第一端耗接該 = ”’、、—弟二端耦接該電源及一控制端接收該 弟-《信號。該第五關接該輸 01417-TW/A09017 201112203 出端、一第二端耦接該電源及一控制端接收一第三 時脈信號。該第六開關具有一第一端耦接該輸入 端、一第二端耦接該第一節點及一控制端接收該第 三時脈信號。 本發明之另一實施例中，用於顯示面板之移位 暫存器另包含一第七開關及一第八開關。該第七開 關具有一第一端接收該第一時脈信號、一第二端耦 接該第二節點及一控制端耦接該第一節點。該第八 開關，具有一第一端耦接該第一節點、一第二端耦 接該輸出端及一控制端接收該第一時脈信號。 本發明另提出一種用於顯示面板之移位暫存器 包含複數串接之驅動級，每一驅動級包.含一輸入 端、一輸出端、一充電單元、一放電單元、一充電 驅動單元及一補償單元。該充電單元用以娘據一第 一節點之電位使一第二節點對該輸出端充電。該放 電單元用以根據至少一時脈信號將該第一節點及該 輸出端放電。該充電驅動單元用以根據該輸入端及 該時脈信號之電位控制該第一節點之電位。該補償 單元，耦接於該第一時脈信號、該第一節點、該第 二節點及該輸出端之間；該補償單元包含一第七開 關及一第八開關，其中該第七開關具有一第一端接 收一第一時脈信號、一第二端耦接該第二節點及一 控制端耦接該第一節點；該第八開關具有一第一端 Γ ai417-TW/A090I7 7 201112203 福接該第-節點、—第二端接該輸出端及—控制端 接收°亥第蚪脈彳§號；其中每一驅動級之該第二節 點耦接至下一驅動級之輸入端。 本發明之顯示面板之移位暫存器中，當每一驅 動級接收三個具相位差之時脈信號時，其輸出端僅 ，力有33.3%的a㈣為浮接；當每—驅動級接收二個 具相=差之時脈信號時，其輪出端僅約有5〇%的時 y為孚接本务明並透過於每一驅動級加入一補償 單元以消除輸出信號浮動之問題。 、 【實施方式】 為了。襄本叙明之上述和其他目的、特徵 '、和優 點能更明顯，下文將配合所附圖示，作詳說明如 y。於本發明之說明中，相同之構件係以相同之符 號表示，於此合先敘明。The switching elements SW3 and SW6 are turned off during the second period t2' input to a low level. The clock signal CLK3 is switched to the low level to turn off the switching element SW5. The node P is not charged, so its potential remains at a low level and the switching element swj SW4 is turned off. The CLK is converted to a high level, and the potential of the node p is increased by the effect of the sinusoidal capacitance of the clock signal CLK1 (about 90% of the potential change of the clock signal CLK1); therefore, the node 'point p While still maintaining the 2 high level and turning on the switching element sW1, the gate level of the clock signal CLKi is coupled to the output terminal 丨 so that the output terminal 1 outputs the output signal of the high level during this period. During the third period, the input terminal is still at a low level, so that the slaves SV/3 and Please 6 remain closed. The clock signal CLK3 remains at the I level while maintaining the off state of the switching element SW5. The node py 2 maintains the low level and turns off the switch Tt pieces SW2 & sw4. a: i CLK] is converted to a low level and the potential of the node P is pulled through the effect of the pulse signal cLK 1 (about 90% of the clock signal CLKy: 夂)) but the node p is not discharged through other paths. Gas = quasi "turn on the switching element SWi, the clock signal clk low level is coupled to the wheel terminal 1. 0141J-TW/A09017 201112203 during the fourth period ", the input terminal is maintained at a low level and the switching elements SW3 and SW6 are turned off. And because the clock signal CLK3 is again converted to a high level, the switching element SW5 is turned on, and the switching element sTM4 is turned on; therefore, the =1 output terminal 1 is coupled to the power source Vss and discharged to the low level. Then, in each period after the fourth period t4, the clock signal CLKLK] is sequentially converted into a high level pulse in the continuous period, as shown in Fig. 3. The output i is only in the case where the clock signal "I is converted to: level_connected to the power supply Vss" during the clock signal 1 and c%: during the two levels, there is no connection to any power source and floats: ng) That is, the state of the output terminal is out; the floating circuit of the circuit causes the output volume to sweat and the valley is prone to malfunction. For this reason, it is necessary to describe the shift of the φ for the mouth. The panel is temporarily or repeatedly reduced or reduced. The sub-output is in the output. [Invention] The present invention provides an output of the shift register for the display panel. As a result, the shift register can effectively reduce the sum of the sub-turns, and the double-k is low chopping the signal. The present invention proposes a <~, ', board for the complex serial connection The shift register register P is lost and the moving stage. The mother '-wheel outlet charging unit, input terminal, early π and - charging driver c, 01417-TW / A090 ] 7 201112203 single 兀 *. The charging unit is based on A μ clock signal charges the output terminal.::;, the potential causes the 'first-clock signal to simultaneously the first- The second third clock signal 卩: the output is discharged according to the potential of the node according to the input terminal and the second charging driving unit. The potential of the pulse is controlled by the potential of the pulse 5彳Each of the bit buffers of the bit register further includes -compensation == the first clock signal, the first node, the charge is a low level, and the wave terminal of the drive stage is connected. The ρ (four) signal is Lowering the output at a high level = another type of shifting end for the display panel '-output two second moving switch; fourth switch,: door = two _, - third first switch having a first Off: the six switches. The switch is connected to the output terminal and -μ u # *7gp I - the second end i is coupled to a first node. The second I, a first end and a - control end are coupled The input terminal and a first node - the third switch has a first - first: day: - the first end is coupled to the TM power supply and - the control end receives the second:: pulse 2. The fourth switch has a The first end consumes the ="', the second terminal is coupled to the power supply and the control terminal receives the younger-"signal. The fifth switch connects the output 01417-TW/A09017 201112203, the second end is coupled to the power source and a control terminal receives a third clock signal. The sixth switch has a first end coupled to the input end, a second end coupled to the first node, and a control end receiving the third clock signal. In another embodiment of the present invention, the shift register for the display panel further includes a seventh switch and an eighth switch. The seventh switch has a first end receiving the first clock signal, a second end coupled to the second node, and a control end coupled to the first node. The eighth switch has a first end coupled to the first node, a second end coupled to the output end, and a control end receiving the first clock signal. The present invention further provides a shift register for a display panel comprising a plurality of serially connected driver stages, each driver stage package comprising an input terminal, an output terminal, a charging unit, a discharge unit, and a charging driving unit And a compensation unit. The charging unit uses a potential of a first node to cause a second node to charge the output. The discharge unit is configured to discharge the first node and the output terminal according to at least one clock signal. The charging driving unit is configured to control the potential of the first node according to the input end and the potential of the clock signal. The compensation unit is coupled between the first clock signal, the first node, the second node, and the output end; the compensation unit includes a seventh switch and an eighth switch, wherein the seventh switch has a first end receives a first clock signal, a second end is coupled to the second node, and a control end is coupled to the first node; the eighth switch has a first end Γ ai417-TW/A090I7 7 201112203 The second node is connected to the output terminal, and the second terminal is connected to the output terminal and the control terminal receives the second phase; wherein the second node of each driver stage is coupled to the input terminal of the next driver stage. In the shift register of the display panel of the present invention, when each driver stage receives three clock signals with phase difference, the output terminal only has a force of 33.3% a (four) for floating; when each drive stage When receiving two clock signals with phase=difference, when the round-trip end is only about 〇%, the y is the first thing and the compensation unit is added to each driver stage to eliminate the floating of the output signal. . [Embodiment] For the sake of. The above and other objects, features, and advantages of the present invention will be more apparent, and will be described in detail below with reference to the accompanying drawings. In the description of the present invention, the same components are denoted by the same reference numerals and will be described in the foregoing.
V 請參照第4圖所示，其顯示本發明第—實施例 =用於顯示面板之移位暫存器。移位暫存器1〇包含 I數♦接且貫賀相同之驅動級丨丨。每一驅動級1丄 包含一輸入端111及一輪出端112，該輸入端lu 用以接收-輸人信號INPUT;該輸出端112用以輸 山一輸出k號OU1 PUT至一顯示面板（未繪示）的一 條掃描線並耦接至下一驅動級丨丨之輸入端m，亦 即母一驅動級11所輸出之輸出信號OUTPUT係同 柃作為掃描信號及下一驅動級之輪入信號INPUT。 % 01417-TW/A09017 201112203 母一驅動級u並接收三個具相位差之時脈 cLKi〜CLK3。該第一時脈信號至第 ：： CLK广CLK3係由—時脈產生器2〇所提供，复= 時脈產生器20可包含或不包含於該移位暫存哭Γ〇 内。此外’本發明之說明中，高準位例 。 特，低準位例如可為-ίο伏特，但本發明並不LT此 叫夢'、?、第5圖所示’其顯示本發 面板之移位暫存器之第—級用 =不 動級11包含一輪入媳ni u的电路圖。驅 早兀113、一充電驅動 冤 初早兀及—放電單元115。 =電單元113用以根據—節 :_該輪出端112充電以 ：: 號。該充電單元113 -早位之輪“ 交Γ . 1笛 弟—開關T!及一第—電 奋C丨’δ亥弟一開關Τι具有一第一 斤士兒 信號CLK"；、一穿_沪全Λ 而按收一弟一日寸脈 耦接一Μ 〃輕接該輸出端⑴及一控制端 耦接一弟一郎點ρ去 ^ Aq 啟該第1關Ί、，若二郎點Pl為高準位而開 高準位，該輪出端^之=脈信號CLK1同時為 該第一電容q接於兮=將被充電至高準位。 二端間，用以降低检開關I之控制端與第 輸出低準位時因輕==伽於該驅動級11 強調的是，第一電容 ^成之漣波（npple)。必須 在Cl °』根據不同實施例而省略。 .該充電驅動單元114 阳以根據該輸入端111 01417-TW/A09017 201112203 恭第— a卞脈化號CLK3之電位控制該第一節點I之 -电位以驅動該充電單元113之動作。該充電驅動單 ::14具有一第一節點用以控制該充電單元113 :開關!：〖之開啟或關閉。該充電驅動單元⑴ τ ^ # 2第六開關丁6。該第二開關 I2，、有一第一端及一控制端耦接該輸入端lu及一 弟-端耦接該第一節點Ρι。該第六開關八具有一第 -：耗接該輪入端ln、—第二端柄接該第一節點 1控制端接收該第三時脈信號CLK3。 °亥放％早70 115用以根據—第二時脈信號clk2 及該第三時脈作获ΓΤ12 U CLK3將該第一節點PJ該輸出 ，放電’以消除該第—節點Ρι及該輸出端112 :J f _日守脈仏谠CLKl為低準位時之浮接情形。該 :f凡115包含一第三開_ τ3、-第职開關τ4 、一弟五濶_ 1,5。該第三開Μ τ3之第-端與第二端 第五開關丁5之第一端與第二端，該第三 開關τ3及第五卩卩關τ 開關丁5之第一端耦接該輸出端11 2 ’ ::弟„接-電源Vss;該第三開關τ3之控制端 山收°亥第—時脈信號CLK2，該第五開關τ5之控制 =3 5收竣弟三時脈信號CLK.3。該第四開關τ4具有 弟$而耦接該第一節點、—第二端耦接該電源 及k d端接收該第二時脈信號clk2。該電源 例如’但不限於’可為-10伏特，其用以對該第 -即點Pi及該輸出端112放電。 ai417-TW/A09〇17 、 201112203 曰该第-開關至第六開關Tl〜T^如可為薄膜電 晶體（TFT)並具有相同之電導型式（例如帝曰 =該第一開關至第六叫τ6可利用非晶 ^ ^ 3¾ M t a (amorphous silicon thin film transist〇r process)直接形成於一玻璃基板上。 級驅動級之操作示意圖 :同時參照第6及7圖所示，第6圖顯示該移 暫存器之操作時序圖；》7圖顯示該移位暫存器 BEr〇 Art _>» 13. /L·. — λ- _ ;弟一』間^，該充電‘驅動單元U4自該輸7 11接收一輸入信號1咖τ之高準位脈衝㈣se 並透過該第六開關τ6之控制端接收該第三時脈㈣ clk3之高準位脈衝。此時，該充電驅動旱元11“ 開關τ2、τ6均開啟（ON)並將該第一節點Ρι之電伯 充電至高準位而開啟該充電單元113之、第—S T二該第三時脈信號CLK3同時開啟該放電單元11) 之第五開關丁5以使該輪出端112耦接至電源Vss ' 該第一時脈信號（^之^:位為低準位，因此該輪出 知112之電位在此期間為低準位。此外，由於該第 -時脈信.號CLK2為低準位而使得該第三開關 第四開關丁4維持關閉（0FF)。 " 3 U於第二期間t2，輸入信號INPUT及第三時脈信 波clk3均轉換為低準位而關閉該充電驅動單元⑴ 之開關.T 2、T 6以及該放電單元i】5之第五開關 01417-TW/A09017 11 201112203 希，_時脈彳5號CLK：2仍維持為低準位而關閉該放 ^元115之開關τ3、τ4。該第一時脈信號CLKi 4時轉換為高準位，導致該第—節點P1之電位受到 該第—時脈信號CLK1與雜散電容之耦合效應進一 =拉升而維持於高準位並開啟該第—開關T1，因 在》亥輸出端112被該第一時脈信號（：乙 Γ未:輸Γ高準位之輸出脈衝信號至；= (未、.·曰不）之—掃描線或下-驅動級u之輸人端川。 號二^信號1NPUT及第三時脈信 之… 關閉該充電驅動單元114 ^關n6以及該放電單元115之第五開關T5。 :元號CLK2轉換為高準位而開啟該放電 得該第-節…該輸 輪出低準妆夕趴 因此，該輸，.出端112 位之輸出信號，·該充電驅動單元114之第 一即點Pi被放電至低準位而關閉苐-開關T1。弟 仿而=:=t4’輸入信號卿仍維持為低準 位動單元114之第二。3 一％脈f吕唬CLfC,鞞描故你，.住， 2 e弟 山之《 、τ Λ Λ 闕閉心電單元 準位而開啟該充^/動弟;⑽化號CLK3轉換為高 乂尤I驅動單元】；之笫丄 得該第-節點仍維持 關閉I?而從 I;該第三時•信叫同時開二 01417-TW/A09017 ^ 12 201112203 之第五開關τ5而使得該輪出端㈣接至電源^ 位而=:rt5’輪入信號_仍維持為低準 :;=?元114之第二開關τ2。該第 元115之門Η τ 2乃維持為低準位而關閉該放電單 兀i13之開關τ3、丁兮 干 ❿ 為低準位而_該充電轉換 及該放電單元115之第五= :70 U4之第六開關τ6 ⑽轉換為高準二五開…^ 脈信號CLK,與雜散電Χ容即=占Pl受到該第一時 啟該第-開關τ,，導致該輪出 漣波而開 透過叙接-大電第—節…連波可 ^ '值之弟—電容Ci來削減。 第六期間t6及第七里0 pp 13及第四期間14 ’卿:：轉目同於第三期間 明m 8圖所示，其顯示本 之用於顯示面板之移㈣# 弟—貞細例 圖。驅動級σ_ —㈣動級之電路 元114、一放電單元ml::二充電騣動單 單元⑴、充電驅動單元114及放:早:…。該充電 與第一實施例之第5圖相同，心：7" 115之構造 補償單元m心當—驅動級之於:再賢述。該 準位信號而該第-時脈信號CLK”:V12輸出低 6圖之第五期降低_ — (如第 山〜112之;連波， 0J417-TW/A09017 201112203 可用以驅動下一級驅動級。 該補償單元丨1 6包含一第 關第1容C ” 7、一第八開 罘一包合C2。该第七開關且 端接收該第—時脈作声 ^ /、啕弟一 Μ 1〇就CLK1、一弟二端透過一第一 :點P趣該充電單元113之第—開關Τι之第：： 控制端輕接該充電驅動單& 114之第一節點 p」。該第八開關丁8具有一第，接該充電驅動單 之第一節點Ρι、一第二端耦接該輸出端⑴ 一控制端接收該第一時脈信號CLK“ i中，者卞 第-時脈信號CLK,由低準位轉換為高準位之；： 期間内三該第八開關T8被開啟並將該充電驅動單元 114之第節點Ρ!之電荷放電至該輸出端112。藉 此，當該驅動級11'於輸出低準位期間，可以降低言^ 第一節點Ρ〗受到該第一時脈信號CLK]#、換至高準 位時的耦合效應而產生的漣波。該第二電容C2之一 端搞接該充電驅動單元114之第一節點Ρι，另一端 輕接於遠第一卽點P2及該第一節點p!間。當該第— 日’Ϊ脈k號CLKi轉換為局準位時（其電位例如為V. Referring to Fig. 4, there is shown a first embodiment of the present invention = a shift register for a display panel. The shift register 1〇 contains the I-number and the same drive level. Each driver stage 1 includes an input terminal 111 and a round output terminal 112 for receiving and inputting an input signal INPUT; the output terminal 112 is for outputting a mountain and outputting a k number OU1 PUT to a display panel (not a scanning line is coupled to the input terminal m of the next driving stage ,, that is, the output signal OUTPUT outputted by the mother-drive stage 11 is used as the scanning signal and the rounding signal of the next driving stage. INPUT. % 01417-TW/A09017 201112203 The mother-driver stage u receives three clocks with phase difference cLKi~CLK3. The first clock signal to the :: CLK wide CLK3 is provided by the clock generator 2, and the complex = clock generator 20 may or may not be included in the shift temporary buffer. Further, in the description of the present invention, the high level is an example. Specifically, the low level can be, for example, - ίο volt, but the present invention is not LT, which is called 'dream', ?, and FIG. 5, which shows the first stage of the shift register of the present panel. 11 contains a circuit diagram of the round 媳ni u. Drive early 113, a charge drive 冤 early and 放电 discharge unit 115. The electric unit 113 is used to charge the following number 112 according to the section: _. The charging unit 113 - the early wheel "crossing. 1 flute - switch T! and a first - electric Fen C丨 'δ海弟 a switch Τι has a first jinsian signal CLK"; Λ Λ Λ 按 按 按 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 弟 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该When the high level is high and the high level is turned on, the pulse signal CLK1 of the round terminal is simultaneously connected to the first capacitor q and will be charged to the high level. The second end is used to lower the control end of the check switch I. When the output low level is light == gamma, the driver stage 11 emphasizes that the first capacitor is cp (npple). It must be omitted in accordance with different embodiments. The charging driving unit 114 Yang controls the potential of the first node I to drive the charging unit 113 according to the potential of the input terminal 111 01417-TW/A09017 201112203 恭第— a 卞 pulse number CLK3. The charging driver: :: 14 has A first node is used to control the charging unit 113: switch!: turn it on or off. The charging drive unit (1) τ ^ # 2 sixth switch hex 6. The second switch I2 has a first end and a control end coupled to the input end lu and a second end coupled to the first node 。. The sixth switch VIII has a first-: consuming the round-ended end Ln, - the second end handle is connected to the first node 1 control terminal to receive the third clock signal CLK3. °Hoon% early 70 115 is used to obtain the second clock signal clk2 and the third clock signal U CLK3 discharges the output of the first node PJ and discharges to eliminate the floating condition of the first node 及ι and the output terminal 112: J f _ 守 脉 CLK CLKl is at a low level. The third end _ τ3, the first duty switch τ4, the first 濶 濶 1, 1, 1, the first end and the second end of the third switch τ3 The first end of the third switch τ3 and the fifth switch τ switch 5 is coupled to the output end 11 2 ': the younger-connected power supply Vss; the third end of the third switch τ3 is controlled by the mountain - Clock signal CLK2, the control of the fifth switch τ5 = 3 5 receives the third clock signal CLK.3. The fourth switch τ4 is coupled to the first node, the second terminal is coupled to the power source, and the kd terminal receives the second clock signal clk2. The power source, for example, but not limited to, may be -10 volts for discharging the first - point Pi and the output terminal 112. ai417-TW/A09〇17, 201112203 曰 The first to sixth switches T1 to T^ can be thin film transistors (TFTs) and have the same conductivity type (for example, the first switch to the sixth switch) Τ6 can be directly formed on a glass substrate by using an amorphous silicon thin film transist 〇r process. Operational diagram of the stage driving stage: Referring to FIGS. 6 and 7, FIG. 6 shows the Operation timing diagram of the shift register; "7 shows that the shift register BEr〇Art_>» 13. /L·. — λ- _; brother one" ^, the charging 'drive unit U4 from The input 7 11 receives an input signal 1 τ high-level pulse (4) se and receives the high-level pulse of the third clock (4) clk3 through the control terminal of the sixth switch τ6. At this time, the charging drives the drought element 11" The switches τ2 and τ6 are both turned ON (ON) and charges the first node 电1 to the high level to turn on the second unit clock signal CLK3 of the charging unit 113 and simultaneously turn on the discharge unit 11) The fifth switch 5 is configured to couple the wheel terminal 112 to the power source Vss '. The first clock signal (^^: the bit is low level Bit, so the potential of the wheel 112 is low during this period. In addition, the third switch fourth switch 4 is kept off (0FF) because the first-clock signal CLK2 is at a low level. " 3 U in the second period t2, the input signal INPUT and the third clock signal clk3 are both converted to a low level to turn off the switch of the charging drive unit (1). T 2, T 6 and the discharge unit i] 5 The fifth switch 01417-TW/A09017 11 201112203 _, _ clock 彳 5 CLK: 2 still maintains a low level and closes the switch τ3, τ4 of the discharge element 115. The first clock signal CLKi 4 Converting to a high level causes the potential of the first node P1 to be maintained at a high level by the coupling effect of the first-clock signal CLK1 and the stray capacitance, and the first switch T1 is turned on, because The output terminal 112 is subjected to the first clock signal (: Γ Γ : : Γ Γ Γ = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =端川. No. 2 signal 1NPUT and third clock signal... Turn off the charging drive unit 114 ^OFF n6 and the fifth switch T5 of the discharge unit 115 : The number CLK2 is converted to a high level and the discharge is turned on to the first section... The output wheel is low in the makeup evening. Therefore, the output, the output signal of the output 112, the first of the charging drive unit 114 One point Pi is discharged to a low level and the 苐-switch T1 is turned off. The analog input ===t4' input signal remains as the second of the low level moving unit 114. 3%% pulse f 吕唬CLfC, 故写故你,.住, 2 e弟山之", τ Λ Λ 阙 心 心 心 心 心 心 心 心 心 心 心 / ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; CLK CLK乂尤I drive unit]; then the first node still maintains the I? and I; the third time • the letter calls the second switch 0115-TW/A09017^12 201112203 fifth switch τ5 The round end (4) is connected to the power supply and the =: rt5' rounding signal _ remains at the low level:; = the second switch τ2 of the element 114. The threshold τ 2 of the cell 115 is maintained at a low level, and the switch τ3 of the discharge unit i13 is turned off, the 兮 兮 ❿ is at a low level _ the charge conversion and the fifth of the discharge unit 115 = : 70 The sixth switch τ6 (10) of U4 is converted into a high-precision two-five open ... ^ pulse signal CLK, and the stray electric capacitance is = when Pl receives the first-time start of the first-switch τ, causing the round-out chopping Open through the connection - the big electricity - section ... Lian Bo can ^ 'the value of the brother - capacitor Ci to cut. The sixth period t6 and the seventh period 0 pp 13 and the fourth period 14 'Qing:: the same as the third period Ming m 8 figure, which shows the use of the display panel shift (four) #弟-贞examples. The driver stage σ_ - (four) moving stage circuit element 114, a discharge unit ml:: two charging singly unit (1), charging drive unit 114 and put: early: .... This charging is the same as that of the fifth embodiment of the first embodiment, and the core: 7" 115 construction compensation unit m-heart-driver level is: The level signal and the first-clock signal CLK": V12 output is lower in the fifth period of the lower graph _ - (such as the second ~ 112; continuous wave, 0J417-TW / A09017 201112203 can be used to drive the next level of driver stage The compensation unit 丨1 6 includes a first level first capacitor C ”7, an eighth opening unit and a package C2. The seventh switch end receives the first clock vocal ^ /, 啕弟一Μ 1 〇 CLK1, a second end of the second pass through a first: point P interesting to the first switch of the charging unit 113 - the first: the control terminal is lightly connected to the first node p of the charging drive single & 114. The eighth The switch 8 has a first node connected to the first driving node of the charging driving unit, and a second terminal coupled to the output terminal (1). A control terminal receives the first clock signal CLK "i, the first-clock signal CLK is converted from a low level to a high level; during the period three, the eighth switch T8 is turned on and the charge of the node Ρ! of the charging driving unit 114 is discharged to the output terminal 112. During the output of the low level, the driver stage 11' can reduce the coupling of the first node 受到 by the first clock signal CLK]# and switch to the high level. The first capacitor C2 is connected to the first node Ρι of the charging driving unit 114, and the other end is connected between the far first point P2 and the first node p! — When the 'k' CLKi is converted to the local level (the potential is, for example,
Vi) ’則該第一節點Pi之耦合電位Vp丨可以式（1)表 示： νΡι=νι X [cgs7/(Cgs7+Cgd7+Cgs1+C2)]+Vp2 χ [(Cgd7+CgSi+C2)/(Cgd7+CgSi + C2+Cgd1+C1)] (1) 其中，Cgs?及CgA分別為該:第七開關丁7之閱 014 丨 7-TW/A09017 14 201112203 極姻間之雜散電容;eg…扯 之雜散電：：關Tl之閘極-源極間及閘極-汲極間 動級心輸出高準位時，較大 電能乂 一開關Tl及該第七帆之充 力’反之’當該驅動級…於輪 小的vPi可降低該輸出端u =率又 中’為降低製作時電容所佔用：達波。於一貫施例 第-雷六r h谷所佔用的面積’可僅製作該 弟一電合c2而省略該第一電容 該輪出.端m等效上係相二中 因此該苐二節點p2之電位纟 2 出端U 2的電位變化' (SWing)係高於該輸 ㈣:及之驅動能力’可選擇將第二節點p2輕接至下及 、·及石動級之輸人端U1以驅動該下—級驅動級。 因本發明第二實施例之用於顯示、面 位暫存器則可顯示如第9圖所示，苴一 々夕 之第二節.點卩2之輸出係作為 =11 號。此外，其爾夕連接方動級之輸入信 示，故於此不再二.广接“則相同於第4圖所 μ同％參妝弟8至1〇圖所示，第⑺圖 及驅勤級之操作時序圖，其與以圖:差 異土要在於第二期間h及第五期間匕。 於第-期間h，該充電驅動 端⑴接收-輸入信號啊之高準位脈 - · ： ··. ίVi) 'The coupling potential Vp of the first node Pi can be expressed by the formula (1): νΡι=νι X [cgs7/(Cgs7+Cgd7+Cgs1+C2)]+Vp2 χ [(Cgd7+CgSi+C2)/ (Cgd7+CgSi + C2+Cgd1+C1)] (1) where Cgs? and CgA are respectively: the seventh switch D.7 014 丨7-TW/A09017 14 201112203 The stray capacitance between the marriages; ...to the stray electricity:: off the gate of Tl - between the source and the gate - the transition between the gate and the drain of the pole is higher, the larger power, the switch Tl and the force of the seventh sail' 'When the driver stage...the small vPi in the wheel can reduce the output u = rate in the middle' to reduce the capacitance occupied by the production: Dabo. In the consistent application of the area occupied by the first - Rayhrh Valley, it is only possible to make the brother a union c2 and omit the first capacitor. The end m is equivalent to the phase two, so the second node p2 The potential change of the potential 纟2 at the end U 2 ' (SWing) is higher than the input (four): and the driving ability 'can select the second node p2 to be connected to the lower end, and the input end U1 of the stone moving stage to drive The lower-level driver stage. According to the second embodiment of the present invention, the display and the surface register can be displayed as shown in Fig. 9. The output of the second section of the first point is the number =11. In addition, the input signal of the erection connected to the moving level is therefore no longer two. The splicing "is the same as the drawing in Figure 4, the same as the % ginseng mate 8 to 1 〇, the picture (7) and drive Operational timing diagram of the diligent level, and its diagram: the difference between the two is the second period h and the fifth period . During the period - period h, the charging driver (1) receives the high-level pulse of the input signal - · : ··. ί
01417-TW/A090U 201112203 該第六開關τ _ CLK^ T T 此守5亥充電驅動單元114之 2、丁6均開啟並將該第一節點ρ :’關 位，該充電單 〃 充電至向準 116之第七門 弟一開關Tl以及該補償單元 叫至^關//被開啟而轉合該第—時脈信號 〆弟—民卢點P2及該輸出端1工2 〇 二 信號CLK3同日丰門龄兮士πο 〇Λ弟二4脈 以传… 電早元115之第五開關Τ5 M H端112輕接至該電源VSS。該第一時脈01417-TW/A090U 201112203 The sixth switch τ _ CLK^ TT 2, 2, D, 6 of the 5H charging drive unit 114 are turned on and the first node ρ: 'closed, the charging unit is charged to the standard 116 seventh brother-in-one switch Tl and the compensation unit called to ^ off / / is turned on and the first - clock signal brother - Min Lu point P2 and the output end 1 2 signal CLK3 with Rifeng Age gentleman πο 〇Λ弟二四脉传... The early switch of the electric early 115 Τ5 MH end 112 is lightly connected to the power supply VSS. The first clock
電位為低準位而關閉該第八開關I 即‘”、P2及輸出端112之電位在此 準位。此外，忐於兮结__ 士 / J J句低 Μ 由於5亥弟一日守脈信號CLK2為低準位而 關閉該第三開關T3及該第四開關丁4。.， | ，二第間t2 ’輸入信號1NPUT及第三時脈信 唬clk3均轉換為低準位而關閉該充 =叫丁6以及該放電單元115之第五開關T5: .0\417-TW/Α09017 :!二時脈信號叫仍維持為低準位而關閉該放 =凡115之開關Τ3、Τ4。該第一時脈信號m ^夺轉換為高準位，於暫態期間，該第—時脈信號 ^ 3先開啟該補償單元116之第八開關τ8而將 充電驅動單S114之第―節⑽之部分電荷放電 至§玄輸出㉟112;接著於穩態期間，該第一節點P1 之電位根據式⑴之叙合效應再度拉升而仍維持於 高準位並開啟該等開關T1、.T7。應該了解的是，由 於邊第-節點Ρ,之電荷部分已放電至該輸出端112 16 201112203 C!:時脈信號CLKi之電壓受到該等開關 合效庫：】：C2、C1所分享，該第—節…搞 ^心升之電壓小於第6圖之第二期 =二此’該第二節點P2及輸出端⑴被該第 輸出二：二Μ充電至高準位，藉此該輸出端112 构出间準位之輸出脈衝信號至一顯示面杯夕一播 描線；該第二節點p並輸古立 一驅動級4位之脈衝信號下 m :::期間t3及第四期間t4 ’該充電驅動單元 號⑴放電絲準似㈣—時脈信 琴驅動麵丨因此該補償單元116不動作。 實：心Γ此期間中各元件之動作類似於第- 故於此不再費述。第-期間t3及第吻“’ 位而輸入信號1_T仍維持為低準 動單元114之第二開關丁2。該第 一和·脈k號CLK2仍难介.准， 元出之_ T,、^ U財位而關閉該放電單 為低，位而4。该第三時脈信號CLK3轉換 為低早位而關閉該充雷 及該放電單元115之二u，開關L CLK,轉換為高準位 ^ 5 °亥弟—時脈㈣ ⑽首先開啟該卿暫=間，該第-時脈信號 該充電驅動單元i Η之；1 ^之第八_ T8而將 弟一即點ρι之部分電荷放電 r ^ 01417-TW/A09017 17 201112203 2該輸出端⑴;接著於 點匕之電荷部分已放電至由於°亥第-即 時脈俨轳Γτπ ^ 。"輪出缒112以及該第一 脈^cuc,之·受到該 c” C丨所分享（式υ 7 1及兒合 廊所抽斗夕+厂 亥第—郎點Pi因耦合效 應所拉升之電壓可小於第6圖 成 者。該輸出端m於此期間 動揭不 償單元116之第-節點p 电位擾動直接由該補 々々抓 2之電位所決定，且爷篦- 即點p2之電壓僅為該第—時脈俨 以弟- 壓。因此，第10圖中，者节駿^ 1之部份分 位期η 士七、 田°亥15動級11 '於輸出低準 位期間，由於該等節點 時脈俨跋η κ 2之％位均小於該第一 观唬cLKl之電壓，因 有效地被減少。 勒出知112之漣波可 第六期間k及第七期間 , Μ第四期間V，故於此不再贅刀述別相同於第三期間 期間：發了施财’由於三個時脈信號, 中的兩個時芽四』間、和第五期間t5) 間U)該輪出端H2均屬接至3 3和弟四期 出端112 >姑ΛΑ “ " 為電深VSS ’所以該輸 • U /予接的吟間僅為33 3%。心成 於輸出低準位時，受到此外，驅動級『 得該輪出蠕116之補償而使 之用du圖所示，其顯示本發明第三實施例 、⑽r移㈣存級轉級.之電路 01417-T W / A09012 201112203 圖’其與本發明第二實施例之差異在於第三實施例 係使用兩時脈信號，例如一時脈信號CLK及一反相 時脈信號CLKB，且該時脈信號Clk與反相時脈信 號CLKB係彼此反相。驅動級]Γ，同樣包含一充電 早元113 充電驅動早元114、一放電單元115及 一補償單元116 ;其中該充電單元113、充電驅動單 元114及補償單元116之連接方式類似於第二實施 例之第8圖，故於此不再贅述。該放電單元丨丨5根 據該反相時脈信號CLKB以消除該第一節點Ρι及該 輸出端112於該時脈信號c L κ為低準位時之浮接^ 形。該放電單元115包含-第三開關Τ3及一第四開 關14 ’ ^第三開關丁3具有一第一端耦接該輪出端 112、一第二端耦接該電源Vss : 相時崎CLKB,當該反相時脈信 :位日夺，或輪出端112透過該第三開關^向該電源 ss放電。該第四開關T4具有—第—端耦接： 驅動單元1 i 4之第一 ^ 充电 v 弟即點Pl、一弟二端耦接該電调 ss及一控制端耦接該驅動級 Λ、 補償單元U6之第-、針ρ, + 他動級之 1盔古唯 2，當該第二節點IV之 位為南準位時，兮楚一 ,了 4弟一即點透過該第四開闕τ 向該電源Vss放電。 间關 示，第12圖顯示第 請同時參照第1ί及12圖所 11圖之一級驅動級之操作時序圖 ' 0J417-TW/A09017 19 201112203 山於第一期間，該充電驅動單元114自該輸入 端^1接收一輸入信號IN P U T之高準位脈衝並透過 第/、開關Τό之控制端接收該反相時脈信號clkb 之高準位脈衝。此時，該充電驅動單元114之開關 丁2、丁6均開啟並將該第一節點ρι之電位充電至高準 位’該★充電單元113之第一開關Τι以及該補償單元 116之第七開關了7被開啟而耦合該時脈信號CLK至 :第一節點Pa及該輪出端〗丨2。該時脈信號之 電位為低準位而關閉該第八開關T8,該第二節點p2 及輸出端112之電位在此期間均為低準位。此外， 由於該反相時脈錢CLKB為高準位而開啟該第三 開關τ3而使該輪出端112耦接該電源vss。第一期 1 ^中下驅動級之第二節點p/為低準位而關閉 §亥弟四開關τ4。 於第二期間t2，輸入信號INPUT及反相時脈信 號CLKB均轉換為低準位而關閉該充電驅動單元 ⑴之開關了2、了6以及該放電單元115之第三開關 丄3。該時脈信號C L K此時轉換為高準# ,於暫態期 間’該時脈信號咖首―啟該補償單it m之第 八開關T 8而將該充雪酿如gg - ,，^ /兄4驅動早兀丨14之第一節點p丨 之4刀電何放電至該輸出端112;接著於穩態期間， 該第一節.點Ρ,之電位根據式⑴之耦合效應再度拉 升而仍維持於高準位並開啟該開關W7。應該了 解的是’由於該第一節點P!之電荷部分已放電至該 01417-TW/A09017 20 201112203 輸出端U2以及該時脈信 關τ7、Τι及電容C2、Ci所之；^到該等開 搞合效應所㈣之電料於第6圖^_ ==因 揭示者。因此，談篦_ P d間t2中所 脈信號CLK充電至5準^ t2及輸出端112被該時 电芏间早位，稭此該輪 -高準位之脈衝信號至—顯 則出 第-銘D、，认， 攸之* —知描線；該 點p2亚輪出一高準位之脈衝信號至下 二端⑴。第二期間t2中，下—驅動級之第 —2’為低準位而關閉該第四開關Τ4β 而關=3間t3，該輸入信號INPUT為低準位而 關閉该充電驅動單元114之 :脈信號咖轉換為高準位而開 Γ:該輪出㈣透過該第開關電； 之;低準饮。第三期間τ’3中’該風動級U" ^ 一驅動級之第二節，點ρ2"轉換為高準位而開啟 W四開關丨4而使得該充電驅動單元114镇—Μ 點Ρ !被放電至低準㈣關閉該開 ϋ 信號CLK肤Β士 Μ Ί -往， 邊^脈 哙轉換為低準位而關閉該第八開關 8，因此該補償單元116不動作。 "" 位而間U’輸入信號1NPUT仍維持為低準 而關_充電驅動料114之第二開關 ，時脈信號CLKB轉換為低準位而_該充電驅動 早7L 114之第六開關Τό及該放電單元115之第三開 01417-TW / A09Q17 21 201112203 二信號CLK轉換為高準位，於㈣期 八開…將該充電:動=償二元-之第 由於該第-節點^之電巧二，接者於穩態期間， 112以及該時脈信號CLK:;=電；該輸出端 T丨及電容C2、（^所分享（式I又°亥寻開關丁7、 因耦合效應所拉升之電壓；’因此該第-節點P, 中所揭-土 小於第6圖第5期η t 中所揭不者。且該輸出端112於 H5 直接由該補償單元116 奸/ 4之電位擾動 定，且該第二節點p2之：:點？2之電位所決 之部份分壓。因此，第u 4；^脈信號CLK. 於輸出低準位期間，由於、當該級驅動級IV， 小於該時脈信號CLK之電麗即準位P:,P2,電位均 U2之漣魂可有效地被減少。 因此3輸出端 乂弟五期間t5及第七期間卜中艇動 之助作類似於第三期間ts;第六 、， 。凡件 各元件之動作類似於第:a t6中驅動級1 於太η " 』間心故於此不再贅述。 方；本發明之第三實施例 間（例如，第三期間丈3和第四心f兩個時脈信號期 信號期間（例如’第三期間）B t4)中的—個時脈 電源Vss，所以該輸出端112端112耦接至該 此外，該驅動'級於輪出低予广時間僅為5〇%。 _奴時，受到該補償 0I4I7-TW/A09017 22 201112203 σσ 早元 波。 116之補償而使得該輪出端 U2具有較低之漣 -別丨处，由於習知 之輪出端浮接時間長且輪出：顯示器之移位暫存器 動，因此容易導致其所:明顯之樹 形。本發明提出另一種用於4:現誤彭作的情 (第8及11圖），其透過‘ 移位暫存器The potential is at a low level and the eighth switch I is turned off, that is, the potentials of '', P2, and output terminal 112 are at this level. In addition, the 忐 _ _ _ 士 / J J 句 Μ Μ Μ Μ Μ Μ Μ The signal CLK2 is at a low level, and the third switch T3 and the fourth switch 4 are turned off. . . , |, the second t2 ' input signal 1NPUT and the third clock signal clk3 are both converted to a low level and the signal is turned off. Charge = D6 and the fifth switch T5 of the discharge unit 115: .0\417-TW/Α09017: The two-clock signal is still maintained at a low level and the switch is turned off. The first clock signal m ^ is converted to a high level. During the transient period, the first clock signal ^ 3 first turns on the eighth switch τ8 of the compensation unit 116 and drives the first section (10) of the charging unit S114. A portion of the charge is discharged to the sigma output 35112; then, during the steady state, the potential of the first node P1 is again pulled up according to the summation effect of the equation (1) while still maintaining the high level and turning on the switches T1, .T7. It should be understood that due to the edge-node Ρ, the charge portion has been discharged to the output terminal 112 16 201112203 C!: The voltage of the clock signal CLKi is subjected to The switch effect library:]: C2, C1 share, the first section... the voltage of the heart rise is less than the second phase of the sixth figure = two this 'the second node P2 and the output end (1) are the first Output 2: the second battery is charged to a high level, whereby the output terminal 112 constructs an output pulse signal of the inter-level position to a display surface of the display line; the second node p and the input of the ancient driver-level 4 position Under the pulse signal m:: period t3 and the fourth period t4 'the charging drive unit number (1) the discharge wire is quasi-like (four) - the clock letter driving surface, so the compensation unit 116 does not operate. The action of the component is similar to the first - so it will not be described here. The first period t3 and the first "t" and the input signal 1_T remain as the second switch 2 of the low snap-action unit 114. The first and · pulse k number CLK2 is still difficult to pass. Quasi, the yuan out of the _ T, , ^ U financial position and close the discharge order is low, bit and 4. The third clock signal CLK3 is converted to a low early position to turn off the charging and the discharge unit 115, and the switch L CLK is converted to a high level ^ 5 °Hai - the clock (four) (10) first open the Qing = between, the first-clock signal of the charging drive unit i; 1 ^ the eighth _ T8 and the younger one point ρι partial charge discharge r ^ 01417-TW / A09017 17 201112203 2 the output end (1); Then the portion of the charge at the point 已 has been discharged to due to the °H-immediate pulse 俨轳Γππ ^ . "Turn out 缒112 and the first pulse ^cuc, which is shared by the c" C丨 (Formula 1 7 1 and the children's gallery 抽 夕 夕 + Factory Haidi - Lang point Pi is pulled up by the coupling effect The voltage may be smaller than that of the figure 6. The output terminal m during this period of the first node p potential disturbance of the uncovering unit 116 is directly determined by the potential of the patch 2, and the grandfather - point p2 The voltage is only the first-clock 俨 弟 弟 。 。 。 。 。 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 ^ ^ ^ ^ During this period, since the % of the node 俨跋η κ 2 is less than the voltage of the first 唬 唬 cLK1, it is effectively reduced. The 涟 wave of the known 112 can be the sixth period k and the seventh period, Μ The fourth period V, so this is no longer the same as during the third period: the implementation of the 'four clock signals, two of the four buds, and the fifth period t5) Inter) U) The round end H2 is connected to 3 3 and the fourth phase of the terminal 112 > aunt " " is the electric depth VSS ' so the input / U / pre-connected only 33 3%. When the heart is at the output low level, in addition, the driver stage is compensated by the wheel 116 and is shown by the du diagram, which shows the third embodiment of the present invention, (10) r shift (four) storage level conversion. Circuit 01417-TW / A09012 201112203 FIG. 2 differs from the second embodiment of the present invention in that the third embodiment uses two clock signals, such as a clock signal CLK and an inverted clock signal CLKB, and the clock signal Clk and the inverted clock signal CLKB are inverted from each other. The driving stage] 同样 also includes a charging early 113 charging driving early element 114, a discharging unit 115 and a compensation unit 116; wherein the charging unit 113, the charging driving unit 114 and the compensation unit 116 are connected in a manner similar to the second implementation The eighth figure of the example is omitted here. The discharge cell 丨丨5 is based on the inverted clock signal CLKB to eliminate the floating pattern of the first node 及 and the output terminal 112 when the clock signal c L κ is at a low level. The discharge unit 115 includes a third switch Τ3 and a fourth switch 14 ′. The third switch 3 has a first end coupled to the wheel end 112 and a second end coupled to the power source Vss: phase aki CLKB When the inverted clock signal: bit annihilation, or the wheel terminal 112 discharges through the third switch ^ to the power source ss. The fourth switch T4 has a first-end coupling: a first charging terminal of the driving unit 1 i 4 is a point P1, a second terminal is coupled to the electrical ss, and a control terminal is coupled to the driving stage, The first and the second of the compensation unit U6, the needle ρ, + the first level of the other level of the helmet, when the second node IV is the south level, the Chu Chuyi, the 4 brothers, the point through the fourth opening阙τ discharges to the power source Vss. In the first period, the charging drive unit 114 is input from the input stage of the first stage and the first stage of the drawing of the first and second stages of the figure 11A. The terminal 1 receives a high-level pulse of the input signal IN PUT and receives the high-level pulse of the inverted clock signal clkb through the control terminal of the /, switch 。. At this time, the switches 2 and 4 of the charging driving unit 114 are both turned on and the potential of the first node ρι is charged to a high level 'the first switch 充电 of the charging unit 113 and the seventh switch of the compensation unit 116 7 is turned on to couple the clock signal CLK to: the first node Pa and the round-out terminal 丨2. The potential of the clock signal is at a low level to turn off the eighth switch T8, and the potentials of the second node p2 and the output terminal 112 are all low levels during this period. In addition, the third switch τ3 is turned on because the inverted clock CLKB is at a high level, so that the round terminal 112 is coupled to the power source vss. In the first period, the second node p/ of the lower-level driver stage is turned off at a low level. § Haidi four-switch τ4. During the second period t2, both the input signal INPUT and the inverted clock signal CLKB are converted to a low level to turn off the switches 2, 6 of the charging drive unit (1) and the third switch 丄3 of the discharge unit 115. The clock signal CLK is converted to a high level # at this time, and during the transient period, the clock signal is the first switch T 8 of the compensation unit it m and the snow is filled as gg - , , ^ / Brother 4 drives the first node of the early 14th, which is discharged to the output terminal 112; then during the steady state, the first node, the potential, is again pulled up according to the coupling effect of the equation (1). While still maintaining the high level and turning on the switch W7. It should be understood that 'because the charge portion of the first node P! has been discharged to the 01417-TW/A09017 20 201112203 output terminal U2 and the clock signal τ7, Τι and the capacitor C2, Ci; ^ to these The electric material of (4) is in the sixth picture ^_ == because of the revealer. Therefore, the signal CLK of t2 in t2 is charged to 5 quasi-t2 and the output end 112 is prematurely connected by the electric current, and the pulse signal of the round-high level is displayed to the first - Ming D,, recognize, 攸 * * Know the line; this point p2 sub-pulse a high-level pulse signal to the next two ends (1). In the second period t2, the second-lower driving stage of the second-lower driving stage turns off the fourth switch Τ4β and turns off=3, t3, and the input signal INPUT is at a low level to turn off the charging driving unit 114: Pulse signal coffee is converted to a high level and opened: the round (4) through the first switch;; low drink. In the third period τ'3, the wind stage U" ^ the second section of the driver stage, the point ρ2" is converted to the high level and the W four switch 丨4 is turned on to make the charging drive unit 114-- ! is discharged to the low level (4) to turn off the opening signal CLK skin Μ Ί - to, the side pulse 哙 turns to the low level and closes the eighth switch 8, so the compensation unit 116 does not operate. "" The U' input signal 1NPUT remains low and closes _ the second switch of the charge drive material 114, the clock signal CLKB is converted to a low level and the charge switch drives the sixth switch of 7L 114第三 and the third opening of the discharge unit 115 01417-TW / A09Q17 21 201112203 The two signals CLK are converted to a high level, and the (four) period is eight open... the charging: the motion = the binary - the first due to the first node In the steady state, 112 and the clock signal CLK:; = electricity; the output terminal T 丨 and the capacitor C2, (^ share (the I and ° 亥 开关 丁 、 7, due to coupling effect The voltage that is pulled up; 'so the first node P, the soil is less than the one shown in the fifth phase η t of Figure 6, and the output 112 is directly stalked by the compensation unit 116 at H5 / 4 The potential disturbance is fixed, and the partial voltage of the second node p2:: the potential of the point 2 is divided. Therefore, the u 4; ^ pulse signal CLK. during the output low level, due to, when The driver stage IV, which is smaller than the clock signal CLK, is the level P:, P2, and the potential of the U2 is effectively reduced. Therefore, the output of the clock is t5 during the period of 5 During the seventh period, the movement of the boat is similar to the third period ts; sixth, the action of each component is similar to the first: a t6 driver level 1 is too η " Further, in the third embodiment of the present invention (for example, the clock period of the two periods of the third period and the fourth heart f (for example, the 'third period) B t4) The power supply Vss, so the output end 112 of the output terminal 112 is coupled to the other, the drive 'level is only 5〇% in the round-out low-width time. _ slave time, subject to the compensation 0I4I7-TW/A09017 22 201112203 σσ early yuan The compensation of the wave 116 makes the round end U2 have a lower 涟--the other end, because the conventional wheel-out terminal floats for a long time and turns out: the shift register of the display moves, so it is easy to cause : Apparent tree shape. The present invention proposes another kind of situation for the 4: error (8th and 11th drawings), which is transmitted through the 'shift register
少輪出電位之漣波。補償單元，可有效減 以限以前述實施例揭示，然其並非用 常知m 何本發明所屬技術領域令具有通 …離本發明之精神和範圍 可 後附之申請專利範圍所保讓範圍當視Less rounds of potential ripple. The compensation unit can be effectively reduced by the above-mentioned embodiments, but it is not a matter of general knowledge, and the scope of the patent application scope can be extended from the spirit and scope of the present invention. Vision
01417-TW/A09017 23 201112203 【圖式簡單說明】 第1圖顯示一種習知用於液晶顯示器之移位暫存器 之方塊圖。 β 弟2圖減示苐1圖中一級驅動級之電路圖。 第3圖顯示第2圖之一級驅動級之操作時序圖。 第4圖顯示本發明第一實施例之用於顯示面板之移 位暫存器之方塊圖。 第5圖顯示第4圖中一級驅動級之電路圖。 第6圖顯示第5圖之一級驅動級之操作時序圖。 第7圖顯示第5圖之一級驅動級之操作示意圖。 第8圖顯示本發明第二實施例之用於顯示面板之移 位暫存器之一級驅動級之電路圖。 第9圖顯示本發明第二實施例之用於顯示面板之移 位暫存器之方塊圖。 第1 〇圖顯示第8圖之一級驅動級之操作日|序圖。 第11圖顯示本發明第三實施例之用於顯示面板之 移位暫存器之一级驅動級之電路圖。 第12圖顯示第1丨圖之一級驅動級之操作時序圖。 .11、1Γ、1Γ 一級驅動級 112 輸出端 114 充電驅動單元 116 補償單元 CLKi〜CLK3時脈信號 【主要元件符號說明】 10移位暫存器 111 輸入端 113 115 20 充電單元 放電單元 時脈產生器 0141Z-TW/A09017 201112203 Τι~Τ8 開關 電容 INPUT輸入信號 CLK、CLKB時脈信號 9 移位暫存器 Vdd 正電壓源 SW广sw6開關元件 ti~t7 期間 Ρ!、P2節點 OUTPUT輸出信號 P2' 下一驅動級之第二節點 91 一級驅動級01417-TW/A09017 23 201112203 [Simplified Schematic] FIG. 1 shows a block diagram of a conventional shift register for a liquid crystal display. The β brother 2 diagram shows the circuit diagram of the first-level driver stage in the 苐1 diagram. Figure 3 shows the timing diagram of the operation of the one-level driver stage of Figure 2. Fig. 4 is a block diagram showing a shift register for a display panel in the first embodiment of the present invention. Figure 5 shows the circuit diagram of the primary driver stage in Figure 4. Fig. 6 is a timing chart showing the operation of the one-stage driver stage of Fig. 5. Fig. 7 is a view showing the operation of the one-stage driving stage of Fig. 5. Figure 8 is a circuit diagram showing a stage-level driving stage of a shift register for a display panel in accordance with a second embodiment of the present invention. Figure 9 is a block diagram showing a shift register for a display panel in accordance with a second embodiment of the present invention. Figure 1 shows the operating day | sequence diagram of the first-level driver stage in Figure 8. Fig. 11 is a circuit diagram showing a one-stage driving stage of a shift register for a display panel in accordance with a third embodiment of the present invention. Figure 12 shows the timing diagram of the operation of the first-level driver stage of Figure 1. .11,1Γ,1Γ Primary driver stage 112 Output terminal 114 Charging drive unit 116 Compensation unit CLKi~CLK3 Clock signal [Main component symbol description] 10 Shift register 111 Input terminal 113 115 20 Charge unit discharge unit clock generation器 014 014 014 014 014 014 014 014 014 The second node of the next driver stage 91
Vss 電源 P、P 節點Vss power P, P node
01417-TW/A0901701417-TW/A09017