CN100578306C

CN100578306C - Liquid crystal display device

Info

Publication number: CN100578306C
Application number: CN200710096909A
Authority: CN
Inventors: 李栢远; 文胜焕
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2002-04-08
Filing date: 2003-04-04
Publication date: 2010-01-06
Anticipated expiration: 2023-04-04
Also published as: KR20030080979A; KR100860239B1; CN101038384A

Abstract

A driver circuit drives display device and LCD device has a driver circuit that includes driving stages and dummy stage. The driving stage includes output and control terminals. The output terminal of the present stage is connected to the control terminal of the previous state to be cascade-connected each other. The driving stage outputs driving signal for controlling the switching device arranged on the display device through the output terminal. The dummy stage includes dummy output terminal and dummy control terminal. The dummy output terminal is connected to the control terminal of the last driving stage to output dummy output signal for turning on or off the last driving stage. The dummy control terminal is connected to the dummy output terminal to be turned on or off by the dummy output signal. The delay of signals is reduced, thereby enhancing display quality.

Description

LCD

The application be that April 4, application number in 2003 are 03800881.5 the applying date, denomination of invention divides an application for the application of " LCD ".

Technical field

The present invention relates to a kind of driven with active matrix display of driving the driving circuit of driven with active matrix display and having this driving circuit of being used to, more specifically, relate to and a kind ofly improve the driving circuit of display display quality and have the LCD of this driving circuit.

Background technology

Usually, polysilicon LCD (LCD) has high travelling speed and consumes low electric power, but needs to make the working procedures of polysilicon LCD.The general display that the polysilicon LCD is used for having small screen size.The general display that the amorphous silicon LCD is used for having screen sizes, for example, laptop computer (or notebook), liquid crystal display monitor, high-definition television (HDTV ' s).

Recently, the amorphous silicon LCD is utilized at the glass substrate (or thin-film transistor substrate) of LCD and is gone up the formation gate driver circuit, so that reduce the operation of making LCD.

Usually, gate driver circuit comprises shift register and wiring portion.Wiring portion offers register with a plurality of signals.Wiring portion comprises many wirings, and the layout of wiring will influence the output signal by gate driver circuit output.Because the mutual intersection generation of wiring electric capacity can cause the output signal distortion from gate driver circuit.Therefore, the display quality of LCD can reduce.

When gate driver circuit is used to have screen sizes (big picture) and high-resolution amorphous silicon LCD, be formed at the on-chip traditional gate drivers of thin film transistor (TFT) (TFT) and have following problems.

Become according to the screen size of LCD and to maximize and the resolution of LCD when improving, gate line that forms on thin-film transistor substrate and the pixel quantity that is connected to gate line also increase thereupon.Along with the increase of gate line and pixel, postpone also to become big apart from the RC of gate drivers gate line far away more thereupon, more near last gate line, it is also elongated to have the interval constant time lag time of taking place of high level from first gate line.Owing to this reason, the distortion of grid output signal takes place.Therefore, reduce the display quality of LCD.

And, produce electric capacity being arranged at away from driving circuit and having between the wiring of high line width.Correspondingly, the RC of wiring postpones to improve.Therefore, need to be provided with the wire structures that transmits gate drive signal with the minimum delay to gate line.

Summary of the invention

Therefore, the present invention has avoided substantially because one or more problems that limitation and defective caused of correlation technique.

First feature of the present invention provides a kind of driving circuit that is used to drive the driven with active matrix display that improves the display quality of display.

Second feature of the present invention provides a kind of LCD with above-mentioned driving circuit.

The 3rd feature of the present invention provides a kind of display with wire structures of the display quality that can improve display.

In one aspect of the invention, provide a kind of driving circuit that is used to drive the driven with active matrix display.This driving circuit comprises a plurality of driving sections and virtual segment (dummystage).Each drives section and comprises lead-out terminal and control terminal.The output terminal of present segment is connected with the control terminal of previous state, is connected in series to form each other, and each drives section and is used for the gauge tap device by the lead-out terminal output drive signal.Switchgear is arranged on the driven with active matrix display.Virtual segment comprises dummy output terminal and virtual controlling terminal.The control terminal of the driving section that dummy output terminal is sub and last is connected with the output virtual output signal and is used to be switched on or switched off last driving section between the driving section.The virtual controlling terminal is connected to be switched on or switched off by virtual output signal with dummy output terminal.

In another aspect of the present invention, provide a kind of LCD, this LCD comprises display part and gate drivers.Display unit comprise first substrate, in the face of second substrate of this first substrate and place first substrate and second substrate between liquid crystal layer.First substrate have be formed at pixel on many gate lines being connected of switchgear, and pixel arranged with the matrix form.The gate driver drive switchgear, and gate drivers comprises a plurality of driving sections and virtual segment.Each drives section and has lead-out terminal and control terminal.The lead-out terminal that to work as the front wheel driving section is connected to be connected to each other with the control terminal of previous state.Driving section will be used for being transported to each gate line by the drive signal of lead-out terminal gauge tap device.Virtual segment comprises dummy output terminal and virtual controlling terminal.The driving section that dummy output terminal is sub and last is connected with the output virtual output signal and is used to be switched on or switched off last driving section between the driving section.The virtual controlling terminal is connected to be switched on or switched off by virtual output signal with dummy output terminal.

In another aspect of the present invention, provide a kind of LCD, this LCD comprises display part, data driver and gate drivers.This display part comprises: i) first substrate, have pixel, gate line and data line, and pixel has the switchgear that is connected with data line with gate line, ii) second substrate, in the face of first substrate, and iii) liquid crystal layer, place between first substrate and second substrate.Data driver offers data line with view data, and data driver is connected in abutting connection with display part formation and with data line.Gate driving portion driving switch device.Gate drivers comprises shift register and wiring portion.Shift register has and is one another in series a plurality of sections that connect, and shift register is divided into first group and second group and forms in abutting connection with display part.Portion imposes on each section with external signal by wiring, and each drives section is used to control described switchgear to gate line output by lead-out terminal drive signal.Wiring portion comprises first clock line, second clock line, the 3rd clock line, reaches the 4th clock line.By first clock line first clock signal is offered first group odd number and drive section.To have the second clock signal that has 180 ° of outs of phase with respect to first clock signal by the second clock line offers first group even number and drives section.By the 3rd clock line first clock signal is offered second group odd number and drive section.By the 4th clock line the second clock signal is offered second group even number and drive section.

According to the present invention, the sub and last control terminal that drives section of the dummy output terminal of virtual segment is connected and is connected with the virtual controlling terminal of virtual segment.And except the wiring of first and second clock lines, cloth portion also comprises appends the 3rd and the 4th clock line that first and second clock is provided.This LCD can provide the display quality of raising.

Description of drawings

Above-mentioned and other advantage of the present invention will be by describing its preferred embodiment in detail with reference to the accompanying drawings, thereby become more obvious, wherein:

Fig. 1 is the display panels synoptic diagram of first exemplary embodiments according to the present invention;

Fig. 2 shows the block scheme of shift register of the driving grid driving circuit of Fig. 1;

Fig. 3 shows the circuit diagram of the driving section of Fig. 2;

Fig. 4 shows the driving segment layout planimetric map of Fig. 3;

Fig. 5 shows the circuit diagram of the virtual segment of Fig. 2;

Fig. 6 shows the virtual segment layout planimetric map of Fig. 5;

Fig. 7 shows virtual segment and drives section the oscillogram of virtual segment output signal when having same structure;

Fig. 8 shows the oscillogram of output signal of the virtual segment of Fig. 5;

Fig. 9 shows the driving section and the virtual segment structural circuit figure of second exemplary embodiments according to the present invention;

Figure 10 shows the block scheme of the shift register of the gate driver circuit of the 3rd exemplary embodiments according to the present invention;

Figure 11 shows the oscillogram of output signal of the gate driver circuit of Figure 10;

Figure 12 shows the layout of the 3rd and the 4th clock line arrangement of Figure 10;

Figure 13 shows the first and the 3rd clock line annexation and the second and the 4th clock line annexation layout;

Figure 14 shows the wire structures layout of the shift register of the 4th exemplary embodiments according to the present invention;

Figure 15 shows the shift register layout of the wire structures with Figure 14; And

Figure 16 shows the shift register wire structures layout of the 5th exemplary embodiments according to the present invention.

Embodiment

Describe the preferred embodiment of the present invention below with reference to accompanying drawings in detail.

Fig. 1 is the display panels synoptic diagram of first exemplary embodiments according to the present invention, and Fig. 2 shows the block scheme of shift register of the driving grid driving circuit of Fig. 1.

With reference to Fig. 1, the display panels of first exemplary embodiments comprises thin-film transistor substrate 100, color filter substrate (not shown) and places liquid crystal layer (not shown) between thin-film transistor substrate 100 and the color filter substrate according to the present invention.

Thin-film transistor substrate 100 has viewing area (DA) and neighboring area (PA).Arrange a plurality of pixels in the viewing area with the matrix form.Each pixel comprises thin film transistor (TFT) (TFT) substrate 100 and the pixel electrode 120 that is connected with thin-film transistor substrate 100.Thin-film transistor substrate 100 is connected with gate line (GL) with data line (DL).Data line extends along first direction, and gate line is along extending in the vertical second direction of first direction substantially.

Resolution according to number of pixels decision display panels 200.If a plurality of pixels have m*n, resolution is m*n, and have on the thin-film transistor substrate 100 m data line (DL1, DL2 ..., DLm) with n gate line (GL1, GL2 ..., GLn).

Be provided with data line (DL1, DL2 ..., DLm) the data side neighboring area (PA) of an end is provided with data drive circuit 140.Be provided with gate line (GL1, GL2 ..., GLn) the gate electrode side neighboring area (PA) of an end is provided with gate driver circuit 130.The operation that gate driver circuit 130 is identical with the operation of a plurality of pixels of (DA) formation in the viewing area forms.Gate driver circuit 130 comprises shift register.

As shown in Figure 2, shift register 131 comprise a plurality of sections of connecting of being one another in series (SRC1 ..., SRCn+1).Specifically, shift register 131 comprise the individual driving section of n (even number) (SRC1 ..., SRCn) and virtual segment (SRCn+1).

N drive section (SRC1 ..., SRCn) to n gate line (GL1, GL2 ..., GLn) export gate drive signal in turn.N drives each lead-out terminal of section OUT and is connected with the previous control terminal (CT) that drives section respectively.N drive section (SRC1 ..., the terminal (CR) that respectively transmits SRCn) is connected to the next section input terminal (IN) that drives.Provide the commencing signal (ST) that replaces output signal to first input terminal (IN) that drives section (SRC1).

The input terminal (IN) of virtual segment (SRCn+1) is connected on the transmission terminal (CR) of n driving section (SRCn).Lead-out terminal (OUT) then is connected to n control terminal (CT) that drives section SRCn.Therefore, virtual segment SRCn+1 controls n and drives section (SRCn) operation normally.The lead-out terminal (OUT) of virtual segment (SRCn+1) also combines with the control terminal (CT) of virtual segment (SRCn+1).Therefore, virtual segment (SRCn+1) is by the control signal control of self.

Have around the shift register 131 to shift register 131 various wiring lines portion 132 is provided.Specifically, wiring portion 132 comprises commencing signal line (STL), first power lead (VDDL), first clock line (CKL), second clock line (CKBL), reaches second source line (VSSL).

Commencing signal line (STL) provides the commencing signal that is provided by the outside (ST) to first input terminal (IN) that drives section (SRC1).Commencing signal (ST) is the pulse synchronous with vertical synchronizing signal that external graphics controller (not shown) etc. provides.First power lead (VDDL) drives section (SRC1 with n, ..., SRCn) and virtual segment (SRCn+1) connect and first power supply voltage signal (VDD) be provided, and second source line (VSSL) drives section (SRC1 with n, ..., SRCn) and virtual segment (SRCn+1) connect and second source voltage signal (VSS) be provided.

By first clock line (CKL) to n drive section (SRC1 ..., SRCn) in odd number drive section (SRC1, SRC3 ...) and virtual segment (SRCn+1) first clock signal is provided.By second clock line (CKBL) to n drive the Duan Zhongdi even number drive section (SRC2, SRCn ...) provide and have the second clock signal (CKB) that relative first clock signal (CK) has 180 ° of outs of phase (inverted phase).

Therefore, each section output signal (OUT1 ..., OUTn) have between active area (high level state) in turn and take place, be chosen in turn respectively output signal (OUT1 ..., corresponding gate line between active area OUTn) (GL1 ..., GLn).

Fig. 3 shows the circuit diagram of the driving section of Fig. 2, and Fig. 4 shows the driving segment layout planimetric map of Fig. 3.Pointed out typically at Fig. 3 and Fig. 4 to drive section (SRCn) the n time, and residue drive section (SRC1 ..., SRCn-1) drive section (SRCn) and have same structure with n, therefore omit residue drive section (SRC1 ..., related description SRCn-1).

With reference to Fig. 3 and Fig. 4, n of shift register 131 drive section (SRCn) comprise draw the 131a of portion (pull-up part), pull-down section (pull-down part) 131b, on draw drive division 131c, drop-down drive division 131d, and transmit efferent 131e.N drives section (SRCn) to be had input terminal (IN), lead-out terminal (OUT), control terminal (CT), clock terminal (CKT), second source line terminals (VSST), first power line terminal (VDDT), reaches and transmit lead-out terminal (CR).

On draw the 131a of portion to comprise first nmos pass transistor (NT1).Clock signal is imposed on the drain electrode of first nmos pass transistor (NT1), the grid of first nmos pass transistor (NT1) is connected with first node (N1), and the source electrode of first nmos pass transistor (NT1) is connected with lead-out terminal (OUT).

Pull-down section 131b comprises second nmos pass transistor (NT2).The drain electrode of second nmos pass transistor (NT2) is connected with lead-out terminal (OUT), the grid of second nmos pass transistor (NT2) is connected with Section Point (N2), and the source electrode of second nmos pass transistor (NT1) is connected with second source line terminals (VSST).

On draw drive division 131c to comprise capacitor (C), nmos pass transistor (NT3, NT4, NT5, NT6, NT7, NT8 and NT9).Capacitor C is connected between first node (N1) and the lead-out terminal (OUT).The 3rd nmos pass transistor (NT3) drain electrode is connected with first power line terminal (VDDT), and grid is connected with input terminal (IN), and source electrode then is connected with first node (N1).The 4th nmos pass transistor (NT4) drain electrode and grid are connected with first power line terminal (VDDT) jointly, and source electrode then is connected with the grid of the 5th nmos pass transistor (NT5).In addition, the 5th nmos pass transistor (NT5) drain electrode is connected with first power line terminal (VDDT), and grid is connected with the source electrode of the 4th nmos pass transistor (NT4), and source electrode then is connected with Section Point (N2).

The 6th nmos pass transistor (NT6) drain electrode is connected with the source electrode of the 3rd nmos pass transistor (NT3), and grid is connected with Section Point (N2), and source electrode is connected with second source line terminals (VSST).The 7th nmos pass transistor (NT7) grid is connected with Section Point (N2), drain electrode and input terminal (IN), and source electrode then is connected with second source line terminals (VSST).The 8th nmos pass transistor (NT8) drain electrode is connected with Section Point (N2), and grid is connected with input terminal (IN), and source electrode then is connected with second source line terminals (VSST).

Although not shown in Figure 3, the source electrode of the 8th nmos pass transistor (NT8) also can be connected to three power line terminal of reception than the 3rd power supply voltage signal of second source voltage signal (VSS) low voltage level.The 9th nmos pass transistor (NT9) drain electrode is connected with input terminal (IN), and grid is connected with control terminal (CT), and source electrode then is connected with second source line terminals (VSST).

Drop-down drive division comprises nmos pass transistor (NT10, NT11, NT12, NT13).Specifically, the tenth nmos pass transistor (NT10) drain electrode is connected with Section Point (N2), and grid is connected with first node (N1), and source electrode then is connected with second source line terminals (VSST).The 11 nmos pass transistor (NT11) drain electrode is connected with the source electrode of the 4th nmos pass transistor (NT4), and grid and first node (N1), source electrode then are connected with second source line terminals (VSST).The tenth bi-NMOS transistor (NT12) drain electrode is connected with first node (N1), and grid is connected with control terminal (CT), and source electrode then is connected with second source line terminals (VSST).

Transmit efferent 131e and comprise that drain electrode is connected with clock terminal (CKT), grid is connected with described first node (N1), the 14 nmos pass transistor (NT14) that source electrode then is connected with transmission lead-out terminal (CR).Therefore, transmit efferent 131e control and transmit clock signal corresponding in first and second clock signal (CK or CKB) to the input terminal (IN) that the next one drives section.

N drives in the section (SRCn), transmission signal (CR) by the previous paragraphs that received by input terminal (IN) is connected the 3rd nmos pass transistor (NT3), thereby the current potential of first node (N1) rises to first mains voltage level (VDD) from second source voltage level (VSS).Then, according to the current potential rising of the 4th nmos pass transistor (NT4), the 5th nmos pass transistor (NT5) and first node (N1), connect the tenth nmos pass transistor (NT10).Move the tenth nmos pass transistor (NT10), make the current potential of Section Point (N2) reduce to second source voltage level (VSS), disconnect second nmos pass transistor (NT2) thus.

Along with first nmos pass transistor (NT1) is connected in the current potential rising of first node (N1), thereby when lead-out terminal (OUT) begins to occur having the clock signal (CK) of turn-on level, output voltage is increased by capacitor (C), and the grid voltage of first nmos pass transistor (NT1) will rise to more than first mains voltage level.Therefore, first nmos pass transistor (NT1) also keeps complete conducting state thereupon.

When providing the virtual segment output signal that rises to turn-on level, connect the 12 and the 13 nmos pass transistor (NT12, NT13) by n control terminal (CT) that drives section (SRCn).

Connect the tenth bi-NMOS transistor (NT12), first node (N1) current potential will be reduced to second source voltage level (VSS) from first mains voltage level (VDD).Then, connect the tenth nmos pass transistor (NT10).Therefore, Section Point (N2) rises to first mains voltage level (VDD) by the 4th and the 5th nmos pass transistor (NT4, NT5) from second source voltage level (VSS).

Connect the 13 nmos pass transistor (NT13) from the virtual segment output signal that control terminal (CT) receives, the 13 nmos pass transistor of connecting (NT13) is then exported second source voltage level (VSS) to lead-out terminal (OUT) jointly with second nmos pass transistor (NT2).

The the 7th to the 8th nmos pass transistor (NT7, NT8) is under the state of lead-out terminal (OUT) outputting drive voltage first power supply voltage signal (VDD), and n-1 that provides to input terminal (IN) drives and just connect when a section output signal changes to turn-on level.

Specifically, under the state of lead-out terminal (OUT) output second source voltage level (VSS), when input terminal (IN) provides n-1 driving section output signal with turn-on level, the 8th nmos pass transistor (NT8) is also connected thereupon, drives the section output signal to n-1 that provides to input terminal (IN) simultaneously and discharges to second source line terminals (VSST).

And the 9th nmos pass transistor (NT9) connects and offers n-1 the driving section output signal that changes to turn-on level of input terminal (IN) to the virtual segment output signal that receives by control terminal (CT).Prevent the connection of first nmos pass transistor (NT1) thus.

Even the virtual segment output signal that applies by control terminal (CT) is reduced to and is disconnected level and disconnect the tenth bi-NMOS transistor (NT12), but Section Point (N2) is the state of first Yuan voltage level by the 4th and the 5th nmos pass transistor (NT4, NT5) maintenance bias voltage.Therefore, second nmos pass transistor (NT2) keeps on-state, and lead-out terminal (OUT) continues output second source signal (VSS).

Fig. 5 shows the circuit diagram of the virtual segment of Fig. 2, and Fig. 6 shows the virtual segment layout planimetric map of Fig. 5.In Fig. 5 and Fig. 6, for Fig. 1 in n drive section (SRCn) identical structural factor, and the identical drawing reference numeral of mark, and omit the explanation corresponding with it.

With reference to Fig. 5 and Fig. 6, virtual segment (SRCn+1) with n to drive section (SRCn) identical, comprise draw the 131a of portion, pull-down section 131b, on draw drive division 131c, drop-down drive division 131f, and transmit efferent 131e.Virtual segment (SRCn+1) has connected the lead-out terminal (OUT) of virtual segment (SRCn+1) though have and a n driving section same structure on the control terminal (CT) of virtual segment (SRCn+1).Therefore, virtual segment (SRCn+1) is by self output signal control.

Compare with n transistor specifications that drives the tenth bi-NMOS transistor (NT12) of section (SRCn), changed the transistor specifications of the tenth bi-NMOS transistor (NT12) that is connected with control terminal in the virtual segment (SRCn+1), so that keep the output signal of virtual segment (SRCn+1) in the given time.Below, transistorized specification is the ratio (W/L) of transistor channels length L and its width W.

For example, in the virtual segment (SRCn+1), the tenth bi-NMOS transistor (NT12) specification is approximately littler 10 times than n the tenth bi-NMOS transistor (NT12) specification that drives section (SRCn).

Usually, determined good length L, therefore transistorized specification is decided by width of channel W.For example, the width Billy who is used in the transistor (NT12 ') of virtual segment (SRCn+1) to be used in the width W of n the tenth bi-NMOS transistor (NT12) that drives section (SRCn) approximately little 10 times.As Fig. 4 and shown in Figure 6, the transistor of Fig. 6 (NT12 ') channel width than the tenth bi-NMOS transistor (NT12) channel width of Fig. 4 approximately less than 10 times.

Virtual segment (SRCn+1) needs the schedule time by having self output signal of turn-on level up to connecting transistor (NT12 ').That is,,, need the schedule time up to connecting transistor (NT12 ') by transistor (NT12 ') specification even rise to the control terminal (CT) that virtual segment (SRCn+1) output signal of turn-on level feeds back to virtual segment (SRCn+1).Therefore, the tenth nmos pass transistor (NT10) can directly not disconnect yet, so Section Point (N2) keeps second source voltage level (VSS) in the given time.Thereby the lead-out terminal (OUT) of virtual segment (SRCn+1) keeps turn-on level in the given time.

Through after the schedule time, connect the tenth two-transistor (NT12 '), corresponding its disconnects the tenth nmos pass transistor (NT10), and Section Point (N2) rises to first mains voltage level (VDD) from second source voltage level (VSS).Along with Section Point (N2) current potential rises to first mains voltage level (VDD), connect second nmos pass transistor (NT2), at virtual segment (SRCn+1) lead-out terminal (OUT) output second source voltage level (VSS).

And, in the virtual segment (SRCn+1), form the state of in n driving section (SRCn), removing the 13 nmos pass transistor (NT13) that is connected with control terminal (CT).As shown in Figure 6, removed the 13 nmos pass transistor (NT13) of Fig. 4.Therefore, only export second source voltage (VSS) to lead-out terminal (OUT), to postpone time to lead-out terminal (OUT) output second source voltage (VSS) at second nmos pass transistor (NT2) of on-state.

The oscillogram of virtual segment output signal when Fig. 7 shows virtual segment and drives section and have same structure, and Fig. 8 shows the oscillogram of output signal of the virtual segment of Fig. 5.X-axis express time (μ m), Y-axis is represented voltage (V).

With reference to Fig. 7, drive section in turn output have a high-voltage level output signal (OUTn-1, OUTn) afterwards, virtual segment (SRCn+1) brings into operation.In Fig. 7, virtual segment is formed with driving section same circuits, and the lead-out terminal of virtual segment is connected with the control terminal of virtual segment.At this moment, output signal (OUTn+1 ') from the virtual segment lead-out terminal becomes turn-on level by n output signal (OUTn) that drives section, simultaneously, the output signal (OUTn+1 ') that becomes turn-on level is provided to n respectively and drives section (SRCn) control terminal and self control terminal.

Self the output signal (OUTn+1 ') that provides by control terminal from the output signal (OUTn+1 ') of virtual segment lead-out terminal output is reduced to the disconnection level.Therefore, virtual segment output signal (OUTn+1 ') can not keep turn-on level in the given time, and directly drops to the disconnection level.That is, described virtual segment output signal (OUTn+1 ') maximum voltage is not enough to drive the maximum level value of section output signal (OUT) far away.

Yet as shown in Figure 8, if virtual segment (SRCn+1) is made up of circuit among Fig. 5, virtual segment output signal (OUTn+1) shows its stability.Drive section in turn output have a high-voltage level output signal (OUTn+1) afterwards, virtual segment (SRCn+1) operation.

Become turn-on level from the output signal (OUTn+1 ') of virtual segment (SRCn+1) lead-out terminal by n output signal (OUTn) that drives section, the output signal (OUTn+1) that becomes turn-on level simultaneously is provided to n control terminal that drives section (SRCn) control terminal and virtual segment (SRCn+1) respectively.

Then, even the control terminal by virtual segment (SRCn+1) provides output signal (OUTn+1), but the transistor specifications that is connected with the lead-out terminal of virtual segment (SRCn+1) is little, disconnects level and needs the schedule time so drop to from the output signal (OUTn+1) of virtual segment lead-out terminal output.Therefore, the output signal (OUTn+1) of virtual segment (SRCn+1) can keep turn-on level in the given time.

The output signal that is produced (OUTn+1) is almost the same with output signal (OUTn) to have high-voltage level.Therefore, n driving section (SRCn) can be carried out stabilized driving by the output signal (OUTn+1) of virtual segment (SRCn+1).

Fig. 9 shows the driving section and the virtual segment structural circuit figure of second exemplary embodiments according to the present invention.

With reference to Fig. 9, according to the shift register 133 of second embodiment of the invention comprise n drive section (SRC1 ..., SRCn) and virtual segment (SRCn+1).N drive section (SRC1 ..., SRCn) in n drive section (SRCn) comprise draw the 133a of portion, pull-down section 133b, on draw drive division 133c, reach drop-down drive division 133d.

On draw the 133a of portion to comprise first nmos pass transistor (NT1a).Clock signal (CK) is imposed on the drain electrode of first nmos pass transistor (NT1a), the grid of first nmos pass transistor (NT1a) is connected with first node (N1a), and the source electrode of first nmos pass transistor (NT1a) is connected with lead-out terminal (OUTn).

Pull-down section 133b comprises second nmos pass transistor (NT2a).The drain electrode of second nmos pass transistor (NT2a) is connected with lead-out terminal (OUTn), the grid of second nmos pass transistor (NT2a) is connected with Section Point (N2a), and the source electrode of second nmos pass transistor (NT2a) is connected with second source line terminals (VSST).

On draw drive division 133c to comprise capacitor (C), nmos pass transistor (NT3a, NT4a, NT5a).The drain electrode of the 3rd nmos pass transistor (NT3a) is connected with first power line terminal (VDDT), the grid of the 3rd nmos pass transistor (NT3a) is connected with input terminal (IN), the source electrode of the 3rd nmos pass transistor (NT3a) is connected with first node (N1a).The drain electrode of the 4th nmos pass transistor (NT4a) is connected with first node (N1a), the grid of the 4th nmos pass transistor (NT4a) is connected with control terminal (CT), the source electrode of the 4th nmos pass transistor (NT4a) is connected with second source line terminals (VSST).The drain electrode of the 5th nmos pass transistor (NT5a) is connected with first node (N1a), the grid of the 5th nmos pass transistor (NT5a) is connected with Section Point (N2a), the source electrode of the 5th nmos pass transistor (NT5a) is connected with second source line terminals (VSST).The 3rd nmos pass transistor (NT3a) specification is bigger approximately 2 times than the 5th nmos pass transistor (NT5a) specification.

Drop-down drive division 133d comprises the 6th and the 7th nmos pass transistor (NT6a, NT7a).The drain and gate of the 6th nmos pass transistor (NT6a) is connected with second source line terminals (VDDT) jointly, the source electrode of the 6th nmos pass transistor (NT6a) is connected with Section Point (N2a).The drain electrode of the 7th nmos pass transistor (NT7a) is connected with Section Point (N2a), the grid of the 7th nmos pass transistor (NT7a) is connected with first node (N1a), the source electrode of the 7th nmos pass transistor (NT7a) is connected with second source line terminals (VSST).The 6th nmos pass transistor (NT6a) specification is bigger approximately 16 times than the 7th nmos pass transistor (NT7a) specification.

If provide n-1 output signal that drives section (SRCn-1) to n input terminal that drives section (SRCn), just connected the 7th nmos pass transistor (NT7a).By moving the 7th nmos pass transistor (NT7a), Section Point (N2a) current potential drops to second source voltage level (VSS) from first mains voltage level (VDD), disconnects second nmos pass transistor (NT2) thus.Then, even connect the 7th nmos pass transistor (N7a), because the 6th nmos pass transistor (NT6a) specification is bigger approximately 16 times than the 7th nmos pass transistor (NT7a) specification, so Section Point (N2a) continues to keep second source voltage level (VSS).

Provide the output signal (OUTn+10) of the virtual segment (SRCn+1) that rises to turn-on level by n control terminal (CT) that drives section (SRCn), the 7th nmos pass transistor (NT7a) just disconnects.Therefore, Section Point (N2a) rises to first mains voltage level (VDD) by the 6th nmos pass transistor (NT6a) from second source voltage level (VSS).

The output signal (OUTn+10) of the virtual segment (SRCn+1) that applies by n control terminal (CT) that drives section (SRCn) drops to the disconnection level, even disconnect the 4th nmos pass transistor (NT4a), but Section Point (N2a) is first mains voltage level (VDD) by the 6th nmos pass transistor (NT6a) bias voltage.Therefore, second nmos pass transistor (NT2) keeps on-state, continues output second source voltage level (VSS) at lead-out terminal (OUTn).

Even when the current potential of the output signal that changes the virtual segment (SRCn+1) that applies by n control terminal (CT) that drives section (SRCn) with the off voltage level and disconnect the 4th transistor (NT4a), owing to the 6th transistor (NT6a) Section Point keeps first mains voltage level (VDD).Therefore, transistor seconds (NT2a) keeps on-state, and lead-out terminal (OUTn) has second source voltage level (VSS).

As shown in Figure 9, virtual segment (SRCn+1) comprise draw the 133a of portion, pull-down section 133b, on draw drive division 133c ', and drop-down drive division 133d.Virtual segment (SRCn+1) has and n driving section (SRCn) same structure, but the control terminal (CT) of virtual segment (SRCn+1) is connected with virtual segment (SRCn+1) lead-out terminal (OUTn+1).Therefore, virtual segment (SRCn+1) is according to self output signal control.

Compare with the transistorized transistor specifications of the control terminal that is connected in n driving section (SRCn), changed the transistorized transistor specifications of the control terminal that is connected in virtual segment (SRCn+1), so that keep the output signal of virtual segment (SRCn+1) in the given time.

For example, the 4th nmos pass transistor (NT4a ') specification is approximately littler 10 times than the 4th nmos pass transistor (NT4a) specification.Therefore, virtual segment (SRCn+1), being switched to the 4th nmos pass transistor (NT4a ') by self output signal with turn-on level needs the schedule time.Even provide the virtual segment (SRCn+1) that rises to turn-on level output signal by virtual segment (SRCn+1) control terminal (CT), the 7th nmos pass transistor (NT7a) needs the schedule time but connect the 4th nmos pass transistor (NT4a '), so also can not disconnect at once.The 4th node (N4) keeps second source voltage level (VSS) in the given time.Therefore, the output terminal of virtual segment (SRCn+1) can keep high-voltage level in the given time.

Through connection the 4th nmos pass transistor (NT4 ') after the schedule time, corresponding connection the 7th nmos pass transistor with it (NT7a), the 4th node (N4) rises to first mains voltage level (VDD) from second source voltage level (VSS).Along with the 4th node potential rises to first mains voltage level (VDD), connect second nmos pass transistor (NT2a), at virtual segment (SRCn+1) lead-out terminal (OUT) output second source voltage level (VSS).

The control terminal (CT) of virtual segment (SRCn+1) is connected with virtual segment (SRCn+1) lead-out terminal (OUTn+1), makes the virtual segment (SRCn+1) can stable operation.And gate driver circuit, need not established so need not to chase after from the independent wiring of outside when control signal is provided to the control terminal (CT) of virtual segment (SRCn+1).

Therefore, can prevent when chase after establish wiring during (not shown) in other wiring with chase after the delay phenomenon of the various signals that offer gate driver circuit that the electric capacity that produces between the wiring of establishing causes.

Figure 10 shows the block scheme of the shift register of the gate driver circuit of the 3rd exemplary embodiments according to the present invention, and Figure 11 shows the oscillogram of output signal of the gate driver circuit of Figure 10.Below, ' i ' is the even number littler than ' n '.

With reference to Figure 10, the gate driver circuit 150 of the 3rd exemplary embodiments comprises shift register 151 according to the present invention.Shift register 151 is divided into first group of G1 and second group of G2.Having to shift register 151 at shift register 151 peripheries provides a plurality of wiring lines portion 152.More specifically, wiring portion 152 comprises commencing signal line (STL), first power lead (VDDL), first clock line (CKL1), second clock line (CKBL1), second source line (VSSL), the 3rd clock line (CKL2) and the 4th clock line (CKBL2).

First clock line (CKL1) drives section (SRC1 to first group of G1, ..., SRCi-1) odd number in drives section (SRC1, SRC3, ...) first clock signal (CK) is provided, the 3rd clock line (CKL2) drives section (SRCi to second group of G2, ..., SRCn) in odd number drive section (SRCi+1) and virtual segment (SRCn+1) provides first clock signal (CK).Second clock line (CKBL1) is to the driving section (SRC1 of first group of G1, ..., SRCi-1) even number in drives section (SRC2, ...) the second clock signal (CKB) that has with first clock signal (CK) inverted phase (having 180 ° of outs of phase) is provided, the 4th clock line (CKBL2) to the driving section of second group of G2 (SRCi ..., SRCn) in even number drive a section (SRCi, ..., SRCn) provide second clock letter (CKB).

Therefore, n drive section (SRC1 ..., SRCn) in a part drive according to first and second clock signal that provides respectively by first and second clock line CKL1, CKBL1.N drive section (SRC1 ..., remainder SRCn) drives according to first and second clock signal C K, the CKB that provide respectively by the 3rd and the 4th clock line CKL2, CKBL2.Therefore, make become minimum the time delay that has first and second clock signal C K, the CKB that connect the voltage level generation from first grid polar curve to n gate line in turn, to prevent the distortion phenomenon of each section output signal.

The the 3rd and the 4th clock line CKL2, CKBL2 combine with the connecting line that crosses other wiring also to drive a section (SRC1 with n respectively, ..., SRCn) connect, but combine with first and second clock line CKL1, CKBL1 one end and respectively with a n driving section (SRC1, ..., SRCn) connect.

Specifically, import the 3rd clock line CKL2 one end of the first clock signal C K and the first clock line CKL2, one end of the input first clock signal C K and be arranged in mutual close position.And second clock line CKBL1 one end of input second clock signal CKB is arranged in mutual close position with the 4th clock line CKBL2 one end of input second clock signal CKB.In other words, first to fourth clock line (CKL1, CKBL 1, CKL2, CKBL2) input terminal is arranged in first and drives section (SRC1) close position.

The first clock line CKL1 other end combines with the 3rd clock line CKL2 other end, and with virtual segment (SRCn+1) close position on combine.

The second clock line CKBL1 other end combines with the 4th clock line CKBL2 other end, and with virtual segment (SRCn+1) close position on combine.

The the 3rd and the 4th clock line CKL2, CKBL2 directly are not connected with shift register 151, do not have and other wiring intersection yet.Thereby by the 3rd and the 4th clock line CKL2, the translational speed of first and second clock signal C K, the CKB of CKBL2 is faster than first and second clock signal C K, CKB translational speed by first and second clock line CKL1, CKLB1.

And wiring portion 152 wiring width are narrow more arranges in abutting connection with shift register 151 more.

Specifically, near arranging commencing signal line STL in shift register 151 places, next the first power cable VDDL and commencing signal line STL positioned adjacent.On the first power cable VDDL outside, arrange the second and first clock line CK1, CKBL1 in turn.Abut to form second source electric wire VSSL with the first clock line CKL1.The 3rd clock line CKL2 and second source electric wire VSSL positioned adjacent, its order four clock line CKBL2 and the 3rd clock line CKL2 positioned adjacent.

Wiring portion 152 is made up of this various wirings that are disposed in order, thereby can improve the display quality of LCD.Promptly near more with shift register 151, total contact area is also big more between the wiring, and hand capacity also becomes big thereupon.Therefore, few more wiring that is subjected to hand capacity is arranged near shift register 151 more.Thus, can improve the display quality of LCD.

With reference to Figure 11, provide first and second clock signal C K, CKB by first and second clock line CKL1, CKBL1 to 151 first groups of G1 of shift register, and to first group of G1 for the first time the section of driving SRC1 commencing signal ST is provided, first of first group of G1 drives section SRC1 and replys commencing signal ST line end, and the first clock signal C K high-voltage level produces the first output signal OUT1.Then, second drives the first output signal OUT1 that section SRC2 replys first driving section SRC1, and second clock signal CKB high-voltage level produces the second output signal OUT2.

Provide first and second clock signal C K, CKB by the 3rd and the 4th clock line CKL2, CKBL2 to 151 second groups of G2 of shift register, i the section SRCi that first of second group of G2 drives section replys first group of G1 i-1 i-1 output signal that drives section SRCi-1 of the section of driving at last, and second clock signal CKB high-voltage level produces i output signal OUTi-1.An i+1 driving section SRCi+1 replys i output signal OUTi, and the first clock signal C K high-voltage level produces i+1 output signal OUTi+1.

In sum, each drive produce in turn among section lead-out terminal OUT with high-voltage level first, second ..., the n output signal (OUT1, OUT2 ..., OUTn).

Figure 12 shows the layout of the 3rd and the 4th clock line arrangement of Figure 10, and Figure 13 shows the first and the 3rd clock line annexation and the second and the 4th clock line annexation layout.

With reference to Figure 12, arrange commencing signal line STL, the first power lead VDDL, the first and first clock line CKL1, CKBL1, second source line VSSL, the 3rd and the 4th clock line CKL2, CKBL2 in turn in shift register 151 outsides.Each wiring width is narrow more arranges near shift register 151 more.In other words, former wiring width from shift register is at least more than or equal to the adjacent side wiring width.More near shift register 151, the total contact area between the wiring is just big more, and hand capacity is also big, therefore fewly more arranged near shift register 151 more by the wiring of capacitive effect.

Specifically, near arranging commencing signal line STL in shift register 151 places, secondly, the first power lead VDDL and commencing signal line STL positioned adjacent.On the first power lead VDDL outside, arrange the second and first clock line CKL1.Second clock line CKBL1 is arranged in the inboard than the first clock line CKL1.Abut to form second source line VSSL with the first clock line CKL1.This structure can prevent wiring and with corresponding wiring line be connected to each section (SRC1 ..., the SRCn+1) delay that causes of the hand capacity that produces between the connecting line on.The the 3rd and the 4th clock line CKL2, CKBL2 are connected with the connecting line combination of crossing other wiring and with shift register 151, but combine with first and second clock line CKL1, CKBL1 one end, be connected with shift register 151, so be arranged in the outside than second source line VSSL.As shown in figure 12, the 3rd and the 4th clock line CKL2, CKBL2 form in thin-film transistor substrate 300 potted line region S A.

Specifically, thin-film transistor substrate 300 is divided into formation gate line (not shown), data line (not shown), reaches the viewing area (DA) of pixel (not shown) and neighboring area (PA) of (DA) periphery formation in the viewing area.

Neighboring area (PA) is divided into the gate driving zone (GA) that forms shift register 151 and various wirings and forms the bonded block that thin-film transistor substrate combines with the color filter (not shown), for example, and the potted line zone (SA) of sealant (not shown).Gate driving zone (GA) and potted line zone (SA) are overlapped.Be that potted line zone (SA) is as the criterion with center, potted line zone (SA) and is divided into medial region with liquid crystal and the exterior lateral area that does not have liquid crystal.(GA) comprises the first area in the gate driving zone.

In potted line zone (SA), form the part of the 3rd and the 4th clock line CKL2, CKBL2, second source line VSSL.In gate driving zone (GA), form remainder, the first clock line CKL1, second clock line CKBL1, and the commencing signal line STL of second source line VSSL.

The part of second source line VSSL, first and second clock line CKL1, CKBL1, the first power lead VDDL and commencing signal line STL have the part that contacts with connecting line, so if they are formed the loose contact that the operation of exerting pressure in the time of just may producing combination film transistor chip 300 and color filter causes in potted line zone (SA) in high temperature.

Have with being routed in the gate driving zone (GA) of connecting line contact portion and form, do not have with being routed in the potted line zone (SA) of connecting line contact portion and form, so can prevent the increase of the whole specification of LCD.Specifically, the part that the remainder of second source line VSSL, the 3rd and the 4th clock line CKL2, CKBL do not combine with connecting line is so also can form in potted line zone (SA).

Owing to chase after and establish the 3rd and the 4th clock line CKL2, CKLB2, do not produce the phenomenon that the LCD specification increases.And, in not having the potted line zone (SA) of liquid crystal, form the 3rd and the 4th clock line CKL2, CKBL2, so there is not electric capacity, therefore, first and second clock signal C K, CKB are more a lot of than first and second clock line CKL1, CKBL1 minimizing time delay.

With reference to Figure 13, the first clock line CKL1, one end combines with the 3rd clock line CKL2 one end, and second clock line CKBL1 one end combines with the 4th clock line CKBL2 one end.Therefore, the 3rd clock line CKL2 provides the first clock signal C K to each section of shift register, and the 4th clock line CKBL2 provides second clock signal CK to each section.

As Figure 12 and shown in Figure 13, the 3rd and the 4th clock line CKL2, CKBL2 directly are not connected with shift register 151, do not have the part that intersects with other wiring yet.So first and second clock signal C K, CKB are fast by the speed that first and second clock line CKL1, CKBL2 move by the velocity ratio that the 3rd and the 4th clock line CKL2, CKBL2 move.

Therefore, each section (SRC1 of shift register 151, ..., SRCn+1) part in is according to first and second clock signal C K, the CKB operation that provides by first and second clock line CKL1, CKBL1, and remainder is according to first and second clock signal C K, the CKB operation that provides by the 3rd and the 4th clock line CKL2, CKBL2.

Therefore, make from first grid polar curve to the end gate line have first and second clock signal C K, the CKB that high-voltage level produces in turn and become minimum time delay so that avoid from the distortion of the output signal of shift register 151 outputs.

Figure 14 shows the wire structures layout of the shift register of the 4th exemplary embodiments according to the present invention, and Figure 15 shows the shift register layout of the wire structures with Figure 14.

With reference to Figure 14 and Figure 15, between second source line VSSL and shift register (not shown), arrange the first connecting line VSSLc that connects second source line VSSL and each section.Between second source line VSSL and shift register, arrange first and second clock line CKL1, the CKBL1 in parallel with second source line VSSL.

The first connecting line VSSLc and first and second clock line CKL1, CKBL1 intersect.And first and second clock line CKL1, CKBL1 have first width W 1 at the first connecting line VSSLc with in the zone of intersecting, and have second width W 2 littler than first width W 1 in the zone of intersecting with the first connecting line VSSLc.

Specifically, corresponding zone of intersecting on the first clock line CKL1 with the first connecting line VSSLc, the first depressed part C1 that formation falls in to the inside from a sidewall, the zone that the corresponding first connecting line VSSLc intersects on second clock line CKL1 also forms the second depressed part C2 that falls in to the inside from a sidewall.

The first clock line CKL1 has first and second sidewall 1401,1402 that extends to length direction, and second clock line CKBL1 has the 3rd and the 4th sidewall 1403,1404 that extends to length direction.First and second clock line CKL1, CKBL1 make second sidewall 1402 and the 3rd sidewall 1403 mutually in the face of arranging.The first depressed part C1 forms on the first side wall 1401, and the second depressed part C2 forms on the 4th sidewall 1404.

As Figure 14 and shown in Figure 15, between the first clock line CKL1 and shift register 151, arrange the first clock signal connecting line CKLc that first clock signal is provided to each section, between second clock line CKBL1 and shift register 151, arrange the second clock signal connecting line CKBLc that the second clock signal is provided to each section.The first clock signal connecting line CKLc contacts with the first clock line CKL1 near second sidewall 1402 of the first clock line CKL1, and second clock signal connecting line CKBLc contacts with second clock line CKBL1 near the 3rd sidewall 1403 of second clock line CKBL1.Preferably, first and second depressed part C1, C2 are forming on nonoverlapping position with first and second clock signal connecting line CKLc, CKBLc contact portion.

Can reduce electric capacity in first and second clock line CK1, CKB1 and the generation of the first connecting line VSSLc transposition section.Therefore, can reduce first and second clock signal delay time that applies by first and second clock line CKL1, CKBL1.And, the time delay of the second source voltage signal VSS that applies by the first connecting line VSSLc.

The width of first and second clock line of the narrower formation of part CKL1, CKBL1 is so may increase resistance.Yet the retardation ratio resistance of signal more is subjected to the influence of electric capacity, so finally still can reduce time delay.

Below, showing embodiment and comparative example by table 1, the RC that shows according to electric capacity and resistance change postpones.First width W 1 of first and second clock line CKL1, CKBL1 is 70 μ m in an embodiment, and second width W 2 is 45 μ m.In comparative example, (W1 W2) is 70 μ m to first and second width of each among first and second clock line CKL1, the CKBL1.

Table 1

CKL1(CKBL1)	W1	W2	C	R
CKL1(CKBL1)	W1	W2	C	R	Comparative example	70μm	70μm	385pF	457Ω
Embodiment	70μm	45μm	344.5pF	489Ω	Comparative example	70μm	70μm	385pF	457Ω

As shown in Figure 1, first electric capacity that produces between first and second clock line CKL1, CKBL1 and the first connecting line VSSLc in comparative example is 385pF.In an embodiment, second electric capacity that produces between first and second clock line CKL1, CKBL1 and the first connecting line VSSLc is 344.5pF.The second capacity ratio comparative example has reduced about 10.5% in an embodiment.

In comparative example, first resistance is 457 Ω among first and second clock line CKL1, the CKBL1, and second resistance is 489 Ω among first and second clock line CKL1, the CKBL1 in an embodiment.Second resistance ratio, first resistance among the embodiment has increased about 7% approximately.Yet the ratio that the ratio that second resistance increases reduces less than second electric capacity is so finally reduced the RC delay.

With reference to Figure 14 and Figure 15, between second source line VSSL and shift register (not shown), arrange the first connecting line VSSLc that connects second source line VSSL and each section.Between second source line VSSL and shift register, arrange and second source line VSSL first and second clock line CKL1, CKBL1 side by side.

The first connecting line VSSLc and first and second clock line CKL1, CKBL1 intersect.The 3rd depressed part C3 that caves in to the inside from a sidewall that the first connecting line VSSL has that corresponding zone of intersecting with the first clock line CKL1 forms.The 4th depressed part C4 that caves in to the inside from a sidewall that has that corresponding zone of intersecting with second clock line CKBL1 forms.The first connecting line VSSLc with the disjoint zone of first and second clock line in have the 3rd width W 3, in the zone of intersecting with first and second clock line, have four width W 4 littler than the 3rd width W 3.

Because the first connecting line VSSLc width narrows down in the zone of intersecting with first and second clock line CKL1, CKBL1, therefore can reduce the electric capacity that forms between first and second clock line CKL1, CKBL1 and the first connecting line VSSLc.Therefore, can reduce the time delay of first and second clock signal that applies by first and second clock line CKL1, CKBL1 and the first supply voltage time delay that applies by the first connecting line VSSLc.

In above-mentioned gate driver circuit, because virtual segment (SRCn+1) lead-out terminal and last drive section (SRCn) are when control terminal is connected, also the control terminal with virtual segment (SRCn+1) is connected, with the signal delay phenomenon that prevents to provide to gate driver circuit.

And, change the transistor arrangement that is connected with control terminal in the virtual segment (SRCn+1), with the output signal of normal output virtual segment (SRCn+1), thereby can improve the liquid crystal display displays quality.

And, because wiring portion also has the 3rd and the 4th clock line that receives first and second clock respectively except first and second clock line, therefore can make from first grid polar curve to the end gate line have first and second clock delay time that high-voltage level takes place in turn and become minimum, further can improve the liquid crystal display displays quality.

The above is an exemplary embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. LCD comprises:

Display part, comprise i) first substrate, have pixel, gate line and data line, described pixel has the switchgear that is connected with described data line with described gate line, ii) second substrate, in the face of described first substrate, and iii) liquid crystal layer, place between described first substrate and described second substrate;

Data driver is used to provide the described data line with view data, and described data driver is connected in abutting connection with described display part formation and with described data line; And

Gate driving portion, be used to drive described switchgear, described gate drivers comprises shift register and wiring portion, described shift register has a plurality of driving sections that are one another in series and connect, described shift register is divided into first group and second group and the described display part formation of adjacency, by described wiring portion external signal is imposed on each described driving section, and each is described to drive section and is used to control the drive signal of described switchgear by lead-out terminal to described gate line output, and wherein said wiring portion comprises:

First clock line drives section to first group odd number first clock signal is provided;

The second clock line drives section to described first group even number the second clock signal that has 180 ° of outs of phase with respect to described first clock signal is provided;

The 3rd clock line drives section to described second group odd number described first clock signal is provided; And

The 4th clock line drives section to described second group even number described second clock signal is provided.

2. LCD according to claim 1, it is characterized in that, the described first, second, third and the 4th clock line comprises first, second, third and four-input terminal respectively, in first first area that drives section that is provided with described shift register with described first, second, third and the setting that is adjacent to each other of four-input terminal.

3. LCD according to claim 2, it is characterized in that, at last second area that drives section that is provided with described shift register described first clock line is connected with described the 3rd clock line, and described second clock line is connected with described the 4th clock line at described second area.

4. LCD according to claim 1, it is characterized in that, be formed for seal in the neighboring area of described display part, and described the 3rd clock line and described the 4th clock line are arranged on described neighboring area in conjunction with described first substrate and described second substrate.

5. LCD according to claim 1, it is characterized in that, described wiring portion also comprises first power lead, the second source line, and commencing signal line, first transmission signals is imposed on described first power lead, second transmission signals is imposed on described second source line, commencing signal is imposed on described commencing signal line, drive section to be provided for described first of the section that drives, described commencing signal line is set by the sequence of positions of the described shift register of distance of appointment, described second source line, described first clock line, described second clock line, described first power lead, described the 3rd clock line, and described the 4th clock line.

6. LCD according to claim 5, it is characterized in that, described wiring portion also comprises and is used to connect described first power lead and each described first connecting line that drives section, described first clock line and described second clock line have first width and have second width at the second portion that itself and described first connecting line intersect at itself and the Uncrossed first of described first connecting line, and described second width is less than described first width.

7. LCD according to claim 5, it is characterized in that, described wiring portion also comprises and is used to connect described first power lead and each described first connecting line that drives section, described first connecting line that connects first power lead and each described driving section intersects with described first clock line and described second clock line respectively, described first connecting line has the 3rd width in itself and the disjoint part of described first clock line and described first connecting line at itself and the disjoint part of described second clock line, described first connecting line has the 4th width at part and described first connecting line that itself and described first clock line intersect in the crossing part of itself and described second clock line, and described the 4th width is less than described the 3rd width.