JP3677100B2 - Flat panel display device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to a flat panel display device in which a plurality of pixels are arranged in a matrix and a driving method thereof.
[0002]
[Prior art]
In recent years, devices such as personal computers, word processors, TVs, and video projectors are generally thin, lightweight, and have low power consumption, and flat panel display devices represented by a liquid crystal display (LCD) are widely used. In particular, research and development of active matrix LCDs are active because good display images without crosstalk between adjacent pixels can be obtained. A general active matrix LCD is provided for controlling a light transmittance of a pixel in each horizontal pixel array, and a display panel in which a plurality of pixels are arranged in a matrix and each row of pixels constitutes one horizontal pixel array. And a signal line driver circuit for driving a plurality of signal lines. The signal line driving circuit converts pixel data sequentially supplied from the outside into a parallel format for each horizontal scanning period, and converts the obtained pixel data for one horizontal pixel array into analog voltages, respectively. Is supplied to each signal line.
[0003]
In recent trends, the number of pixels in each horizontal pixel array is increased to increase the resolution of the active matrix LCD, and the word length of the pixel data is increased to increase the gradation accuracy. In order to increase the number of pixels and the word length, the signal line driver circuit needs to process the pixel data at a higher speed. If the processing speed of the signal line driving circuit is increased to the limit, it becomes difficult to drive all the signal lines within one horizontal scanning period.
[0004]
As a solution to this problem, there is a block driving technique for driving N (N is an integer of 2 or more) pixel blocks obtained by dividing each horizontal pixel array. In this driving technique, the signal line driving circuit is composed of N driver units that respectively drive a group of signal lines assigned to these pixel blocks, and two line memories are allocated to these driver units for one horizontal pixel array. Are newly provided to store each of the pixel data. Pixel data for one horizontal pixel array is written into one line memory in each horizontal scanning period, and pixel data for one horizontal pixel array already written is read out from the other line memory. In this case, since the driver units corresponding to the respective pixel blocks can operate in parallel to process the pixel data distributed to them, the processing speed of each driver unit is equal to the number of pixel data equal to the total number of signal lines. Can be reduced to about 1 / N of the sequential processing.
[0005]
[Problems to be solved by the invention]
However, the block driving technique has a drawback that two line memories are newly required. Since each of these line memories must have a memory capacity capable of storing pixel data for one horizontal pixel array, this memory capacity increases as the number of pixels and the word length increase. Furthermore, these line memories are required to have a performance capable of withstanding high-speed data transfer as the memory capacity increases. Therefore, when the block driving technique is adopted, it is inevitable that the manufacturing cost of the flat panel display device becomes high.
[0006]
An object of the present invention is to provide a flat panel display device and a driving method thereof that can maintain a memory capacity necessary for block driving each horizontal pixel array on a small scale.
[0007]
[Means for Solving the Problems]
According to the present invention, a display panel in which a plurality of pixels are arranged in a matrix and pixels in each row form one horizontal pixel array, and pixels in each horizontal pixel array are divided into a plurality of continuous pixel blocks and driven. A plurality of driver units, M data supply buses connected to at least one of these driver units, and a control unit for distributing pixel data sequentially supplied from the outside to the M data supply buses, Each of the control units can be read from the other area while writing to one area, and includes a plurality of memory units each storing pixel data for one pixel block, and the total memory capacity of these memory units is 1 Data distribution circuit with less memory capacity for storing all pixel data for the horizontal pixel array, and pixel data sequentially supplied from the outside in one pixel block Each pixel data block is divided into pixel data blocks corresponding to the number of pixels, and M pixel data blocks are sequentially written into M memory units, and M pixels stored in these M memory units during the writing. There is provided a flat panel display device having a control circuit for reading out data blocks in parallel and performing control for supplying these M pixel data blocks to corresponding ones of the M data supply buses.
[0008]
According to the present invention, a display panel in which a plurality of pixels are arranged in a matrix and pixels in each row form one horizontal pixel array, and the pixels in each horizontal pixel array are divided into a plurality of continuous pixel blocks and driven. A plurality of driver units, M data supply buses connected to at least one of these driver units, and a control unit for distributing pixel data sequentially supplied from the outside to the M data supply buses. The control unit can read from the other area while writing to one area, and includes a plurality of memory sections each storing pixel data for one pixel block, and the total memory capacity of these memory sections is A driving method of a flat panel display device having a data distribution circuit smaller than a memory capacity for storing all pixel data for one horizontal pixel array, Dividing the pixel data sequentially supplied from the unit into pixel data blocks for each number corresponding to the number of pixels of one pixel block, and sequentially writing the M pixel data blocks to the M memory units. Reading the M pixel data blocks stored in the M memory units in parallel, and supplying the M pixel data blocks to the corresponding ones of the M data supply buses, respectively. And a method for driving a flat panel display device.
[0009]
In the flat panel display device and the driving method thereof, pixel data sequentially supplied from the outside is divided into pixel data blocks for each number corresponding to the number of pixels of one pixel block, and M pixel data blocks are divided into M pixel data blocks. The M pixel data blocks are sequentially written in the memory unit, and the M pixel data blocks stored in the M memory units are read in parallel during the writing, and the M pixel data blocks are read into the M data supply buses. Are supplied to the corresponding ones respectively. Therefore, the total memory capacity of the plurality of memory units is smaller than the memory capacity necessary for storing all the pixel data for one horizontal pixel array. Further, the memory capacity does not greatly depend on the number of pixel data for one horizontal pixel array and the word length of the pixel data. This makes it possible to increase the number of data and the word length while maintaining the memory capacity. As a result, it is possible to prevent the manufacturing cost of the flat panel display device from increasing due to the block driving of the horizontal pixel array.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a flat panel display according to a first embodiment of the present invention will be described with reference to the accompanying drawings. This flat panel display device is manufactured as a light transmissive active matrix LCD operating in a normally white mode.
[0011]
FIG. 1 schematically shows a configuration of the flat panel display device, and FIG. 2 shows a cross-sectional structure of the liquid crystal panel shown in FIG. The flat panel display device includes a liquid crystal panel 3 capable of color display. The liquid crystal panel 3 is provided with a display area 2 having a diagonal of 14 inches. The liquid crystal panel 3 includes an array substrate 101, a counter substrate 301, a liquid crystal layer 401 formed of a liquid crystal composition held between the array substrate 101 and the counter substrate 103 as a light modulation layer, and polarization axes orthogonal to each other. It is comprised by polarizing plate PL1 and PL2 affixed on the outer surface of the array substrate 101 and the counter substrate 301. FIG. In the liquid crystal panel 3, a sealant is added to the outer peripheral portions of the array substrate 101 and the counter substrate 301, the array substrate 101 and the counter substrate 301 are bonded together, and the gap between the array substrate 101 and the counter substrate 301 is surrounded by the sealant. It is formed by filling a liquid crystal composition.
[0012]
The array substrate 101 includes a glass substrate SB1, 600 × 2400 pixel electrodes 151 arranged in a matrix on the glass substrate SB1, and 600 scanning lines 113 formed along the rows of the pixel electrodes 151, respectively. (Y1-Y600), 2400 signal lines 103 (X1-X2400) formed along the columns of the pixel electrodes 151, and the intersections of the scanning lines 113 and the signal lines 103, respectively, are formed as switching elements. 600 × 2400 thin film transistors (TFTs) 121, 600 storage capacitor lines 161 each having a region overlapping the pixel electrode 151 in the corresponding row, and formed substantially parallel to the scanning line 113, and the pixel electrode And a first alignment film OR1 that entirely covers the matrix array 151. The TFT 121 has an inverted staggered TFT structure using an amorphous silicon thin film as an active layer. The pixel electrode 151 is a transparent conductive film made of Indium Tin Oxide (ITO). The storage capacitor line 161 and the pixel electrode 151 constitute a storage capacitor CS.
[0013]
The counter substrate 301 is a glass substrate SB2, a matrix light shielding film SF formed on the glass substrate SB2 so as to mask the peripheral portion of the pixel electrode 151, and a color formed on the glass substrate SB2 exposed from the matrix light shielding film SF. It has a filter FL, a counter electrode 311 facing the matrix array of pixel electrodes 151, and a second alignment film OR2 that covers the counter electrode 311 as a whole. The light shielding film SF shields light incident on the TFT 121, light passing through the gap between the signal line 103 and the pixel electrode 151, and light passing through the gap between the scanning line 113 and the pixel electrode 151. The color filter FL is composed of red, green, and blue color stripes that transmit light of corresponding color components, and these color stripes are repeatedly arranged in the row direction of the pixel electrodes 151. The counter electrode 311 is a transparent conductive film made of ITO like the pixel electrode 151. The first alignment film OR <b> 1 and the second alignment film OR <b> 2 are provided for twist nematic (TN) alignment of liquid crystal molecules when there is no potential difference between the pixel electrode 151 and the counter electrode 311. Each TFT 121 has a gate connected to one of the scanning lines 113 and a source / drain path connected between one of the signal lines 103 and one of all the pixel electrodes 151. The pixel electrode 151 and the counter electrode 311 constitute a liquid crystal capacitor CLC. The storage capacitor line 161 is connected to the counter electrode 311. The display area of the liquid crystal panel 3 is composed of 600 horizontal pixel arrays each including 800 groups of RGB pixels, and each group of RGB pixels corresponds to three adjacent pixel electrodes 151. Further, in order to reduce the external dimensions of the display device, the signal lines 103 and the scanning lines 113 are drawn out only to one end side of the liquid crystal panel 3 in the column and row directions of the pixel electrodes 151, respectively.
[0014]
(Note that the alignment films OR1 and OR2 and the polarizing plates PL1 and PL2 described above are unnecessary when a polymer dispersed liquid crystal in which a transparent resin and a liquid crystal material are mixed is used as a liquid crystal composition.)
This flat panel display device further includes a signal line driving circuit 12 for driving signal lines X1-X2400, a scanning line driving circuit 14 for driving scanning lines Y1-Y600, a signal line driving circuit 12, and a scanning line driving circuit 14. And a liquid crystal controller 16 to be controlled. The signal line drive circuit 12 has a tape carrier package (TCP) that forms drive portions XT1, XT2,..., XT8 on the signal line drive circuit board 5A and the wiring film XF. The scanning line driving circuit 14 has a tape carrier package (TCP) for forming driving units YT1, YT2,..., YT8 on the scanning line driving circuit substrate 5B and the wiring film XF. The liquid crystal controller 16 is constructed from a programmable logic array and disposed on the control circuit board 5C. The liquid crystal controller 16 receives RGB pixel data sequentially supplied from the outside at a rate of 800 (= number of RGB pixel groups) per horizontal scanning period, and sends these RGB pixel data together with various control signals to the signal line driving circuit 12. Supply. Each RGB pixel data is composed of a combination of R pixel data, G pixel data, and B pixel data representing red, green, and blue color components. Each of R pixel data, G pixel data, and B pixel data is 64 (= 2 ⁶ ) It has a 6-bit word length to display the corresponding color component in gradation. For this reason, the word length of RGB pixel data is 18 bits in total. Various control signals are a start pulse ST generated prior to the supply of RGB pixel data for one horizontal pixel array, a load pulse LD generated following the completion of the supply of RGB pixel data for one horizontal pixel array, And a clock pulse CK generated each time two RGB pixel data are supplied. The frequency of the clock pulse CK is set to 18 MHz, which is half of the system clock frequency of 36 MHz. The liquid crystal controller 16 further drives a control signal YSEL including a clock pulse and a start pulse to select one of the scanning lines Y1 to Y600 every horizontal scanning period equal to a period of 1024 clocks (= 28 μs). Supply to circuit 14. The signal line driving circuit 12 receives RGB pixel data for one horizontal pixel array from the liquid crystal controller 16 every horizontal scanning period, and converts R pixel data, G pixel data, and B pixel data included in each RGB pixel data into analog pixels. These are converted to signal voltages and supplied to the signal lines X1-X2400 in parallel. The scanning line driving circuit 14 sequentially selects the scanning lines Y1-Y600 based on the control signal YSEL from the liquid crystal controller 16, and supplies the scanning pulse to the selected scanning line. The TFTs 121 corresponding to the respective horizontal pixel arrays become conductive with the rise of the scanning pulse supplied via the corresponding one of the scanning lines Y1-Y600, and are supplied in parallel via the signal lines X1-X2400. The pixel signal voltage is supplied to the pixel electrode 151 of the horizontal pixel array. The liquid crystal capacitor CLC and the storage capacitor CS are charged by the pixel signal voltage thus supplied. Although these TFTs 121 become non-conductive with the fall of the scanning pulse, the potential difference between each pixel electrode 151 and the counter electrode 311 is still held by the liquid crystal capacitor CLC and the storage capacitor CS, and these TFTs 121 remain after one frame period. It is updated when it becomes conductive again.
[0015]
The TCP of the signal line drive circuit 12 is arranged in series on the wiring film XF so as to divide the matrix array of the pixel electrodes 151 into 8 blocks in the row direction, and driver units XT1, XT2 that drive 300 signal lines X1-X2400 each. ,..., XT8. The signal lines X1-X2400 are respectively connected to the output ends of these driver portions XT1-XT8 via anisotropic conductive films. The input ends of these driver portions XT1-XT8 are solder-connected to a wiring portion formed on the signal line drive circuit board 5A, and this wiring portion is further solder-connected to a liquid crystal controller 16 formed on the control circuit board 5C. .
[0016]
Further, the TCP of the scanning line driving circuit 14 is arranged in series on the wiring film YF so as to divide the matrix array of the pixel electrodes 151 into four blocks in the column direction, and driver units YT1, which drive 150 scanning lines Y1-Y600 one by one. YT2,..., YT4 are configured. The scanning lines Y1-Y600 are connected to the output ends of these driver units YT1-YT4 through anisotropic conductive films, respectively. The input ends of these driver portions YT1 to YT4 are solder-connected to a wiring portion formed on the scanning line driving circuit board 5B, and this wiring portion is further solder-connected to a liquid crystal controller 16 formed on the control circuit board 5C. . The basic structure of the driver units YT1-YT4 is the same as the conventional one.
[0017]
As shown in FIG. 3, the signal line driving circuit 12 includes a group of odd driver units XT1, XT3,..., XT7 and a group of even driver units XT2, XT4,. It is configured to be block driven. Each of the driver units XT1 to XT8 includes a 100-stage shift register circuit SR, a selection circuit SA, a latch circuit LA1, a latch circuit LA1, and a digital-analog converter D / A.
[0018]
In the group of odd-numbered driver units XT1, XT3,..., XT7, all shift register circuits SR are connected in series. That is, the first stage of the shift register circuit SR of the driver unit XT1 is connected to receive the start pulse ST supplied from the liquid crystal controller 16, and the last stage of the shift register circuit SR is connected to the first stage of the shift register circuit SR of the driver unit XT3. The final stage of the shift register circuit SR of the driver unit XT3 is connected to the first stage of the shift register circuit SR of the driver unit XT5, and the final stage of the shift register circuit SR of the driver unit XT5 is the shift register circuit SR of the driver unit XT7. Connected to the first stage. Each of the shift register circuits SR of the driver units XT1, XT3,..., XT7 is connected to receive a clock pulse ST supplied from the liquid crystal controller 16. The selection circuits SA of the driver units XT1, XT3,..., XT7 are commonly connected to the data supply bus SDL1 and are connected to the shift register circuits SR of the driver units XT1, XT3,. The latch circuits LA1 of the driver units XT1, XT3,..., XT7 are connected to the selection circuits SA of the driver units XT1, XT3,. The latch circuits LA2 of the driver units XT1, XT3,..., XT7 are connected to receive the load pulse LD supplied from the liquid crystal controller 16, and are connected to the latch circuits LA1 of the driver units XT1, XT3,. The digital-analog converters D / A of the driver units XT1, XT3,..., XT7 are connected to the latch circuit LA2 of the driver units XT1, XT3,. The signal lines X1201 to X1500 and the signal lines X1801 to X2100 are respectively connected. Each shift register circuit SR sequentially shifts the start pulse ST to the subsequent stage in response to the clock pulse CK. Each selection circuit SA extracts 18-bit RGB pixel data SD from the data supply bus SDL1 in response to a start pulse ST from each stage of the corresponding shift register circuit SR, and a 6-bit R pixel included in the RGB pixel data. Data, 6-bit G pixel data, and 6-bit B pixel data are supplied to the corresponding latch circuit LA1. Each latch circuit LA2 latches the pixel data for 300 pixels from the latch circuit LA1 in response to the load pulse LD, and supplies them to the corresponding digital-analog converter D / A. Each digital-analog converter D / A converts the pixel data for these 300 pixels into a pixel signal voltage and supplies it to the corresponding 300 signal lines.
[0019]
In the group of even driver sections XT2, XT4,..., XT8, all shift register circuits SR are connected in series. That is, the first stage of the shift register circuit SR of the driver unit XT2 is connected to receive the start pulse ST supplied from the liquid crystal controller 16, and the last stage of the shift register circuit SR is connected to the first stage of the shift register circuit SR of the driver unit XT4. The final stage of the shift register circuit SR of the driver section XT4 is connected to the first stage of the shift register circuit SR of the driver section XT6, and the final stage of the shift register circuit SR of the driver section XT6 is the shift register circuit SR of the driver section XT8. Connected to the first stage. Further, each of the shift register circuits SR of the driver units XT2, XT4,..., XT8 is connected to receive a clock pulse CK supplied from the liquid crystal controller 16. The selection circuits SA of the driver units XT2, XT4,..., XT8 are commonly connected to the data supply bus SDL2 and are connected to the shift register circuits SR of the driver units XT2, XT4,. The driver circuits XT2, XT4,..., XT8 are connected to the selection circuits SA of the driver sections XT2, XT4,. The latch circuits LA2 of the driver units XT2, XT4,..., XT8 are connected to receive the load pulse LD supplied from the liquid crystal controller 16, and are connected to the latch circuits LA1 of the driver units XT2, XT4,. The digital-analog converters D / A of the driver units XT2, XT4,..., XT8 are connected to the latch circuit LA2 of the driver units XT2, XT4,. The signal lines X1501-X1800 and X2101-X2400 are connected to the signal lines X1501-X1800, respectively. Each shift register circuit SR sequentially shifts the start pulse ST to the subsequent stage in response to the clock pulse CK. Each selection circuit SA extracts 18-bit RGB pixel data SD from the data supply bus SDL2 in response to a start pulse ST from each stage of the corresponding shift register circuit SR, and a 6-bit R pixel included in the RGB pixel data. Data, 6-bit G pixel data, and 6-bit B pixel data are supplied to the corresponding latch circuit LA1. Each latch circuit LA2 latches the pixel data for 300 pixels from the latch circuit LA1 in response to the load pulse LD, and supplies them to the corresponding digital-analog converter D / A. Each digital-analog converter D / A converts the pixel data for these 300 pixels into a pixel signal voltage and supplies it to the corresponding 300 signal lines.
[0020]
As shown in FIG. 4, the liquid crystal controller 16 controls the operation of the data distribution circuit DST for distributing the RGB pixel data SD sequentially supplied from the outside to the data supply buses SDL1 and SDL2, and the operation of the data distribution circuit DST. A control signal YSEL supplied to the drive circuit 14 and a sequence controller SC that generates control signals such as a start pulse ST, a clock pulse CK, and a load pulse LD supplied to the signal line drive circuit 12.
[0021]
The data distribution circuit DST has a selector WS, memories M1, M2, and M3, and a selector RS. The selector WS selects one of the memories M1, M2, and M3, and supplies RGB pixel data SD sequentially supplied from the outside to the selector WS. Each of the memories M1 to M3 is formed as a two-port RAM having 100 18-bit memory areas and capable of reading from one other memory area while writing to one memory area. The memory capacity described above is selected so that all RGB pixel data SD to be processed by one of the driver units XT1-XT8 can be stored. Each of the memories M1, M2, and M3 stores 100 RGB pixel data SD sequentially supplied from the selector WS as one block. The selector RS distributes two blocks of RGB pixel data SD read in parallel from two of the memories M1, M2, and M3 to the data supply buses SDL1 and SDL2.
[0022]
In order to control the operations of the selector WS, the memories M1-M3, and the selector RS, the sequence controller SC performs the write control signals WM1, WM2, and WM3, the write address signal WADRS, the read control signals RM1, RM2, and RM3. Read address signal RADRS and control signals S1 and S2 are generated. Write control signals WM1, WM2, and WM3 are supplied in common to selector WS and are also supplied to memories M1, M2, and M3, respectively. Write address signal WADRS and read address signal RADRS are supplied in common to memories M1, M2, and M3. Read control signals RM1, RM2, and RM3 are supplied to memories M1, M2, and M3, respectively. Control signals S1 and S2 are commonly supplied to the selector RS.
[0023]
The sequence controller SC generates write control signals in the order of WM1, WM2, WM3, WM1, WM2, WM3,... In order to write the memories M1, M2, and M3 one by one. Accordingly, the selector WS sequentially selects the memories M1, M2, and M3, and supplies the RGB pixel data SD sequentially supplied from the outside to the selection memory. The write control signals WM1, WM2, and WM3 are switched every time 100 RGB pixel data SD are supplied. The selection memory stores the RGB pixel data SD sequentially supplied from the selector WS in a write memory area designated by the write address signal WADRS. The write address signal WADRS is updated in a cycle corresponding to the supply rate of the RGB pixel data SD, and 100 RGB pixel data SD are written in the first to 100th memory areas, respectively. Further, the sequence controller SC performs the write operation in this way, while setting the read control signals RM1 and RM2, RM3 and RM1, RM2 and RM3, RM1 and RM2, in order to read the memories M1, M2, and M3 two by two, It occurs in the order of RM3 and RM1, RM2 and RM3. Each of these two memories reads the RGB pixel data SD from the read memory area designated by the read address signal RADRS and supplies it to the selector RS. The read address signal RADRS is updated in a cycle corresponding to about half of the supply rate of the RGB pixel data SD, and 100 RGB pixel data SD are sequentially read from the first to 100th memory areas. The selector RS corresponds to the odd-numbered driver portion and even-numbered driver portion to which two blocks of RGB pixel data SD read out in parallel from two of the memories M1-M3 are controlled by the control signals S1 and S2. Distribution to the data supply buses SDL1 and SDL2. Thereby, the RGB pixel data SD for each horizontal pixel array is divided into 8 blocks, and 4 odd blocks are supplied to the driver units XT1, XT3, XT5, and XT7 via the data supply bus SDL1, respectively. The signals are supplied to the driver units XT2, XT4, XT6, and XT8 via the data supply bus SDL2, respectively.
[0024]
FIG. 5 shows the operation of the flat panel display device configured as described above.
Each horizontal scanning period is composed of a data supply period (= 28 × 800/1024 μs) and a blanking period (= 28 × 224/1024 μs), and 800 18 bits corresponding to the number of pixels constituting one horizontal pixel array. RGB pixel data is sequentially supplied to the liquid crystal controller 16 from the outside during this data supply period. These 800 pieces of RGB pixel data SD are divided by 100 by the selector WS, and become eight RGB pixel data blocks DB1 to DB8 respectively assigned to the driver units XT1, XT2,. The memories M1, M2 and M3 sequentially store these RGB pixel data blocks DB1-DB8. Each of the RGB pixel data blocks DB1-DB8 is written into one of the memories M1, M2, and M3 in one block period (= t) equal to 1/8 of the data supply period, that is, 28 × 100/1024 μs. That is, the RGB pixel data blocks DB1-DB3 are sequentially written in, for example, the memories M1, M2, and M3. These memories M1, M2, and M3 are repeatedly used to sequentially store subsequent RGB pixel data blocks DB4-DB8.
[0025]
Reading from the memories M1-M3 is performed while writing to the memories M1-M3 is performed as described above. In this reading, two consecutive RGB pixel data blocks DB1-DB8 are read in parallel in two block periods (= 2t). That is, the RGB pixel data blocks DB1 and DB2 are read in parallel from the memories M1 and M2 in the first two block periods (= 2t), and the RGB pixel data blocks DB3 and DB4 are read in the next two block periods (= 2t). The RGB pixel data blocks DB5 and DB6 are read in parallel from the memories M2 and M3 in the next two block periods (= 2t), and the RGB pixel data blocks DB7 and DB8 are read in the next two. Data are read from the memories M1 and M2 in parallel in the block read period (= 2t).
[0026]
The RGB pixel data blocks DB1 and DB2, DB3 and DB4, DB5 and DB6, and DB7 and DB8 read out in parallel are distributed to the data supply buses SDL1 and SDL2 via the read selector RS. That is, the odd RGB pixel data blocks DB1, DB3,..., DB7 are supplied to the data supply bus SDL1 connected to the odd driver units XT1, XT3,. , XT8 are supplied to the data supply bus SDL2 connected to the even driver units XT2, XT4,.
[0027]
By the way, since each of the memories M1 to M3 has a memory capacity of 100 words × 18 bits, RGB pixel data exceeding one block cannot be stored. For this reason, the sequence controller SC starts parallel reading of these 2RGB pixel data blocks before the end of continuous writing of the 2RGB pixel data blocks, and continues after the end of parallel reading of these 2RGB pixel data blocks. Continuous writing of 2 RGB pixel data blocks is started, and the data distribution circuit DST is controlled so that writing of each RGB pixel data is not overtaken by reading.
[0028]
For example, with respect to the memory M1, the RGB pixel data block DB1 is written over one block period (= t) and then read out over two block periods (= 2t) with a delay of Δt. That is, the writing of the RGB pixel data block DB4 is started earlier by a period of Δt than the end of reading of the RGB pixel data block DB1. However, since the memory M1 has already started reading the RGB pixel data block DB1 at the start of writing of the RGB pixel data block DB4, the RGB pixel data of the block DB1 has already been read from the RGB pixel data of the block DB4. Are sequentially written into the memory area. Therefore, the memory M1 can also store the RGB pixel data block DB4 within a given memory capacity range. Incidentally, the RGB pixel data block DB4 is also read with a delay of Δt after the writing is completed. Since Δt is set to an arbitrary period from the period of 1 clock (= 27.7 ns) to the period of 99 clocks (= 2.75 μs), for example, 160 ns, writing of each RGB pixel data is overtaken by reading. There is no.
[0029]
Therefore, even if the memory capacity of the memories M1-M3 is 100 words × 18 bits each, the RGB pixel data for one horizontal pixel array is divided into 100 blocks each processed by the driver units XT1-XT8. Write to one of M3 at the data supply rate, and distribute two consecutive blocks from two of the memories M1-M3 in parallel to the read data supply buses SDL1 and SDL2 at half the data supply rate Can do. That is, odd RGB pixel data blocks DB1, DB3,..., DB7 and even RGB pixel data blocks DB2, DB4,..., DB8 are data supply bus SDL1 and even driver connected to odd driver portions XT1, XT3,. , XT8 are supplied to the data supply bus SDL2 connected to the parts XT2, XT4,. Thereby, the RGB pixel data blocks DB1 and DB2 are processed in parallel by the driver units XT1 and XT2, the RGB pixel data blocks DB3 and DB4 are processed in parallel by the driver units XT3 and XT4, and the RGB pixel data blocks DB5 and DB6 are processed. Are processed in parallel by the driver units XT5 and XT6, and the RGB pixel data blocks DB7 and DB8 are processed in parallel by the driver units XT7 and XT8.
[0030]
For example, the driver units XT1 and XT2 perform the following processing while the RGB pixel data blocks DB1 and DB2 are supplied to the data supply buses SDL1 and SDL2 in parallel.
[0031]
In the driver unit XT1, the first to 100th stages of the shift register circuit SR alternately store the start pulse ST in response to the clock pulse CK. In response to the signal from the stage storing the start pulse ST, the selection circuit SA selects a corresponding one of the 100 RGB pixel data sequentially supplied as the RGB pixel data block DB1 to the data supply bus SDL1, Three pixel data (that is, R pixel data, G pixel data, and B pixel data each consisting of 6 bits) included in the RGB pixel data is simultaneously supplied to the latch circuit LA1. The latch circuit LA1 latches the pixel data sequentially supplied from the selection circuit SA corresponding to 100 RGB pixel data, and supplies them to the latch circuit LA2. The latch circuit LA2 latches all pixel data from the latch circuit LA1 at a time in response to the load pulse LD, and supplies it to the digital-analog converter D / A. The digital-analog converter D / A converts the pixel data into pixel signal voltages and supplies them to the signal lines X1-X300.
[0032]
In the driver unit XT2, the first to 100th stages of the shift register circuit SR alternately store the start pulse ST in response to the clock pulse CK. In response to the signal from the stage storing the start pulse ST, the selection circuit SA selects a corresponding one of the 100 RGB pixel data sequentially supplied as the RGB pixel data block DB2 to the data supply bus SDL2, The RGB pixel data is supplied to the latch circuit LA1 at the same time as pixel data for three pixels (R pixel data, G pixel data, and B pixel data each having 6 bits). The latch circuit LA1 latches the pixel data sequentially supplied from the selection circuit SA corresponding to 100 RGB pixel data, and supplies them to the latch circuit LA2. The latch circuit LA2 latches all pixel data from the latch circuit LA1 at a time in response to the load pulse LD, and supplies it to the digital-analog converter D / A. The digital-analog converter D / A converts these pixel data into pixel signal voltages and supplies them to signal lines X301 to X600.
[0033]
Other driver units XT3 and XT4, XT5 and XT6, and XT7 and XT8 operate in parallel as described above. Since the odd-numbered driver units XT1, XT3,..., XT7 and the even-numbered driver units XT2, XT4,..., XT8 operate in parallel in this way, the clock pulse CK is ½ of that when they do not operate in parallel. Generated at frequency. Accordingly, the operating speed of the driver units XT1-XT8 is reduced corresponding to the frequency of the clock pulse CK.
[0034]
As described above, according to the flat panel liquid crystal display device of the present embodiment, the RGB pixel data for one horizontal pixel array has an information amount of 14 kbits (2400 × 6 bits), but 5.4 kbits. With the total memory capacity of the very small memories M1 to M3 (3 × 100 × 18 bits), block driving that reduces the operating speed of the driver units XT1 to XT8 in half is possible. For this reason, the liquid crystal controller 16 can be comprised with an inexpensive small-scale programmable logic array, and the manufacturing cost of a display apparatus can be reduced. Further, since the frequency of the clock pulse CK is reduced to ½, the low-speed type shift register circuit SR can be used in each of the driver units XT1 to XT8. This is effective for reducing the power consumption of the display device.
[0035]
In the above-described embodiment, the RGB pixel data SD for one horizontal pixel array is divided into 8 blocks corresponding to the number of driver units. For example, when 10 driver units are provided, one horizontal pixel array is provided. Minute RGB pixel data SD is divided into 10 blocks. As a result, the number of 18-bit memory areas provided in each of the memory M1 to the memory M3 can be reduced to 80. The number of driver units is preferably set to p (p is a positive integer greater than or equal to 2) times the number of data supply buses. )
In the above-described embodiment, the three memories M1-M3 are provided to drive the odd-numbered driver unit and the even-numbered driver unit in parallel. However, these driver units may be divided into three or more groups or blocks and driven in parallel. In this case, the memories M1 to M3 must also be increased corresponding to the number of groups, but the frequency of the clock pulse CK can be reduced to 1 / number of groups. Therefore, the operation speed of the shift register circuit SR can be further reduced. For example, when one horizontal pixel array includes 3072 pixel electrodes, it is conceivable to provide 16 driver units each driving 192 signal lines and divide them into 4 groups by 4 data supply buses. In this case, 7 memories each having 64 18-bit memory areas are used, and the RGB pixel data for one horizontal pixel array is divided into 16 corresponding blocks and distributed to these 4 data supply buses every 4 blocks. That's fine. This increases the number of driver units and the number of memories, but the frequency of the clock pulse CK can be reduced to 1/4 when 16 driver units are not divided into four groups, so that the operating speed and power consumption of the shift register circuit SR can be reduced. It can be reduced correspondingly.
[0036]
In this embodiment, the driver unit XT-XT8 is fixed on the flexible wiring film XF as an integrated circuit. However, this integrated circuit may be fixed on the array substrate 101 of the liquid crystal panel 3 using an anisotropic conductive film or the like and connected to the data supply buses SDL1 and SDL2 on the array substrate 101. In this case, since the signal line drive circuit board 5A is not necessary, the size of the outer portion of the display region 2 can be reduced. Further, if the signal line driving circuit 12 is formed on the array substrate 101 so as to be connected to the signal line 103 using polycrystalline silicon or the like in the manufacturing process of the liquid crystal panel 3, the signal line 103 is manufactured after the liquid crystal panel 3 is manufactured. And the troublesome work of connecting the signal line drive circuit 12 can be omitted.
[0037]
FIG. 6 shows a modification of the liquid crystal controller shown in FIG. In this modification, a selector EO, an odd memory OM, and an even memory EM are further provided in the data distribution circuit DST. The selector EO is controlled by the control of the control signal PS supplied from the sequence controller SC, and alternately supplies RGB pixel data sequentially supplied from the outside to the odd memory OM and the even memory EM. The odd-numbered memory OM and the even-numbered memory EM are 18-bit memories each storing 1 RGB pixel data, store the RGB pixel data respectively supplied from the selector EO, and supply it to the selector WS. The selector WS supplies 2-word RGB pixel data respectively supplied from the odd-numbered memory OM and the even-numbered memory EM to one of the memories M1-M3. Each of the memories M1 to M3 has 50 36-bit memory areas having the same memory capacity as shown in FIG. 4, and stores 50 2-word RGB pixel data sequentially supplied from the selector WS as one block. . The selector RS distributes two blocks of 2-word RGB pixel data read in parallel from two of the memories M1, M2, and M3 to the data supply buses SDL1 and SDL2.
[0038]
In this case, the number of bits of the data supply buses SDL1 and SDL2 is set to 32 bits, the number of stages of the shift register circuit SR is set to 50 in each of the driver units XT1 to XT8, and the frequency of the clock pulse CK is the same as that of the above-described embodiment. Set to 1/2. Accordingly, the selection circuit SA responds to the signal from the stage storing the start pulse ST, and corresponding one of the 50 2-word RGB pixel data sequentially supplied to the data supply bus SDL1 as the RGB pixel data block DB1. This RGB pixel data is selected as pixel data for six pixels (each of 6-bit first R pixel data, first G pixel data, first B pixel data, second R pixel data, second G pixel data, and second B pixel data). ) And simultaneously supplied to the latch circuit LA1.
[0039]
According to this modification, the total memory capacity is increased by 32 bits in the data distribution circuit DST, but since the number of bits of the data supply buses SDL1 and SDL2 is doubled, the number of stages of the shift register circuit SR is reduced to the driver units XT1-XT8. Each is half. Therefore, the operation speed and power consumption of the shift register circuit SR can be further reduced.
[0040]
Next, a flat panel display device according to a second embodiment of the present invention is described. This display device is configured in the same manner as in the first embodiment except for the signal line drive circuit 12 shown in FIG. 3 and the liquid crystal controller 16 shown in FIG. The signal line driving circuit 12 has the same configuration as that of the above-described modified example. FIG. 7 shows the liquid crystal controller 16 of the flat panel display device according to the second embodiment. The liquid crystal controller 16 controls the operation of the data distribution circuit DST for distributing the RGB pixel data SD sequentially supplied from the outside to the data supply buses SDL1 and SDL2, and the operation of the data distribution circuit DST, as in the first embodiment. And a sequence controller SC that generates control signals YSEL supplied to the line drive circuit 14 and control signals such as a start pulse ST, a clock pulse CK, and a load pulse LD supplied to the signal line drive circuit 12.
[0041]
The data distribution circuit DST includes a selector EO, an odd memory OM, an even memory EM, a selector WS, memories M1 and M2, and a selector RS. The selector EO alternately supplies RGB pixel data sequentially supplied from the outside to the odd-numbered memory OM and the even-numbered memory EM. The odd-numbered memory OM and the even-numbered memory EM are 18-bit memories each storing 1 RGB pixel data, store the RGB pixel data respectively supplied from the selector EO, and supply it to the selector WS. The selector WS supplies 2-word RGB pixel data supplied from the odd-numbered memory OM and the even-numbered memory EM, respectively, to one of the memories M1 and M2. Each of the memories M1 and M2 has a memory capacity obtained by adding one 36-bit memory area to the 50 36-bit memory areas shown in FIG. 6, and 50 2-word RGB pixels sequentially supplied from the selector WS. Store data as one block. The selector RS distributes two blocks of 2-word RGB pixel data SD read in parallel from the memories M1 and M2 to the data supply buses SDL1 and SDL2.
[0042]
In order to control the operations of the selector EO, the selector WS, the memories M1 and M2, and the selector RS, the sequence controller SC controls the control signal PS, the write control signals WM1 and WM2, the write address signal WADRS, the read control signal RM1 and RM2, read address signals RADRS1 and RADRS2, and control signals S1 and S2 are generated. The control signal PS is supplied to the selector EO. Write control signals WM1 and WM2 are supplied in common to selector WS and also supplied to memories M1 and M2, respectively. Write address signal WADRS is supplied commonly to memories M1 and M2, and read address signals RADRS1 and RADRA2 are supplied to memories M1 and M2, respectively. Read control signals RM1 and RM2 are supplied to memories M1 and M2, respectively. Control signals S1 and S2 are commonly supplied to the selector RS.
[0043]
The sequence controller SC generates write control signals in the order of WM1, WM2, WM2, WM1, WM1, WM2,. The selector WS selects one of the memories M1 and M2 based on the above-described write control signal, and supplies 2-word RGB pixel data SD sequentially supplied from the odd memory OM and the even memory EM to the selected memory. The write control signals WM1 and WM2 are updated every time 50 pieces of 2-word RGB pixel data SD are supplied. The selection memory stores the 2-word RGB pixel data SD sequentially supplied from the selector WS in the write memory area designated by the write address signal WADRS. The write address signal WADRS is updated in a cycle corresponding to the supply rate of the 2-word RGB pixel data SD, and 50 RGB pixel data SD are stored in the first to 50th memory areas or the second to 51st memory areas. Each memory area is written. These write memory area ranges are used alternately. Further, sequence controller SC generates read control signals RM1 and RM2 for performing the read operation of memories M1 and M2 while the write operation is thus performed. Each of these two memories reads 2-word RGB pixel data SD from the read memory area designated by the corresponding read address signal RADRS1 or RADRS2, and supplies it to the selector RS. The read address signals RADRS1 and RADRS2 are updated in a cycle corresponding to about half of the supply rate of the 2-word RGB pixel data SD from the selector WS, and are stored in the first to 50th memory areas of one of the memories M1 and M2. The 50 2-word RGB pixel data SD written and the 50 2-word RGB pixel data SD written in the second to 51st memory areas of the other of the memories M1 and M2 are sequentially read out. Let The selector RS receives two blocks of RGB pixel data SD read out in parallel from the memories M1 and M2 under the control of the control signals S1 and S2, and the data supply bus SDL1 corresponding to the odd-numbered driver portion and the even-numbered driver portion to which they are supplied. And SDL2. As a result, the 2-word RGB pixel data SD for each horizontal pixel array is divided into 8 blocks, and 4 odd blocks are supplied to the driver units XT1, XT3, XT8, and XT7 via the data supply bus SDL1, respectively. The blocks are supplied to the driver units XT2, XT4, XT6, and XT8 via the data supply bus SDL2, respectively.
[0044]
FIG. 8 shows the operation of the flat panel display device configured as described above. Here, in order to facilitate understanding of this operation, it is assumed that one horizontal pixel array is composed of 80 pixels, and each of the driver units XT1, XT2,..., XT8 drives 10 signal lines. In this case, each of the memories M1 and M2 must have one 36-bit memory area in addition to five 36-bit memory areas.
[0045]
When 80 RGB pixel data SD corresponding to the number of pixels constituting one horizontal pixel array are sequentially supplied to the liquid crystal controller 16 from the outside, these 80 RGB pixel data SD are alternately switched by the selector EO to the odd-numbered memory OM and The even number memory EM is supplied. The odd-numbered memory OM and the even-numbered memory EM store the RGB pixel data SD supplied from the selector EO and supply it to the selector WS. The selector WS divides five 2-pixel RGB pixel data sequentially supplied from the odd-numbered memory OM and the even-numbered memory EM by five, and eight RGB pixel data blocks DB1- assigned to the driver units XT1, XT2,. Let it be DB8. The memory M1 and the memory M2 selectively store these RGB pixel data blocks DB1-DB8. Each of the RGB pixel data blocks DB1-DB8 is written in one of the memories M1 and M2 in one block period (= t) equal to 1/8 of the data supply period.
[0046]
That is, RGB pixel data blocks DB1, DB2, DB3, DB4, DB5, DB6, DB7, and DB8 are written in memories M1, M2, M2, M1, M1, M2, M2, and M1, respectively. The odd RGB pixel data blocks DB1, DB3, DB5, and DB7 are stored in the memory areas up to addresses 0-4 in the memories M1, M2, M1, and M2, respectively, and the even RGB pixel data blocks DB2, DB4, DB6, and DB8. Are stored in memory areas up to addresses 1-5 in the memories M2, M1, M2, and M1.
[0047]
Reading from the memories M1 and M2 is performed while writing to the memories M1 and M2 is performed as described above. In this reading, two consecutive RGB pixel data blocks DB1-DB8 are read in parallel in two block periods (= 2t). That is, the RGB pixel data blocks DB1 and DB2 are read in parallel from the memories M1 and M2 in the first two block periods (= 2t), and the RGB pixel data blocks DB3 and DB4 are read in the next two block periods (= 2t). The RGB pixel data blocks DB5 and DB6 are read in parallel from the memories M1 and M2 in the next two block periods (= 2t), and the RGB pixel data blocks DB7 and DB8 are read in parallel from the M2 and M1. Data are read in parallel from the memories M2 and M1 in the block read period (= 2t).
[0048]
The RGB pixel data blocks DB1 and DB2, DB3 and DB4, DB5 and DB6, and DB7 and DB8 thus read out in parallel are distributed to the data supply buses SDL1 and SDL2 via the read selector RS. That is, the odd RGB pixel data blocks DB1, DB3,..., DB7 are supplied to the data supply bus SDL1 connected to the odd driver portions XT1, ..., XT7, and the even RGB pixel data blocks DB2, DB4,. , XT2, XT8 are supplied to a data supply bus SDL2.
[0049]
By the way, the sequence controller SC starts parallel reading of these 2RGB pixel data blocks before the end of continuous writing of the 2RGB pixel data blocks, and the subsequent 2RGB pixel data before the end of parallel reading of these 2RGB pixel data blocks. Continuous writing of the pixel data block is started, and the data distribution circuit DST is controlled so that writing of each RGB pixel data is not overtaken by reading. Further, since each of the memories M1 and M2 has an extra memory area corresponding to two-word RGB pixel data, it is avoided that the read address and the write address overlap.
[0050]
For example, the RGB pixel data block DB1 is written in the memory M1 in the first block period, and the RGB pixel data block DB2 is written in the memory M2 in the second block period. These RGB pixel data blocks DB1 and DB2 are read in parallel in the second and third block periods from the memories M1 and M2. The memory M2 is used for writing and reading the RGB pixel data block DB2 in the second block period. However, the reading start is delayed by a period of Δt corresponding to the period required to store one 2-word RGB pixel data. Therefore, after the first 2-word RGB pixel data included in the block DB2 is written to the address 1, the 2-word RGB pixel data can be read.
[0051]
The memory M2 is used to read the RGB pixel data block DB2 and write the RGB pixel data block DB3 in the third block period. However, since the range of the memory area storing the RGB pixel data block DB2 and the range of the memory area storing the RGB pixel data block DB3 are shifted by one memory area, the final 2-word RGB pixel data included in the block DB2 Can be read from the memory area at address 5, and the final 2-word RGB pixel data included in the block DB3 can be written into the memory area at address 4.
[0052]
In an actual display device, one horizontal pixel array is composed of 2400 pixels, and driver units XT1, XT2,..., XT8 each drive 300 signal lines. Therefore, each of the memories M1 and M2 has one 36-bit memory area in 50 36-bit memory areas. However, the operation of this display device is basically the same.
[0053]
Therefore, even if the memory capacity of the memories M1 and M2 is 50 words × 36 bits, respectively, two words of RGB pixel data for one horizontal pixel array are processed in units of 50 blocks processed by the driver units XT1-XT8. Write to one of M1 and M2 at the data supply rate, and distribute two consecutive blocks from two of the memories M1 and M2 in parallel to the read data supply buses SDL1 and SDL2 at half the data supply rate can do. That is, odd RGB pixel data blocks DB1, DB3,..., DB7 and even RGB pixel data blocks DB2, DB4,..., DB8 are data supply bus SDL1 and even driver connected to odd driver portions XT1, XT3,. , XT8 are supplied to the data supply bus SDL2 connected to the parts XT2, XT4,. Thereby, the RGB pixel data blocks DB1 and DB2 are processed in parallel by the driver units XT1 and XT2, the RGB pixel data blocks DB3 and DB4 are processed in parallel by the driver units XT3 and XT4, and the RGB pixel data blocks DB5 and DB6 are processed. Are processed in parallel by the driver units XT5 and XT6, and the RGB pixel data blocks DB7 and DB8 are processed in parallel by the driver units XT7 and XT8.
[0054]
In the second embodiment, RGB pixel data sequentially supplied from the outside is divided into pixel data blocks for each number corresponding to the number of pixels of one pixel block, and two pixel data blocks are sequentially written in the memories M1 and M2. During this writing, the two-pixel data blocks stored in the memories M1 and M2 are read in parallel, and these two-pixel data blocks are supplied to the corresponding ones of the data supply buses SDL1 and SDL2, respectively. Therefore, the total memory capacity of the memories M1 and M2 is sufficiently smaller than ½ of the memory capacity necessary for storing all the pixel data for one horizontal pixel array. Further, the memory capacity does not greatly depend on the number of pixel data for one horizontal pixel array and the word length of the pixel data. This makes it possible to increase the number of data and the word length while maintaining the memory capacity. As a result, it is possible to prevent the manufacturing cost of the flat panel display device from increasing due to the block driving of the horizontal pixel array.
[0055]
In particular, according to this embodiment, the number of memory areas is increased by “1” in each of the memories M1 and M2, but the memory M3 shown in FIG. 4 can be made unnecessary instead.
[0056]
Note that the selector EO, the odd number memory OM, and the even number memory EM can be omitted when the operation speed of the driver units XT1-XT8 does not need to be further reduced. In this case, each memory area of the memories M1 and M2 is composed of 18 bits for storing RGB pixel data.
[0057]
【The invention's effect】
As described above, the flat panel display device and the driving method thereof according to the present invention can maintain the memory capacity necessary for driving each horizontal pixel array in a small scale.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing a configuration of a flat panel display device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of the liquid crystal panel shown in FIG.
FIG. 3 is a block diagram showing a part of a signal line driving circuit formed on the signal line driving substrate and the wiring film shown in FIG. 1;
4 is a block diagram showing a liquid crystal controller formed on the control circuit board shown in FIG. 1. FIG.
FIG. 5 is a time chart for explaining the operation of the flat panel display device shown in FIG. 1;
FIG. 6 is a block diagram showing a modification of the liquid crystal controller shown in FIG.
FIG. 7 is a block diagram showing a liquid crystal controller of a flat panel display device according to a second embodiment of the present invention.
8 is a diagram for explaining the operation of the flat panel display device of the second embodiment controlled by the liquid crystal controller shown in FIG. 7; FIG.
9 is a diagram for explaining the operation of the flat panel display device of the second embodiment controlled by the liquid crystal controller shown in FIG. 7. FIG.
[Explanation of symbols]
3 ... Display panel, XT1-XT8 ... Driver unit, SDL1, SDL2 ... Data supply bus, 16 ... Liquid crystal controller, M1-M3 ... Memory, DST ... Data distribution circuit, SC ... Sequence controller.

Claims (6)

A display panel in which a plurality of pixels are arranged in a matrix and pixels in each row constitute one horizontal pixel array, a plurality of driver units that divide the pixels of each horizontal pixel array into a plurality of continuous pixel blocks, and drive each of them. These driver units are connected in order to M data supply buses, and control means for distributing pixel data sequentially supplied from the outside to the M data supply buses. It is possible to read from other areas during writing, and includes a plurality of memory units for storing pixel data corresponding to one block of pixels, and the total memory capacity of these memory units stores pixel data for one horizontal pixel array. Data distribution circuit with less memory capacity for storing all, and pixel data for each pixel data sequentially supplied from the outside corresponding to the number of pixels in one pixel block This is divided into locks, and M pixel data blocks are sequentially written into the M memory units, and M pixel data blocks stored in the M memory units are read in parallel during the writing. A control circuit that performs control to supply M pixel data blocks to corresponding ones of the M data supply buses, the M data supply buses being first and second data supply buses; And the number of driver units is set equal to an integer multiple of 2 , and each of the data distribution circuits has a memory capacity capable of storing pixel data of a number corresponding to the number of pixels of one pixel block. Including first, second, and third memory units selected one by one to write pixel data blocks and two by two to read two consecutive pixel data blocks in parallel The control circuit writes all the pixel data of each pixel data block to one of the first, second, and third memory portions in a predetermined period without overlapping the writing area and the reading area. A flat panel having a sequence controller for performing control to read two pixel data continuous in a period twice as long from two of the first, second, and third memory units in parallel Display device. Each pixel data is color pixel data respectively representing a plurality of color component gradations, and each driver unit is configured to drive a number of pixels equal to the number of color components corresponding to one color pixel data. The flat panel display device according to claim 1 . The data distribution circuit has conversion means for converting pixel data sequentially supplied from the outside into two-word pixel data two by two, and each area of each memory unit has two-word pixel data sequentially supplied from the conversion means 2. The flat panel display device according to claim 1 , wherein the flat panel display device has a word length set to twice the number of bits of one pixel data for storing. A display panel in which a plurality of pixels are arranged in a matrix and pixels in each row constitute one horizontal pixel array, a plurality of driver units that divide the pixels of each horizontal pixel array into a plurality of continuous pixel blocks, and drive each of them. The M data supply buses to which the driver units are sequentially connected, and control means for distributing pixel data sequentially supplied from the outside to the M data supply buses, each of the control means being assigned to one area. A plurality of memory units that store pixel data corresponding to one block of pixels, and the total memory capacity of these memory units is pixel data corresponding to one horizontal pixel array. In a driving method of a flat panel display device having a data distribution circuit smaller than a memory capacity for storing all of the pixel data, pixel data sequentially supplied from the outside is 1 A first step of dividing the pixel data block into a number corresponding to the number of pixels of the prime block, and sequentially writing M pixel data blocks to the M memory units, and during the writing, the M memory units A second step of reading in parallel the M pixel data blocks stored in, and a third step of supplying these M pixel data blocks to the corresponding ones of the M data supply buses, respectively. The M data supply buses are configured by first and second data supply buses, the number of the driver units is set equal to an integer multiple of 2, and the data distribution circuit includes the number of pixels of one pixel block. Two consecutive pixel data blocks selected one by one in order to write each pixel data block have a memory capacity capable of storing the number of pixel data corresponding to Including first, second, and third memory units that are selected two at a time for reading, and the second step stores all pixel data in each pixel data block without overlapping the writing region and the reading region. While writing to one of the first, second and third memory sections in a predetermined period, two pixel data continuous in a period twice as long as the predetermined period are written in parallel to the first, second, and third. A driving method of a flat panel display device, comprising a sub-step of reading from two of the memory units. Each pixel data is color pixel data respectively representing a plurality of color component gradations, and each driver unit is configured to drive a number of pixels equal to the number of color components corresponding to one color pixel data. 5. The driving method of a flat panel display device according to claim 4 , The data distribution circuit has conversion means for converting pixel data sequentially supplied from the outside into two-word pixel data two by two, and each area of each memory unit has two-word pixel data sequentially supplied from the conversion means 5. The driving method of a flat panel display device according to claim 4 , wherein a word length set to twice the number of bits of one pixel data is stored.

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