JPH08211846A - Flat panel display device and driving method therefor - Google Patents

Abstract

PURPOSE: To make memory capacities required for driving blocks of respective horizontal pixel arraies to be small scales. CONSTITUTION: This device is provided with a display panel in which plural pixels are arranged in a matrix shape, eight driver parts driving eight pixel blocks, data supplying busses SDL1, SDL2 to which driver parts are successively connected and a liquid crystal controller 16 distributing successively supplied pixel data to data supplying busses SDL1, SDL2 and a data distributing circuit DST including memories M1 to M3 respectively storing pixel data equivalent to one pixel block and a sequence controller SC dividing pixel data successively supplied from the outside as pixel data blocks and successively writing two pixel data blocks in two memories and reading out two pixel data blocks stored in the two memories parallelly during the writing of pixel data to supply the readout data to a corresponding data supplying busses among a first and a second data supplying busses SDL1, SDL2 are provided in the liquid crystal controller 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a flat panel display device having a plurality of pixels arranged in a matrix and a driving method thereof.

[0002]

2. Description of the Related Art In recent years, devices such as personal computers, word processors, TVs, video projectors, etc. have generally been thin, lightweight, and have low power consumption, and widely used flat panel display devices represented by liquid crystal displays (LCDs). There is. Especially active matrix LCD
The research and development of (1) is active because a good display image without crosstalk between adjacent pixels can be obtained. A general active matrix LCD is provided to control a light transmittance of a display panel in which a plurality of pixels are arranged in a matrix and each row of pixels constitutes one horizontal pixel array, and a light transmittance of each horizontal pixel array. And a signal line driving circuit that drives a plurality of signal lines. This signal line drive circuit converts pixel data sequentially supplied from the outside into a parallel format for each horizontal scanning period, converts the pixel data of one horizontal pixel array obtained thereby into analog voltages, respectively, and converts these analog voltages. To each signal line.

A recent trend is that the number of pixels in each horizontal pixel array is increased to increase the resolution of the active matrix LCD and the word length of the pixel data is increased to improve the grayscale accuracy. In order to increase the number of pixels and the word length, the signal line driving circuit needs to process pixel data at a higher speed. If the processing speed of the signal line driving circuit is increased to the limit, it becomes difficult to drive all the signal lines within one horizontal scanning period.

As a solution to this problem, there is a block driving technique for driving N (N is an integer of 2 or more) pixel blocks obtained by dividing each horizontal pixel array. In this driving technique, a signal line driving circuit is composed of N driver units that drive a group of signal lines assigned to these pixel blocks, and two line memories are allocated to one horizontal pixel array for these driver units. Is newly provided to store each pixel data of. Pixel data for one horizontal pixel array is written in one line memory in each horizontal scanning period, and already written pixel data for one horizontal pixel array is read from the other line memory. In this case, since the driver units corresponding to the respective pixel blocks can operate in parallel to process the pixel data distributed to them, the processing speed of each driver unit is set to the number of pixel data equal to the total number of signal lines. Can be reduced to about 1 / N of the case of sequential processing.

[0005]

However, the block driving technique has the drawback of requiring two new line memories. Since each of these line memories must have a memory capacity capable of storing pixel data for one horizontal pixel array, this memory capacity increases with an increase in the number of pixels and word length described above. Further, these line memories are required to have performance capable of withstanding high-speed data transfer when the memory capacity increases. Therefore, when the block driving technique is adopted, it is inevitable that the manufacturing cost of the flat panel display device increases.

It is an object of the present invention to provide a flat panel display device capable of maintaining a small memory capacity required for block driving each horizontal pixel array and a driving method thereof.

[0007]

According to the present invention, a display panel in which a plurality of pixels are arranged in a matrix and each row of pixels constitutes one horizontal pixel array, and a plurality of continuous pixels of each horizontal pixel array are provided. A plurality of driver units, each of which is divided into pixel blocks and driven, M data supply buses connected to at least one of the driver units, and pixel data sequentially supplied from the outside to M data supply buses. And a control unit that distributes to one area, each of which can read from another area while writing to one area, and includes a plurality of memory units each storing pixel data of one pixel block, The total memory capacity of these memory units is smaller than the memory capacity for storing all the pixel data for one horizontal pixel array, and is sequentially supplied from the outside. Classified as pixel data blocks for each number corresponding pixel data to the number of pixels of 1 pixel block,
The M pixel data blocks are sequentially written into the M memory units, and the M data stored in the M memory units during the writing.
There is provided a flat panel display device having a control circuit for reading out pixel data blocks in parallel and supplying these M pixel data blocks to respective ones of the M data supply buses. It

According to the present invention, a display panel in which a plurality of pixels are arranged in a matrix and the pixels of each row form one horizontal pixel array, and the pixels of each horizontal pixel array are divided into a plurality of continuous pixel blocks. A plurality of driver units that are respectively driven by the respective
And a control unit that distributes pixel data sequentially supplied from the outside to the M data supply buses, each of which is provided during writing to one area. It is possible to read from other areas and includes a plurality of memory units each storing pixel data for one pixel block, and the total memory capacity of these memory units is for storing all pixel data for one horizontal pixel array. A method of driving a flat panel display device having a data distribution circuit having a smaller capacity than a memory capacity, the method comprising dividing pixel data sequentially supplied from the outside into pixel data blocks in a number corresponding to the number of pixels in one pixel block. , M pixel data blocks are sequentially written to the M memory units, and M pixel data blocks stored in these M memory units during this writing. A parallel reading step, the driving method of the flat panel display device and a respectively supplying step to the corresponding ones of the M pixel data block M data supply bus is provided.

In the flat panel display device and the driving method thereof, the pixel data sequentially supplied from the outside is 1
The pixel data blocks are divided into numbers corresponding to the number of pixels in the pixel block, M pixel data blocks are sequentially written in the M memory units, and are stored in the M memory units during this writing. Further, the M pixel data blocks are read in parallel, and these M pixel data blocks are supplied to the corresponding ones of the M data supply buses. Therefore, the total memory capacity of multiple memory units is 1
This is less than the memory capacity required to store all the pixel data for the horizontal pixel array. Further, this memory capacity does not largely depend on the number of pixel data for one horizontal pixel array and the word length of the pixel data. This makes it possible to increase the number of these data and the word length while maintaining the memory capacity. As a result, it is possible to prevent the manufacturing cost of the flat panel display device from increasing due to the block driving of the horizontal pixel array.

[0010]

DETAILED DESCRIPTION OF THE INVENTION A flat panel display device according to a first embodiment of the present invention will be described below with reference to the accompanying drawings. This flat panel display device is a light transmissive active matrix LCD that operates in a normally white mode.
Manufactured as

FIG. 1 schematically shows the structure of this flat panel display device, and FIG. 2 shows the sectional structure of the liquid crystal panel shown in FIG. The flat panel display device includes a liquid crystal panel 3 capable of color display. The LCD panel 3 has a diagonal 14
An inch display area 2 is provided. The liquid crystal panel 3 includes an array substrate 101, a counter substrate 301, a liquid crystal layer 401 made of a liquid crystal composition and held between the array substrate 101 and the counter substrate 103 as a light modulation layer, and polarization axes thereof are orthogonal to each other. Array substrate 101 and counter substrate 3
Polarizing plates PL1 and P attached to the outer surface of 01
And L2. The liquid crystal panel 3 is the array substrate 1
01 and the counter substrate 301, a sealing agent is added to the outer peripheral portions thereof, and the array substrate 101 and the counter substrate 301 are bonded to each other, and the liquid crystal composition is filled in the gap surrounded by the sealing agent between the array substrate 101 and the counter substrate 301. It is formed by

The array substrate 101 includes a glass substrate SB1 and
6 arranged in a matrix on the glass substrate SB1
00 × 2400 pixel electrodes 151, 600 scanning lines 113 (Y1-Y600) formed along the rows of the pixel electrodes 151, and the pixel electrodes 151.
2400 signal lines 1 formed along each column
03 (X1 to X2400), 600 × 2400 thin film transistors (TFTs) 121 formed as switching elements near the intersections of the scanning lines 113 and the signal lines 103, and the pixel electrodes 151 of corresponding rows.
600 storage capacitor lines 161 that have regions overlapping with each other and are formed substantially parallel to the scanning line 113, and a first alignment film OR1 that entirely covers the matrix array of the pixel electrodes 151. The TFT 121 has an inverted staggered TFT structure using an amorphous silicon thin film as an active layer. The pixel electrode 151 is a transparent conductive film made of Indium Tin Oxide (ITO). The storage capacitor line 161 and the pixel electrode 151 form a storage capacitor CS.

The counter substrate 301 includes a glass substrate SB2 and a glass substrate SB so as to mask the peripheral portion of the pixel electrode 151.
2, a matrix light-shielding film SF formed over the matrix light-shielding film SF, a color filter FL formed over the glass substrate SB2 exposed from the matrix light-shielding film SF, a counter electrode 311 facing the matrix array of the pixel electrodes 151, and the counter electrode. And a second alignment film OR2 that entirely covers 311. The light shielding film SF receives the light incident on the TFT 121, the light passing through the gap between the signal line 103 and the pixel electrode 151, and the scanning line 1.
The light passing through the gap between the pixel electrode 151 and the pixel electrode 151 is blocked. The color filter FL is composed of red, green, and blue color stripes that transmit light of corresponding color components, and these color stripes are repeatedly arranged in the row direction of the pixel electrodes 151. The counter electrode 311 is a transparent conductive film made of ITO like the pixel electrode 151. First alignment film OR1
The second alignment film OR2 is provided to align the liquid crystal molecules in the twist nematic (TN) when there is no potential difference between the pixel electrode 151 and the counter electrode 311. Each TF
T121 is a gate connected to one of the scanning lines 113, and one of the signal lines 103 and all pixel electrodes 15
Source / drain path connected to one of the two. The pixel electrode 151 and the counter electrode 311 form a liquid crystal capacitor CLC. Further, the storage capacitance line 161 is connected to the counter electrode 311. The display area of the liquid crystal panel 3 described above is composed of 600 horizontal pixel arrays each including RGB pixels of 800 groups, and the RGB pixels of each group correspond to three adjacent pixel electrodes 151, respectively. In addition, in order to reduce the external dimensions of the display device, the signal line 10
3 and the scanning line 113 are drawn out only to one end side of the liquid crystal panel 3 in the column and row directions of the pixel electrode 151, respectively.

(Incidentally, the above-mentioned alignment films OR1 and OR2 and the polarizing plates PL1 and PL2 are not necessary when a polymer dispersed liquid crystal obtained by mixing a transparent resin and a liquid crystal material is used as a liquid crystal composition.) The panel display device further includes signal lines X1-X.
2400 for driving the signal line driving circuit and the scanning line Y1
A scanning line driving circuit 14 that drives -Y600 and a liquid crystal controller 16 that controls the signal line driving circuit 12 and the scanning line driving circuit 14 are provided. The signal line drive circuit 12 has a tape carrier package (TCP) that forms the drive units XT1, XT2, ..., XT8 on the signal line drive circuit board 5A and the wiring film XT. The scanning line driving circuit 14 has a tape carrier package (TCP) that forms the driving units YT1, YT2, ..., YT8 on the scanning line driving circuit board 5B and the wiring film XF. The liquid crystal controller 16 is constructed from a programmable logic array and arranged on the control circuit board 5C. The liquid crystal controller 16 receives RGB pixel data sequentially supplied from the outside at a rate of 800 (= the number of groups of RGB pixels) per horizontal scanning period, and sends these RGB pixel data to the signal line drive circuit 12 together with various control signals. Supply. Each RGB pixel data is composed of a combination of R pixel data, G pixel data, and B pixel data representing red, green, and blue color components. Each of the R pixel data, the G pixel data, and the B pixel data has a word length of 6 bits in order to display the corresponding color component with 64 (= 2 ⁶ ) gradations. Therefore, RG
The word length of B pixel data is 18 bits, which is the total of these. Various control signals are RGB for one horizontal pixel array
A start pulse ST generated prior to the supply of pixel data, a load pulse LD generated following the completion of supply of the RGB pixel data for one horizontal pixel array, and 2
It includes a clock pulse CK generated every time one RGB pixel data is supplied. The frequency of this clock pulse CK is 18 MHz, which is half the system clock frequency of 36 MHz.
set to z. The LCD controller 16 is further 102
A control signal YSEL including a clock pulse and a start pulse is supplied to the scanning line driving circuit 14 in order to select one of the scanning lines Y1-Y600 for each horizontal scanning period equal to the period of 4 clocks (= 28 μs). . The signal line drive circuit 12 receives RGB pixel data for one horizontal pixel array from the liquid crystal controller 16 for each horizontal scanning period, and converts R pixel data, G pixel data, and B pixel data included in each RGB pixel data into analog pixels. It is converted into a signal voltage and supplied in parallel to the signal lines X1-X2400. The scanning line drive circuit 14 is a liquid crystal controller 16
Scan lines Y1-Y60 based on the control signal YSEL from
0 is sequentially selected and a scanning pulse is supplied to the selected scanning line.
The TFT 121 corresponding to each horizontal pixel array has a scanning line Y1.
The signal lines X1-X are turned on with the rising edge of the scan pulse supplied via the corresponding one of -Y600.
Pixel signal voltages supplied in parallel via 2400 are supplied to the pixel electrodes 151 of this horizontal pixel array, respectively. The liquid crystal capacitance CLC and the storage capacitance CS are charged by the pixel signal voltage thus supplied. These TFT
Although 121 becomes non-conductive with the fall of the scan pulse, the potential difference between each pixel electrode 151 and the counter electrode 311 is still held by the liquid crystal capacitance CLC and the storage capacitance CS after that, and these TFTs 121 are again turned on after one frame period. It is updated when there is continuity.

The TCP of the signal line driving circuit 12 is arranged in series on the wiring film XF so as to divide the matrix array of the pixel electrodes 151 into eight blocks in the row direction, and a driver unit for driving the signal lines X1 to X2400 300 at a time. XT1, XT2, ..., XT8 are configured. Signal line X1
-X2400 is connected to the output terminals of these driver units XT1 to XT8 via anisotropic conductive films, respectively. The input ends of these driver portions XT1 to XT8 are soldered to a wiring portion formed on the signal line drive circuit board 5A, and this wiring portion is further soldered to a liquid crystal controller 16 formed on the control circuit board 5C. .

The TCP of the scanning line driving circuit 14 is arranged in series on the wiring film YF so as to divide the matrix array of the pixel electrodes 151 into four blocks in the column direction, and drives 150 scanning lines Y1-Y600 each. The parts YT1, YT2, ..., YT4 are configured. Scan line Y
1-Y600 is connected to the output terminals of these driver sections YT1-YT4 via anisotropic conductive films, respectively. The input ends of these driver portions YT1 to YT4 are soldered to a wiring portion formed on the scanning line drive circuit board 5B, and this wiring portion is further soldered to a liquid crystal controller 16 formed on the control circuit board 5C. . Driver unit YT1-YT
The basic structure of No. 4 is the same as the conventional one.

In the signal line drive circuit 12, as shown in FIG. 3, a group of odd number driver units XT1, XT3, ..., XT7 and a group of even number driver units XT2, XT4 ,. Block drive in parallel. Each of the driver units XT1 to XT8 includes a 100-stage shift register circuit SR, a selection circuit SA, a latch circuit LA1, a latch circuit LA1, and a digital-analog converter D / A.

Odd driver sections XT1, XT3, ..., XT
In the group of 7, all shift register circuits SR are connected in series. That is, the first stage of the shift register circuit SR of the driver unit XT1 is connected to receive the start pulse ST supplied from the liquid crystal controller 16,
The final stage of the shift register circuit SR is the driver unit XT.
3 is connected to the first stage of the shift register circuit SR, the final stage of the shift register circuit SR of the driver unit XT3 is connected to the first stage of the shift register circuit SR of the driver unit XT5, and the shift register circuit SR of the driver unit XT5 is connected.
Is the shift register circuit SR of the driver unit XT7.
Is connected to the first stage of. Driver unit XT1, XT3, ...,
Each of the shift register circuits SR of the XT 7 is connected to receive the clock pulse ST supplied from the liquid crystal controller 16. Driver unit XT1, XT3, ..., XT
The selection circuits SA of 7 are commonly connected to the data supply bus SDL1 and also have driver units XT1, XT3, respectively.
..., connected to the shift register circuit SR of XT7. Latch circuit LA of driver units XT1, XT3, ..., XT7
1 is connected to the selection circuits SA of the driver units XT1, XT3, ..., XT7, respectively. Driver part XT1, XT
The latch circuits LA2 of XT7, ..., XT7 are connected to receive the load pulse LD supplied from the liquid crystal controller 16, and the driver units XT1, XT3 ,.
7 latch circuit LA1. Driver part XT
1, XT3, ..., XT7 digital-analog converter D
/ A is connected to the latch circuit LA2 of the driver units XT1, XT3, ..., XT7, and the signal lines X1 to X30.
0, signal line X601-X900, signal line X1201-X
1500 and signal lines X1801-X2100, respectively. Each shift register circuit SR sequentially shifts the start pulse ST to the subsequent stage in response to the clock pulse CK. Each selection circuit SA extracts 18-bit RGB pixel data SD from the data supply bus SDL1 in response to the start pulse ST from each stage of the corresponding shift register circuit SR, and the 6-bit R pixel included in this RGB pixel data. The data, the 6-bit G pixel data, and the 6-bit B pixel data are supplied to the corresponding latch circuit LA1. Each latch circuit LA2 latches the pixel data of 300 pixels from the latch circuit LA1 in response to the load pulse LD,
These are supplied to the corresponding digital-analog converter D / A. Each digital-analog converter D / A has these 300
Convert pixel data for each pixel into pixel signal voltage,
The signal is supplied to the corresponding 300 signal lines.

Even driver sections XT2, XT4, ..., XT
In the group of 8, all shift register circuits SR are connected in series. That is, the first stage of the shift register circuit SR of the driver unit XT2 is connected so as to receive the start pulse ST supplied from the liquid crystal controller 16,
The final stage of the shift register circuit SR is the driver unit XT.
4 is connected to the first stage of the shift register circuit SR, the final stage of the shift register circuit SR of the driver unit XT4 is connected to the first stage of the shift register circuit SR of the driver unit XT6, and the shift register circuit SR of the driver unit XT6 is connected.
Is the shift register circuit SR of the driver unit XT8.
Is connected to the first stage of. Furthermore, driver units XT2, XT
Each of the shift register circuits SR of 4, ..., XT8 is connected to receive the clock pulse CK supplied from the liquid crystal controller 16. Driver unit XT2, XT4
The selection circuit SA of the XT8 is commonly connected to the data supply bus SDL2 and the driver sections XT2 and X are respectively provided.
, XT8 are connected to the shift register circuit SR. The latch circuits LA1 of the driver units XT2, XT4, ..., XT8 are connected to the selection circuits SA of the driver units XT2, XT4 ,. Driver part XT2
The latch circuit LA2 of XT4, ..., XT8 is connected to receive the load pulse LD supplied from the liquid crystal controller 16, and the driver units XT2, XT4 ,.
It is connected to the latch circuit LA1 of XT8. Driver part X
The digital-analog converter D / A of T2, XT4, ..., XT8 is connected to the latch circuit LA2 of the driver units XT2, XT4 ,.
600, signal line X901-X1200, signal line X150
1-X1800 and signal lines X2101-X2400, respectively. Each shift register circuit SR sequentially shifts the start pulse ST to the subsequent stage in response to the clock pulse CK. Each selection circuit SA responds to a start pulse ST from each stage of the corresponding shift register circuit SR and outputs 18-bit RGB pixel data S from the data supply bus SDL2.
D is extracted, and 6-bit R pixel data, 6-bit G pixel data, and 6-bit B pixel data included in this RGB pixel data are supplied to the corresponding latch circuit LA1. Each latch circuit LA2 latches the pixel data of 300 pixels from the latch circuit LA1 in response to the load pulse LD, and these are latched by the corresponding digital-analog converter D / A.
Supply to. Each digital-analog converter D / A converts the pixel data of these 300 pixels into a pixel signal voltage, and supplies the pixel signal voltage to the corresponding 300 signal lines.

As shown in FIG. 4, the liquid crystal controller 16
Is a data distribution circuit DST that distributes RGB pixel data SD sequentially supplied from the outside to the data supply buses SDL1 and SDL2, and controls the operation of the data distribution circuit DST, and at the same time, supplies a control signal YSEL supplied to the scanning line drive circuit 14. And a sequence controller SC that generates control signals such as a start pulse ST, a clock pulse CK, and a load pulse LD supplied to the signal line drive circuit 12.

The data distribution circuit DST has a selector WS, memories M1, M2 and M3, and a selector RS. The selector WS selects one of the memories M1, M2, and M3, to which R is sequentially supplied from the outside.
The GB pixel data SD is supplied. Each of the memories M1 to M3 has 100 18-bit memory areas and is formed as a 2-port RAM capable of reading from one memory area while writing to another memory area. The memory capacity described above is chosen so that it can store all the RGB pixel data SD to be processed by one of the driver units XT1-XT8. Each of the memories M1, M2, and M3 has 100 RGs sequentially supplied from the selector WS.
The B pixel data SD is stored as one block. The selector RS is provided with two blocks of RGB pixel data S read in parallel from two of the memories M1, M2, and M3.
D is distributed to the data supply buses SDL1 and SDL2.

The above-mentioned selector WS, memories M1-M3,
In order to control the operation of the selector RS, the sequence controller SC controls the write control signals WM1, WM2 and WM3, the write address signal WADRS, the read control signals RM1, RM2 and RM3 and the read address signal RA.
Generate DRS and control signals S1 and S2. The write control signals WM1, WM2, and WM3 are selectors W
It is supplied to S in common and supplied to memories M1, M2, and M3, respectively. Write address signal WADR
S and the read address signal RADRS are stored in the memories M1 and M.
2, and M3 are commonly supplied. Read control signal RM
1, RM2, and RM3 are supplied to memories M1, M2, and M3, respectively. The control signals S1 and S2 are commonly supplied to the selector RS.

The sequence controller SC is a memory M
1, write control signals WM1, WM2, WM3, WM1 and WM for operating the write operations of M1, M2 and M3 one by one.
2, WM3 ... As a result, the selector WS sequentially selects the memories M1, M2, and M3, and supplies the RGB pixel data SD sequentially supplied from the outside to the selected memory. The write control signals WM1, WM2, and WM3 are switched every time 100 pieces of RGB pixel data SD are supplied. The selection memory writes the RGB pixel data SD sequentially supplied from the selector WS into the write address signal W.
Store in the write memory area specified by ADRS. The write address signal WADRS is the RGB pixel data S.
Updated in the cycle corresponding to the supply rate of D, 100
Each piece of RGB pixel data SD is written in each of the first to 100th memory areas. Further, the sequence controller SC outputs the read control signals RM1 and RM2, RM in order to read the memories M1, M2 and M3 two by two while the write operation is performed.
3 and RM1, RM2 and RM3, RM1 and R
It occurs in the order of M2, RM3 and RM1, RM2 and RM3 ... Each of these two memories reads the RGB pixel data SD from the read memory area designated by the read address signal RADRS, and reads it from the selector RS.
Supply to. The read address signal RADRS is updated in a cycle corresponding to about half the supply rate of the RGB pixel data SD, and 100 RGB pixel data SD are sequentially read from the first to 100th memory areas. The selector RS corresponds to two blocks of RGB pixel data SD read in parallel from two of the memories M1 to M3 under the control of the control signals S1 and S2 to the odd driver part and the even driver part to which these are supplied. Data supply buses SDL1 and SDL2. As a result, the RGB pixel data SD for each horizontal pixel array is divided into 8 blocks, and the 4 odd blocks are respectively driven by the driver unit XT via the data supply bus SDL1.
1, XT3, XT5, and XT7, and the four even-numbered blocks are supplied to the driver units XT2, XT4, XT6, and XT8 via the data supply bus SDL2.

FIG. 5 shows the operation of the flat panel display device constructed as described above. Each horizontal scanning period is composed of a data supply period (= 28 × 800/1024 μs) and a blanking period (= 28 × 224/1024 μs), which corresponds to the number of pixels constituting one horizontal pixel array.
0 pieces of 18-bit RGB pixel data are sequentially supplied to the liquid crystal controller 16 from the outside during this data supply period.
These 800 RGB pixel data SD are selector WS
Are divided into 100 units by the driver units XT1, XT
2, ..., 8 RGB assigned to XT8
It becomes the pixel data blocks DB1-DB8. Memory M
1, M2 and M3 sequentially store these RGB pixel data blocks DB1-DB8. Each of the RGB pixel data blocks DB1-DB8 is 1/8 of the data supply period,
That is, it is written in one of the memories M1, M2 and M3 in one block period (= t) equal to 28 × 100/1024 μs. That is, the RGB pixel data blocks DB1-DB3 are, for example, memories M1, M2, and M.
Sequentially written in 3. These memories M1, M2, and M3 are used for the subsequent RGB pixel data blocks DB4-DB.
It is repeatedly used to store 8 in sequence.

Reading from the memories M1-M3 is performed by the memory M
Writing to 1-M3 is done while being done as described above. In this reading, the RGB pixel data block DB1
-Two consecutive DB8 have two block periods (= 2
It is read in parallel at t). That is, the RGB pixel data blocks DB1 and DB2 are read in parallel from the memories M1 and M2 in the first two block periods (= 2t), and the RGB pixel data blocks DB3 and DB4 are memory in the next two block periods (= 2t). RGB pixel data blocks DB5 and DB6 read in parallel from M3 and M1 are read in parallel from the memories M2 and M3 in the next two block periods (= 2t), and RGB pixel data blocks DB7 and DB
8 are read in parallel from the memories M1 and M2 in the next 2-block read period (= 2t).

The RGB pixel data blocks DB1 and DB2, DB3 and DB thus read in parallel.
4, DB5 and DB6, and DB7 and DB8 are distributed to the data supply buses SDL1 and SDL2 via the read selector RS. That is, odd number RGB
The pixel data blocks DB1, DB3, ..., DB7 are supplied to a data supply bus SDL1 connected to the odd number driver units XT1, XT3, ..., XT7, and the even RGB pixel data blocks DB2, DB4 ,. , XT4, ..., XT8 are supplied to a data supply bus SDL2.

By the way, each of the memories M1 to M3 has 10
Since it has a memory capacity of 0 words x 18 bits,
RGB pixel data exceeding one block cannot be stored. Therefore, this sequence controller SC is 2R
Before the continuous writing of the GB pixel data blocks is completed, parallel reading of these 2 RGB pixel data blocks is started,
Before the end of parallel reading of these 2RGB pixel data blocks, successive writing of the subsequent 2RGB pixel data blocks is started, and the data distribution circuit DST is controlled so that the writing of each RGB pixel data is not overtaken by the reading.

For example, regarding the memory M1, the RGB pixel data block DB1 is written for one block period (= t) and then delayed by a period of Δt for two block periods (=).
2t). That is, the writing of the RGB pixel data block DB4 is started earlier than the reading of the RGB pixel data block DB1 by a period of Δt. However, since the memory M1 has already started reading the RGB pixel data block DB1 at the start of writing the RGB pixel data block DB4, the RGB pixel data of the block DB4 is RG of the block DB1.
The B pixel data is sequentially written in the already read memory area. Therefore, the memory M1 can also store the RGB pixel data block DB4 within a given memory capacity range. By the way, RGB pixel data block DB4
Is also read with a delay of Δt after the writing is completed. This Δ
Since t is set to an arbitrary period from 1 clock period (= 27.7 ns) to 99 clock period (= 2.75 μs), for example, 160 ns, writing of each RGB pixel data may be overtaken by reading. Absent.

Therefore, even if the memory capacity of each of the memories M1 to M3 is 100 words × 18 bits, the RGB pixel data for one horizontal pixel array is provided in the driver units XT1 to XT.
Write at one data rate to one of these memories M1-M3 in 100 blocks processed in 8
Two consecutive blocks can be distributed in parallel from two of the memories M1-M3 to the read data supply buses SDL1 and SDL2 at a rate half the data supply rate. That is, the odd RGB pixel data block D
, DB7 and even RGB pixel data blocks DB2, DB4, ..., DB8 are connected to the odd driver sections XT1, XT3, ..., XT7, and the data supply bus SDL1 and even driver sections XT2, XT are connected.
4, ..., Is supplied to a data supply bus SDL2 connected to XT8. As a result, the RGB pixel data block D
B1 and DB2 are processed in parallel by the driver units XT1 and XT2, and the RGB pixel data block DB
3 and DB4 are processed in parallel by the driver units XT3 and XT4, and the RGB pixel data block DB5
And DB6 are processed in parallel by the driver units XT5 and XT6, and the RGB pixel data blocks DB7 and DB8 are processed in parallel by the driver units XT7 and XT8.

For example, the driver units XT1 and XT2 are R
The following processing is performed while the GB pixel data blocks DB1 and DB2 are supplied in parallel to the data supply buses SDL1 and SDL2.

In the driver section XT1, the first to 100th stages of the shift register circuit SR alternately store the start pulse ST in response to the clock pulse CK. The selection circuit SA responds to the signal from the stage storing the start pulse ST and sequentially selects one corresponding one of the 100 RGB pixel data supplied as the RGB pixel data block DB1 to the data supply bus SDL1. The 3 pixel data (that is, the R pixel data, the G pixel data, and the B pixel data each consisting of 6 bits) included in the RGB pixel data are simultaneously supplied to the latch circuit LA1. The latch circuit LA1 latches the pixel data sequentially supplied from the selection circuit SA corresponding to 100 pieces of RGB pixel data, and supplies these to the latch circuit LA2. The latch circuit LA2 is responsive to the load pulse LD to latch circuit LA.
All pixel data from 1 are latched at once and supplied to the digital-analog converter D / A. The digital-analog converter D / A converts these pixel data into pixel signal voltages and supplies them to the signal lines X1-X300.

In the driver section XT2, the first to 100th stages of the shift register circuit SR alternately store the start pulse ST in response to the clock pulse CK. The selection circuit SA responds to the signal from the stage storing the start pulse ST and sequentially selects one corresponding one of the 100 RGB pixel data supplied as the RGB pixel data block DB2 to the data supply bus SDL2, This RGB pixel data is converted into pixel data of 3 pixels (6 bits of R pixel data, G pixel data, B pixel data) into a latch circuit L.
Supply to A1 at the same time. The latch circuit LA1 latches the pixel data sequentially supplied from the selection circuit SA corresponding to 100 pieces of RGB pixel data, and supplies these to the latch circuit LA2. The latch circuit LA2 latches all pixel data from the latch circuit LA1 at once in response to the load pulse LD, and supplies it to the digital-analog converter D / A. The digital-analog converter D / A converts these pixel data into pixel signal voltages, and converts the pixel signal voltages into signal line X30.
Supply to 1-X600.

Other driver units XT3 and XT4, XT
5 and XT6, and XT7 and XT8 also operate in parallel as described above. The clock pulse CK is applied to the odd driver sections XT1, XT3, ..., XT7 and the even driver section X.
Since T2, XT4, ..., XT8 operate in parallel in this way, they are generated at a frequency of 1/2 that in the case where they do not operate in parallel. Therefore, the driver units XT1-XT
The operating speed of 8 is reduced corresponding to the frequency of this clock pulse CK.

As described above, according to the flat panel liquid crystal display device of the present embodiment, the RGB pixel data for one horizontal pixel array has an information amount of 14 k bits (2400 × 6 bits), but 5 pixels. .4k bit (3 x 100
X 18 bits) Very small memory M1-M3
It becomes possible to perform block driving in which the operating speed of the driver units XT1 to XT8 is reduced by half with the total memory capacity of. Therefore, the liquid crystal controller 16 can be configured with an inexpensive small-scale programmable logic array, and the manufacturing cost of the display device can be reduced. Further, since the frequency of the clock pulse CK is reduced to 1/2, the low speed type shift register circuit SR can be used in each of the driver units XT1 to XT8. This is effective for reducing the power consumption of the display device.

In the above embodiment, one horizontal pixel array worth of RGB pixel data SD corresponds to 8 driver units.
For example, when ten driver units are provided, the RGB pixel data SD for one horizontal pixel array is divided into ten blocks. This allows
The number of 18-bit memory areas provided in each of the memories M1 to M3 can be reduced to 80. The number of driver units is p, which is the number of data supply buses (p is a positive integer of 2 or more).
It is desirable to be set to double. In the above embodiment, the three memories M1 to M3 are provided to drive the odd driver units and the even driver units in parallel. However, these driver units may be divided into three or more groups or blocks and driven in parallel. In this case, the memories M1 to M3 also have to increase corresponding to the number of groups, but the frequency of the clock pulse CK can be reduced to 1 / the number of groups. Therefore,
The operating speed of the shift register circuit SR can be further reduced.
For example, when one horizontal pixel array includes 3072 pixel electrodes, it is conceivable to provide 16 driver units that drive 192 signal lines and divide these into 4 groups by 4 data supply buses. In this case, 7 memories each having 64 18-bit memory areas are used.
The RGB pixel data for the horizontal pixel array may be divided into corresponding 16 blocks and distributed to these 4 data supply buses every 4 blocks. This increases the number of driver units and the number of memories, but the frequency of the clock pulse CK can be reduced to 1/4 of that in the case where 16 driver units are not divided into four groups, so the operating speed and power consumption of the shift register circuit SR are reduced. It can be correspondingly reduced.

In this embodiment, the driver portions XT-XT8 are flexible wiring films X as integrated circuits.
It is fixed on F. However, this integrated circuit may be fixed on the array substrate 101 of the liquid crystal panel 3 using an anisotropic conductive film or the like, and may be connected to the data supply buses SDL1 and SDL2 on the array substrate 101. In this case, since the signal line drive circuit board 5A is not necessary, the size of the outer portion of the display area 2 can be reduced. Further, if the signal line driving circuit 12 is formed on the array substrate 101 so as to be connected to the signal line 103 by using polycrystalline silicon or the like in the manufacturing process of the liquid crystal panel 3, the signal line 103 is manufactured after the liquid crystal panel 3 is manufactured. The troublesome work of connecting the signal line drive circuit 12 with the signal line drive circuit 12 can be omitted.

FIG. 6 shows a modification of the liquid crystal controller shown in FIG. In this modification, a selector EO, an odd memory OM, and an even memory EM are further provided in the data distribution circuit DST. The selector EO is controlled by the control of the control signal PS supplied from the sequence controller SC, and alternately supplies the RGB pixel data sequentially supplied from the outside to the odd memory OM and the even memory EM.
The odd-numbered memory OM and the even-numbered memory EM are 18-bit memories each storing 1 RGB pixel data, and store the RGB pixel data respectively supplied from the selector EO and supply them to the selector WS. The selector WS is supplied from the odd memory OM and the even memory EM, respectively.
The word RGB pixel data is provided to one of the memories M1-M3. Each of the memories M1 to M3 has 50 36-bit memory areas having the same memory capacity as that shown in FIG. 4, and stores 50 2-word RGB pixel data sequentially supplied from the selector WS as one block. . The selector RS supplies two blocks of 2-word RGB pixel data read in parallel from two of the memories M1, M2, and M3 to the data supply buses SDL1 and SD.
Distribute to L2.

In this case, the number of bits of the data supply buses SDL1 and SDL2 is set to 32 bits, the number of stages of the shift register circuit SR is set to 50 in each of the driver sections XT1 to XT8, and the frequency of the clock pulse CK is the above-mentioned. It is set to 1/2 of that in the embodiment. Therefore, the selection circuit SA responds to the signal from the stage storing the start pulse ST and corresponds to one of the 50 2-word RGB pixel data which is sequentially supplied to the data supply bus SDL1 as the RGB pixel data block DB1. And the RGB pixel data is converted into pixel data for 6 pixels (each of 6-bit first R pixel data, first G pixel data, first B pixel data, second R pixel data, second G pixel data, and second B pixel data). ) And is supplied to the latch circuit LA1 at the same time.

According to this modification, the data distribution circuit DS
Although the total memory capacity is increased by 32 bits at T, the number of bits of the data supply buses SDL1 and SDL2 is doubled, so that the number of stages of the shift register circuit SR is halved in each of the driver units XT1 to XT8. Therefore,
The operating speed and power consumption of the shift register circuit SR can be further reduced.

Next, a flat panel display device according to a second embodiment of the present invention will be described. This display device includes a signal line drive circuit 12 shown in FIG. 3 and a liquid crystal controller 1 shown in FIG.
The structure is the same as that of the first embodiment except for 6. The signal line drive circuit 12 has the same configuration as that of the modification described above. FIG. 7 shows a liquid crystal controller 16 of the flat panel display device according to the second embodiment. This LCD controller 1
6 is RGB which is sequentially supplied from the outside similarly to the first embodiment.
The pixel data SD is supplied to the data supply buses SDL1 and SDL.
A data distribution circuit DST distributed to two and a control signal YSEL supplied to the scanning line driving circuit 14 and a start pulse ST and a clock pulse CK supplied to the scanning line driving circuit 14 while controlling the operation of the data distribution circuit DST. , And a sequence controller SC for generating a control signal such as a load pulse LD.

The data distribution circuit DST has a selector EO, an odd memory OM, an even memory EM, a selector WS, memories M1 and M2, and a selector RS. The selector EO alternately supplies the RGB pixel data sequentially supplied from the outside to the odd memory OM and the even memory EM.
The odd-numbered memory OM and the even-numbered memory EM are 18-bit memories each storing 1 RGB pixel data, and store the RGB pixel data respectively supplied from the selector EO and supply them to the selector WS. The selector WS is supplied from the odd memory OM and the even memory EM, respectively.
The word RGB pixel data is provided to one of the memories M1 and M2. Each of the memories M1 and M2 has a memory capacity in which one 36-bit memory area is added to the 50 36-bit memory areas shown in FIG. 6, and 50 2-word RGB pixels sequentially supplied from the selector WS. Data is stored as one block. The selector RS supplies two blocks of 2-word RGB pixel data SD read in parallel from the memories M1 and M2 to the data supply bus S.
Allocate to DL1 and SDL2.

In order to control the operations of the selector EO, the selector WS, the memories M1 and M2, and the selector RS, the sequence controller SC makes the control signal PS,
Write control signals WM1 and WM2, write address signal W
It generates ADRS, read control signals RM1 and RM2, read address signals RADRS1 and RADRS2, and control signals S1 and S2. The control signal PS is supplied to the selector EO. Write control signals WM1 and WM2
Are commonly supplied to the selector WS and also supplied to the memories M1 and M2, respectively. Write address signal WA
DRS is commonly supplied to memories M1 and M2, and read address signals RADRS1 and RADRA2 are supplied to memories M1 and M2, respectively. Read control signal R
M1 and RM2 are supplied to memories M1 and M2, respectively. The control signals S1 and S2 are commonly supplied to the selector RS.

The sequence controller SC is a memory M1.
And write control signals WM1, WM2, WM2, WM1, WM1 and WM2 for operating M2 one by one.
It occurs in the order of ... The selector WS selects one of the memories M1 and M2 based on the above-mentioned write control signal, and the odd memory OM and the even memory EM are selected as the selected memory.
The 2-word RGB pixel data SD sequentially supplied from The write control signals WM1 and WM2 are 50 2
It is updated each time the word RGB pixel data SD is supplied. The selected memory is 2 words R sequentially supplied from the selector WS.
The GB pixel data SD is stored in the write memory area designated by the write address signal WADRS. The write address signal WADRS is updated at a cycle corresponding to the supply rate of the 2-word RGB pixel data SD, and 50 RGs are updated.
The B pixel data SD is written in each of the first to 50th memory areas or the second to 51st memory areas. The ranges of these write memory areas are used alternately. Sequence controller SC
Thus, while the write operation is performed, read control signals RM1 and RM2 are generated to cause memories M1 and M2 to perform the read operation. Each of these two memories reads 2-word RGB pixel data SD from the read memory area designated by the corresponding read address signal RADRS1 or RADRS2 and supplies it to the selector RS. The read address signals RADRS1 and RADRS2 are updated in a cycle corresponding to about half the supply rate of the 2-word RGB pixel data SD from the selector WS, and are stored in the first to 50th memory areas of one of the memories M1 and M2. 50 2-word RGB pixel data S written
The 50 2-word RGB pixel data SD written in the second to 51st memory areas of the D and the memories M1 and M2 are sequentially read. The selector RS controls the memory M1 by controlling the control signals S1 and S2.
And RGB of 2 blocks read in parallel from M2
The data supply bus SD corresponding to the odd-numbered driver section and the even-numbered driver section to which the pixel data SD should be supplied.
Sort to L1 and SDL2. As a result, 2-word RGB pixel data SD for each horizontal pixel array is divided into 8 blocks, and 4 odd blocks are divided into data supply buses SD.
Driver units XT1, XT3, XT via L1
8 and XT7, and 4 even blocks are supplied to the driver units XT2 and XT2 via the data supply bus SDL2.
It is supplied to XT4, XT6, and XT8.

FIG. 8 shows the operation of the flat panel display device constructed as described above. Here, in order to facilitate understanding of this operation, it is assumed that one horizontal pixel array is composed of 80 pixels, and each of the driver units XT1, XT2, ..., XT8 drives 10 signal lines. In this case, each of the memories M1 and M2 must have one 36-bit memory area in addition to the five 36-bit memory areas.

When 80 pieces of RGB pixel data SD corresponding to the number of pixels forming one horizontal pixel array are sequentially supplied to the liquid crystal controller 16 from the outside, these 80 RGs are supplied.
The B pixel data SD is alternately supplied to the odd memory OM and the even memory EM by the selector EO. The odd-numbered memory OM and the even-numbered memory EM store the RGB pixel data SD supplied from the selector EO and supply it to the selector WS. The selector WS divides the 2-word RGB pixel data, which is sequentially supplied from the odd-numbered memory OM and the even-numbered memory EM, into five groups, and the driver sections XT1, XT2, ..., X are divided.
Eight RGB pixel data blocks DB1-DB8 are assigned to T8. The memory M1 and the memory M2 are the RGB pixel data blocks DB1-DB.
8 is selectively stored. RGB pixel data block DB
1-DB8 is equal to 1/8 of the data supply period 1
It is written in one of the memories M1 and M2 in the block period (= t).

That is, RGB pixel data block DB
1, DB2, DB3, DB4, DB5, DB6, DB
7 and DB8 are memories M1, M2, M2, M1, M
1, M2, M2, and M1 respectively. Odd RGB pixel data block DB1, DB3, DB5
And DB7 are stored in the memory areas up to addresses 0-4 in the memories M1, M2, M1, and M2, respectively, and the even RGB pixel data blocks DB2, DB4,
DB6 and DB8 are stored in the memory areas up to addresses 1-5 in the memories M2, M1, M2 and M1.

Reading from the memories M1 and M2 is performed while writing to the memories M1 and M2 is performed as described above. In this reading, two consecutive RGB pixel data blocks DB1 to DB8 are read in parallel in a two-block period (= 2t). That is,
The RGB pixel data blocks DB1 and DB2 are stored in the memories M1 and M during the first two block periods (= 2t).
2 are read out in parallel and the RGB pixel data block D
B3 and DB4 are read in parallel from the memories M2 and M1 in the next two block periods (= 2t), and RG
The B pixel data blocks DB5 and DB6 are read in parallel from the memories M1 and M2 in the next two block periods (= 2t), and the RGB pixel data blocks DB7 and DB8 are read in the memory M2 in the next two block reading period (= 2t). And are read in parallel from M1.

The RGB pixel data blocks DB1 and DB2, DB3 and DB thus read in parallel.
4, DB5 and DB6, and DB7 and DB8 are distributed to the data supply buses SDL1 and SDL2 via the read selector RS. That is, odd number RGB
, DB7 are supplied to the data supply bus SDL1 connected to the odd driver sections XT1, ..., XT7, and the even RGB pixel data blocks DB2, DB4 ,.
, And is supplied to the data supply bus SDL2 connected to XT8.

By the way, this sequence controller S
C starts parallel reading of these 2RGB pixel data blocks before the end of the continuous writing of the 2RGB pixel data blocks, and continues the subsequent 2RGB pixel data blocks before the end of parallel reading of these 2RGB pixel data blocks. Data writing is started, and the data distribution circuit DST is controlled so that writing of each RGB pixel data is not overtaken by reading. Further, since each of the memories M1 and M2 has an extra memory area for 2-word RGB pixel data, overlapping of the read address and the write address can be avoided.

For example, the RGB pixel data block DB1 is written in the memory M1 during the first block period, and RG
The B pixel data block DB2 is written in the memory M2 in the second block period. These RGB pixel data blocks DB1 and DB2 are read in parallel from the memories M1 and M2 in the second and third block periods. The memory M2 is used for writing and reading the RGB pixel data block DB2 in the second block period. However, the read start is one 2-word RG.
Δ corresponding to the period required to store B pixel data
Delayed by a period of t. Therefore, the first 2-word RGB pixel data included in the block DB2 is set to the address 1
After writing to, the 2-word RGB pixel data can be read.

The memory M2 reads the RGB pixel data block DB2 in the third block period,
It is used to write the pixel data block DB3.
However, since the range of the memory area for storing the RGB pixel data block DB2 and the range of the memory area for storing the RGB pixel data block DB3 are shifted by one memory area, the final two word RGB included in the block DB2
The pixel data can be read from the memory area of address 5, and the final 2-word RGB pixel data contained in the block DB3 can be written in the memory area of address 4.

In an actual display device, one horizontal pixel array is composed of 2400 pixels, and the driver units XT1 and XT are
2, ..., XT8 drive 300 signal lines each. Therefore, each of the memories M1 and M2 has one 36-bit memory area in 50 36-bit memory areas. However, the operation of this display device is basically the same.

Therefore, even if the memory capacities of the memories M1 and M2 are each 50 words × 36 bits, 2 word RGB pixel data for one horizontal pixel array is provided to the driver section X.
Fifty blocks each processed in T1-XT8 write to one of these memories M1 and M2 at the data supply rate, and two consecutive blocks write from two of the memories M1 and M2 to half the data supply rate. Read data supply buses SDL1 and SDL in parallel at the same rate
It can be divided into two. That is, odd RGB pixel data blocks DB1, DB3, ..., DB7 and even RGB pixel data blocks DB2, DB4 ,.
Are odd driver units XT1, XT3, ..., XT7, respectively.
, And data supply bus SDL2 connected to even driver sections XT2, XT4, ..., XT8. As a result, the RGB pixel data blocks DB1 and DB2 are transferred to the driver unit XT1.
And XT2 are processed in parallel, RGB pixel data blocks DB3 and DB4 are processed in parallel by driver units XT3 and XT4, and RGB pixel data blocks DB5 and DB6 are processed in parallel by driver units XT5 and XT6. The pixel data blocks DB7 and DB8 are processed in parallel by the driver units XT7 and XT8.

In the second embodiment, RGB pixel data sequentially supplied from the outside are divided into pixel data blocks by a number corresponding to the number of pixels in one pixel block, and two pixel data blocks are sequentially written in the memories M1 and M2. 2 stored in the memories M1 and M2 during the writing.
Pixel data blocks are read out in parallel, and these two pixel data blocks are read by the data supply buses SDL1 and SDL.
The corresponding one of the two is supplied respectively. Therefore, the total memory capacity of the memories M1 and M2 is sufficiently less than 1/2 of the memory capacity required to store all pixel data for one horizontal pixel array. Further, this memory capacity does not largely depend on the number of pixel data for one horizontal pixel array and the word length of the pixel data. this is,
It is possible to increase the number of data and the word length while maintaining the memory capacity. As a result, it is possible to prevent the manufacturing cost of the flat panel display device from increasing due to the block driving of the horizontal pixel array.

In particular, according to this embodiment, the number of memory areas is increased by "1" in each of the memories M1 and M2, but the memory M3 shown in FIG. 4 can be eliminated instead.

The selector EO, the odd-numbered memory OM, and the even-numbered memory EM can be omitted if it is not necessary to further reduce the operating speed of the driver units XT1 to XT8.
In this case, each memory area of the memories M1 and M2 is RG.
It is composed of 18 bits to store B pixel data.

[0057]

As described above, the flat panel display device and the driving method thereof according to the present invention can maintain a small memory capacity necessary for block driving each horizontal pixel array.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a configuration of a flat panel display device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal panel shown in FIG.

FIG. 3 is a block diagram showing a part of a signal line drive circuit formed on the signal line drive substrate and wiring film shown in FIG.

FIG. 4 is a block diagram showing a liquid crystal controller formed on the control circuit board shown in FIG. 1.

5 is a time chart for explaining the operation of the flat panel display device shown in FIG.

FIG. 6 is a block diagram showing a modification of the liquid crystal controller shown in FIG.

FIG. 7 is a block diagram showing a liquid crystal controller of a flat panel display device according to a second embodiment of the present invention.

8 is a diagram for explaining the operation of the flat panel display device of the second embodiment controlled by the liquid crystal controller shown in FIG.

9 is a diagram for explaining the operation of the flat panel display device of the second embodiment controlled by the liquid crystal controller shown in FIG.

[Explanation of symbols]

3 ... Display panel, XT1-XT8 ... Driver section, SDL
1, SDL2 ... Data supply bus, 16 ... Liquid crystal controller, M1-M3 ... Memory, DST ... Data distribution circuit, S
C ... Sequence controller.

Claims (20)

[Claims] 1. A display panel in which a plurality of pixels are arranged in a matrix and pixels in each row form one horizontal pixel array,
Pixels of each horizontal pixel array are divided into a plurality of continuous pixel blocks and driven respectively, a plurality of driver units, M data supply buses to which these driver units are sequentially connected, and pixels sequentially supplied from the outside. Control means for distributing data to the M data supply buses, each of the control means being capable of reading from another area during writing to one area, and outputting pixel data corresponding to one block of pixels. A data distribution circuit including a plurality of memory units for storing the total memory capacity of these memory units is smaller than a memory capacity for storing all pixel data of one horizontal pixel array, and pixel data sequentially supplied from the outside. Each pixel data block is divided into pixel data blocks corresponding to the number of pixels in one pixel block, and M pixel data blocks are sequentially written in the M memory units. Control for reading in parallel the M pixel data blocks stored in these M memory units and supplying these M pixel data blocks to the corresponding ones of the M data supply buses. A flat panel display device having a control circuit for performing the following. 2. The flat memory according to claim 1, wherein the total memory capacity of the plurality of memory units is set to be less than half the memory capacity for storing all pixel data for one horizontal pixel array. Panel display device. 3. The M number of data supply buses are composed of first and second data supply buses, and the number of the driver units is set equal to an integral multiple of two. Flat panel display device. 4. The data distribution circuit has a memory capacity capable of storing a number of pixel data each corresponding to the number of pixels of one pixel block, and one is selected for writing each pixel data block. The control circuit includes first, second, and third memory units selected two by two for reading consecutive two-pixel data blocks in parallel, and the control circuit does not overlap the write region and the read region. While writing all the pixel data of each pixel data block into one of the first, second and third memory units in a predetermined period, two consecutive pixel data are paralleled in a period twice the predetermined period. 4. The flat panel display device according to claim 3, further comprising a sequence controller that controls reading from two of the first, second, and third memory units. 5. Each pixel data is color pixel data representing a gradation of a plurality of color components, and each driver unit has one
The flat panel display device according to claim 4, wherein the flat panel display device is configured to drive a number of pixels equal to the number of color components corresponding to color pixel data. 6. The data distribution circuit has conversion means for converting two pieces of pixel data sequentially supplied from the outside into two-word pixel data, and respective areas of each memory section are sequentially supplied from this conversion means. 5. The flat panel display device according to claim 4, wherein the flat panel display has a word length set to double the number of bits of one pixel data to store the two word pixel data. 7. The data distribution circuit has a memory capacity capable of storing a number of pixel data that is at least one greater than the number corresponding to the number of pixels in one pixel block, and writes each pixel data block. A first and a second memory portion, both of which are selected for reading the consecutive two pixel data blocks in parallel.
The control circuit writes all pixel data of each pixel data block into one of the first and second memory units for a predetermined period without overlapping the writing region and the reading region, and doubles the predetermined period. 4. The flat panel display device according to claim 3, further comprising a sequence controller that controls reading of continuous two pixel data from the first and second memory units in parallel during the period. 8. Each pixel data is color pixel data representing a gradation of a plurality of color components, and each driver unit has one
The flat panel display device of claim 7, wherein the flat panel display device is configured to drive a number of pixels equal to the number of color components corresponding to color pixel data. 9. The data distribution circuit has a conversion means for converting two pieces of pixel data sequentially supplied from the outside into two-word pixel data, and respective areas of each memory section are sequentially supplied from this conversion means. 8. The flat panel display device according to claim 7, wherein the flat panel display device has a word length that is set to twice the number of bits of one pixel data to store the two word pixel data. 10. A display panel in which a plurality of pixels are arranged in a matrix and pixels in each row form one horizontal pixel array, and first and second pixel blocks obtained by dividing the pixels of each horizontal pixel array. A first and a second driver unit for driving and a control unit for distributing pixel data for one horizontal pixel array to the first and second drive circuits are provided, and the control unit has a total memory capacity of one horizontal pixel array. The memory means has a plurality of memory areas smaller than the memory capacity corresponding to the number of pixel data of, and is capable of reading from another area while writing in one area, and the pixel data sequentially supplied at a predetermined rate. And writing pixel data to be distributed to the first and second block drive circuits from the memory means in parallel during the writing.
A flat panel display device having a control circuit for selecting a writing area and a reading area of the memory means in a predetermined pattern so that an area for storing already read pixel data can be written. 11. A display panel in which a plurality of pixels are arranged in a matrix and each row of pixels constitutes one horizontal pixel array, and M pixel blocks obtained by dividing the pixels of each horizontal pixel array are respectively driven. M driver parts,
A control unit for distributing pixel data for one horizontal pixel array to the M driver units, the control unit having a plurality of total memory capacities smaller than a memory capacity corresponding to the number of pixel data for one horizontal pixel array. And a memory means capable of reading from another area during writing to one area, and pixel data sequentially supplied to this memory means, and during this writing, from the memory means Pixel data to be distributed to the M driver units are read in parallel, and the writing area and the reading area of the memory means are selected in a predetermined pattern so that the area for storing the already read pixel data can be written. A flat panel display device having a control circuit for controlling. 12. A display panel in which a plurality of pixels are arranged in a matrix and pixels in each row form one horizontal pixel array, and a plurality of pixels which are driven by dividing each pixel of each horizontal pixel array into a plurality of continuous pixel blocks. Driver part of
Each of the driver units is provided with M data supply buses to which the driver units are sequentially connected, and control means for distributing pixel data sequentially supplied from the outside to the M data supply buses. It is possible to read from another area during writing, and includes a plurality of memory units for storing pixel data corresponding to pixels of one block, and the total memory capacity of these memory units is one horizontal pixel array worth of pixel data. In a driving method of a flat panel display device having a data distribution circuit having a memory capacity smaller than the memory capacity for storing all pixel data, pixel data sequentially supplied from the outside is converted into pixel data blocks for each number corresponding to the number of pixels of one pixel block. The first step of partitioning and M pixel data blocks are
A second step of sequentially writing the M pixel data blocks stored in the M memory units in parallel during the writing, and the M pixel data blocks are written in the M step. A method of driving a flat panel display device, comprising a third step of supplying the data to a corresponding one of the data supply buses. 13. The flat according to claim 12, wherein the total memory capacity of the plurality of memory units is set to be less than half of a memory capacity for storing all pixel data for one horizontal pixel array. Driving method for panel display device. 14. The M data supply buses are composed of first and second data supply buses, and the number of the driver units is set equal to an integral multiple of two. Driving method for flat panel display device. 15. The data distribution circuits each have a memory capacity capable of storing a number of pixel data corresponding to the number of pixels of one pixel block, and are selected one by one to write each pixel data block. First selected two by two for reading consecutive two pixel data blocks in parallel,
The second step includes the second and third memory sections, and the second step is to perform the first and second all pixel data of each pixel data block in a predetermined period without overlapping the writing area and the reading area.
And while writing to one of the third memory units, read in parallel two consecutive pixel data in a period twice this predetermined period from two of the first, second and third memory units. 6. The method according to claim 1, further comprising a substep of issuing.
4. The method for driving the flat panel display device according to item 4. 16. Each pixel data is color pixel data representing a gradation of a plurality of color components, and each driver unit drives a number of pixels corresponding to the number of color components corresponding to one color pixel data. The method for driving a flat panel display device according to claim 15, wherein the flat panel display device is configured. 17. The data distribution circuit has a conversion means for converting two pieces of pixel data sequentially supplied from the outside into two-word pixel data, and respective areas of each memory section are sequentially supplied from this conversion means. 16. The method of driving a flat panel display device according to claim 15, further comprising a word length set to double the number of bits of one pixel data to store two word pixel data. 18. The data distribution circuit has a memory capacity capable of storing a number of pixel data which is at least one greater than the number corresponding to the number of pixels of one pixel block, and writes each pixel data block. The first and second memory sections are selected for reading the consecutive two pixel data blocks in parallel, and the second step includes a writing area and a reading area. All pixel data of each pixel data block are written into one of the first and second memory units for a predetermined period without being overlapped, and two consecutive pixel data are parallel in a period twice the predetermined period. The method of driving a flat panel display device according to claim 14, further comprising a sub-step of reading from the first and second memory units. 19. Each pixel data is color pixel data representing a gradation of a plurality of color components, and each driver unit drives a number of pixels equal to the number of color components corresponding to one color pixel data. The method of driving a flat panel display device according to claim 18, wherein the flat panel display device is configured. 20. The data distribution circuit has conversion means for converting two pieces of pixel data sequentially supplied from the outside into two-word pixel data, and respective regions of each memory section are sequentially supplied from this conversion means. 19. The method for driving a flat panel display device according to claim 18, wherein the word length is set to double the number of bits of one pixel data to store the two word pixel data.