KR100580550B1 - Block Sequential Driving Method and Apparatus Thereof - Google Patents

Abstract

The present invention relates to a block sequential driving device for preventing distortion of pixel voltages in each block boundary part.

The block sequential driving apparatus according to the present invention includes a memory block for generating an image signal applied to a boundary of each block, and a clock count for generating a control signal to control a switch element corresponding to the memory block and the boundary of the blocks.

Accordingly, the block sequential driving device according to the present invention prevents the distortion of the pixel voltage.

Description

Block Sequential Driving Method and Apparatus Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a block sequential driving method and a device for preventing distortion of pixel voltages in each block boundary part.

In general, a block sequential driving method of a liquid crystal display (hereinafter referred to as "LCD") includes n thin film transistors (hereinafter referred to as "TFTs"). Blocks are sequentially operated and analog video signals supplied from the outside are charged in the respective data lines.

Referring to FIG. 1, a conventional block sequential driving LCD is illustrated. The liquid crystal panel 6 is provided with n blocks composed of m TFTs. These blocks are sequentially driven to charge analog data signals externally applied to each data line. Meanwhile, when an arbitrary k block (ie, 1 <k ≦ n) is operated, the TFTs of the k-1 block are turned off, so that each data line connected thereto is floating. As a result, a coupling capacitor (for example, Cdd, Cdp) is formed as shown in FIG. 2 by the signal charged to the first data line of the k block, so that the m-th data line of the k-1 block in the floating state is formed. And the voltage of the pixel electrode is distorted. In this case, a coupling capacitor (ie, Cdd) exists between the m-th data line dm-1 and the m-th data line dm formed on the lower substrate 8, and the m-th data line ( A coupling capacitor (that is, Cdp) is also present between dm) and the n-th pixel electrode Pn-1. As described above, the conventional block sequential driving method has a problem in that the pixel voltage at the boundary of each block is distorted by the next block. In order to alleviate this problem, a superposition driving method for driving precharging or neighboring blocks is proposed. The overlap driving method will be described with reference to FIG. 3. The overlap driving method is a method of sequentially applying the video signal to the first to n-th blocks B1 to Bn as shown in FIG. 3. In this case, while the video signal of the overlapping first block B1 and the video signal of the second block B2 overlap, the second block B2 performs precharging and the second block in the other area. Block B2 charges the video signal. However, even when such an overlap driving method is used, not only the distortion of the pixel voltage between the block boundaries is completely solved, but also a problem of increasing power consumption has been derived.

Accordingly, it is an object of the present invention to provide a block sequential driving method and apparatus for preventing pixel voltage distortion of each block boundary portion.

In order to achieve the above object, the block sequential driving method according to the present invention sequentially applies the video signal to a switch element corresponding to a boundary of each block.

In addition, the block sequential driving device according to the present invention generates a control signal to control a memory block for generating a video signal and a block edge video signal applied to the boundary of each block, and a switch element corresponding to the boundary of the memory block and blocks. And a clock count.

Other objects and features of the present invention other than the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

A preferred embodiment of the present invention will be described with reference to FIGS. 4 to 9.

Referring to FIG. 4, a block sequential driving device according to the present invention includes a data driving integrated circuit 22 for applying a video signal, a memory block 24 for generating a block edge video signal, and a video signal corresponding to a control signal. And a clock switch 30 that applies a TFT switch 26 for applying a block edge image signal to each block and a control signal for controlling the memory block 24, and controls a switch corresponding to a boundary of each block. It is provided. The data driving integrated circuit 22 sequentially applies m number of image signals to the first to nth blocks B1 to Bn. In this case, m video signals applied from the data driver integrated circuit 22 are applied to the m TFT switches provided in each block. On the other hand, the clock count 30 controls the first to n th control signals CS1 to CSn applied to the memory block 24 and the n + 1 control applied to a TFT switch corresponding to a boundary of the TFT switches 26. The signal CSn + 1 is generated. At this time, the n + 1th control signal has a high level voltage during the time that the first to nth blocks are turned on.

The memory block 24 generates a block edge image signal using the image signal of the data driver integrated circuit 22. As shown in FIG. 5, the first to nth memory blocks are provided in the memory block 24, and the first to nth control signals CS1 to CSn are supplied to each block. In addition, each block is provided with a video signal port for transmitting a video signal and a memory 32 for storing the video signal, as shown in FIG. 6, and a switch 34 switched corresponding to the control signal CS. Consists of Hereinafter, the operation of the memory block will be described. When the high level first control signal CS1 is applied to the first memory block MB1, the switch 34 is connected to the image signal port to transmit the image signal to the outside. At this time, the external memory 32 stores the video signal by the control signal. On the other hand, when the first control signal has a low level, the switch 34 is connected to the memory 32, and the image signal stored in the memory 32 is controlled by the control of the switch 34. It outputs to the path formed by switching. That is, the image signal is output to the m th data line by the first control signal having the high level during the time T1 when the first block is turned on. On the other hand, since the first control signal has a low level during the time when the first block is turned off, the image signal stored in the memory 32 is output to the m-th data line. To this end, the n + 1th control signal CSn + 1 having a high level is applied during the time periods T1 to Tn when the first to nth blocks B1 to Bn are turned on. The second to nth memory blocks MB2 to MBn are also driven in the same manner as the first memory block BM1. Accordingly, the sequential block driving apparatus according to the present invention prevents distortion of the pixel voltage by applying an image signal to the boundary data line of each block.

Referring to FIG. 7, a block sequence driving apparatus according to another embodiment of the present invention is shown. In a block sequential driving device according to another embodiment of the present invention, the first switch element and the last (m) switch element of odd-numbered blocks B1, B3, ..., Bn-1 are the n + 1 control signals CSn +. 1) It has a structure connected to a line. In addition, the second switch elements of the odd-numbered blocks B1, B3, ..., Bn-1 and the first switch elements of the even-numbered blocks B2, B4, ..., Bn of the first to nth blocks The first to nth control signal CS1 to CSn lines are connected to each other. On the other hand, the block edge video signal line has a structure connected to the first switch element and the last switch element of the odd-numbered blocks (B1, B3, ..., Bn-1). In this case, two block edge video signal lines are provided in each of the odd-numbered blocks B1, B3, ..., Bn-1, and thus require n pieces. Operation according to another embodiment of the present invention has been described fully in FIG. 4, so a detailed description thereof will be omitted. In the block sequential driving device according to an embodiment of the present invention, a block edge image signal is supplied to each block by applying a control signal to the last switch element of each block, and according to another embodiment of the present invention. The configuration of the block sequential driving device is to apply a control signal to the first switch and the last switch of the odd block so that the block edge image signal is supplied to the first and the last switch of the odd block. That is, the video signal is applied to the switch element corresponding to the boundary of each block. In addition, the same method as described above may be applied to the first and last switches of the even-numbered blocks according to the designer's intention. Accordingly, the block sequential driving apparatus according to another embodiment of the present invention applies the image signal to the first and last data lines of the odd-numbered block to prevent the distortion of the pixel voltage.

8, a block sequential driving method according to the present invention will be described. For example, the block sequential driving method according to the present invention will be described in detail in the case where the number of blocks n = 5 in the block sequential driving apparatus shown in FIG. 7. The first to fifth control signals CS1 to CS5 are sequentially applied to the switches 34 of the first to fifth blocks as shown in FIG. 8. Meanwhile, the video signal is continuously applied to the first and last switches of the odd-numbered blocks B1, B3, and B5 by the sixth control signal CS6. In this case, the first to fifth control signals CS1 to CS5 maintain the high voltage level only during the turn-on time T of each block, while the sixth control signal CS6 is configured to be the first. The high voltage level is continuously maintained during the turn-on times T1 to T5 of the fifth to fifth blocks. Accordingly, the sixth control signal CS6 is continuously applied to the first and last data lines of the odd-numbered blocks during the turn-on times of the first to fifth blocks (T1 to T5). The first control signal CS1 maintains the high voltage level during the turn-on time T1 of the first block, so that the switches of the first block B1 connected thereto are turned on and input from the outside. Signals are charged to each data line and pixel. At this time, since the sixth control signal CS6 also maintains the high voltage level, the first and last data lines and pixels of the first block are also charged. In addition, during the turn-on time T2 of the second block, the first control signal CS1 maintains a low voltage level while the second control signal CS2 maintains a high voltage level. The switches of the first block B1 to which the first control signal CS1 is applied are turned off and the data line connected thereto is in a floating state. On the other hand, the switches of the second block B2 to which the second control signal CS2 is applied are turned on so that image signals input from the outside are charged in each data line and pixel of the second block B2 through them. . At this time, since the sixth control signal CS6 is continuously at the high voltage level, image signals corresponding to the first and last data lines of the first block B1 stored in the external memory 32 are input again. The first and last data lines and pixels of the first block B1 are recharged through a switch connected to the sixth control signal. As such, by recharging the signal to the data line corresponding to the boundary of the first block B1, the data line and the pixel voltage are prevented from being distorted in the conventional block sequential driving method. In this case, a block edge signal applied to the data line corresponding to the boundary of each block is shown in FIG. 9. In this case, the block edge signal applied to the boundary of each block is continuously applied after the video signal of the corresponding block is applied. In addition, according to the designer's intention, the same method as described above may be applied to the first and the last switches of the even-numbered blocks or the first or the last switches of each block. Accordingly, the block sequential driving method according to the present invention repeatedly applies a signal to the boundary data line of the block to prevent distortion of the pixel voltage.

As described above, the block sequential driving method and apparatus according to the present invention have an advantage of preventing the distortion of the pixel voltage by applying an image signal to the switch element corresponding to the boundary of the block.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view illustrating a conventional block sequential driving method.

FIG. 2 is a diagram for explaining coupling occurring between adjacent pixels. FIG.

3 is a view for explaining the overlapping driving method of a conventional block sequential driving method.

4 is a view showing the configuration of a block sequential drive device according to the present invention.

5 is an enlarged view illustrating a configuration of the memory block of FIG. 3.

FIG. 6 is a detailed view of one memory block of FIG. 4; FIG.

7 is a diagram illustrating a configuration of a block sequence driving apparatus according to another embodiment of the present invention.

8 is a view for explaining a block sequential driving method according to the present invention.

9 is a diagram showing an input form of a signal according to the block sequential driving method;

<Description of Symbols for Main Parts of Drawings>

22: data driving integrated circuit 4: gate driving integrated circuit

6,28: liquid crystal panel 8: lower substrate

10a, 10b: insulating film 24: memory block

26: thin film transistor switch 30: clock counter

32: memory 34: switch

Claims (6)

In the block sequential driving device having a data driving integrated circuit for sequentially applying a video signal to the n blocks consisting of m switch elements, A memory block generating an image signal applied to a boundary of each block; A clock count generating a control signal to control a switch element corresponding to the memory block and the boundary of the blocks; The memory block, And first to n-th memory blocks each having a video signal port for transmitting the video signal, a memory for storing the video signal, and a switch for switching the video signal. The method of claim 1, The clock count sequentially generates first to nth control signals for controlling the first to nth memory blocks, and generates an n + 1 control signal for controlling switch elements corresponding to boundary portions of the blocks. Block sequential drive device characterized in that. In the block sequential driving method of sequentially applying the video signal to the n blocks consisting of m switch elements each of which is driven, The video signal is sequentially applied to the switch element corresponding to the boundary of each block, The image signal is applied to the switch elements corresponding to the boundary of the n-th block during the time when the n-th block is turned on, and the boundary of the n-th block during the time when the n-th block is turned on. And a block edge image signal is applied to the switch elements corresponding to the block sequence driving method. The method of claim 3, wherein And applying an n + 1th control signal having a high level to the switch element corresponding to the boundary of each block during the time when the video signal and the first to nth blocks are turned on. The method of claim 3, wherein A block sequence characterized by applying an n + 1th control signal having a high level to a first switch element and an mth switch element of the odd-numbered block during a time when the first to nth blocks are turned on Driving method. The method of claim 3, wherein A block sequence characterized by applying an n + 1 th control signal having a high level to a first switch element and an m th switch element of the even-numbered block during a time when the first to n-th blocks are turned on; Driving method.