JPH10307567A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain undistorted excellent display performance of an image by arranging video signal buses in an electrically insulated condition with every signal conductor driving block. SOLUTION: First and second transmission lines 105 to 112 respectively and independently constitute video signal buses connected to a display panel controller 702. These video signal buses have a video signal input terminal in a boundary part (on one end part side of 101 to 104) of respective driving blocks on a display panel 701, and are formed so as to extend by crossing with connecting wiring to connect shift registers 101 to 104 and analog switches 113 to 116 to each other. The video signal buses 105 to 112 belonging to the respective driving blocks 11 to 14 are arranged so as to be electrically insulated from each other. As a result, the respective video signal buses 105 to 112 do not cross with wiring in the other driving blocks 11 to 14, and load capacity can be reduced, and a band characteristic can be largely improved. Therefore, an excellent image can be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device such as a liquid crystal display device, and more particularly to a drive circuit integrated display device in which elements for switching pixels by a thin film transistor and a drive circuit are formed on the same substrate.

[0002]

2. Description of the Related Art Liquid crystal display devices have come to be used in various fields including television display applications and OA applications, taking advantage of their features of thinness, light weight, low power consumption, and narrow frame. As a method of realizing this liquid crystal display device at low cost,
There has been proposed a method of integrally integrating a drive circuit on a transparent substrate that attacks a liquid crystal display device.

In this liquid crystal display device integrated with a driving circuit, a thin film transistor for driving pixels arranged in a matrix, a scanning line driving circuit for driving a scanning line for controlling a gate of the thin film transistor, and a signal line connected to a source are provided. The signal line driving circuit to be driven is manufactured by the same process.

The signal line driving circuit includes an analog switch group that samples a video signal supplied from the outside and supplies the signal line to a signal line, and a shift register that supplies a timing signal for controlling a sampling operation of the analog switch. A common video signal bus is connected to the analog switch group.

Incidentally, since the analog switch and the shift register are constituted by thin film transistors,
There are certain limitations on the current drive capability of the switch and the operating speed of the shift register. For this reason, it is conceivable to divide the analog switch group into a plurality of blocks and operate the divided blocks in parallel with each other, thereby expanding the sampling time margin.

In this case, a display is obtained by providing a plurality of video signal buses corresponding to the number of blocks and connecting analog switches of each block operating at the same timing to different video signal buses.

[0007]

However, in the above-described liquid crystal display device, the number of intersections between the connection portion between the analog switch and the video signal bus and other video signal buses not connected to the analog switch increases. At a location, a stray capacitance is formed between the connection portion and the video signal bus. Then, there is a problem that the band of the video signal transmitted on the video signal bus is narrowed, and good image display cannot be obtained.

In particular, as the screen size and definition of a liquid crystal display device increase, it is necessary to increase the number of blocks of a driving circuit. In view of the above technical background, an object of the present invention is to provide a drive circuit-integrated display device capable of obtaining a good display corresponding to a large screen and a high definition.

[0009]

According to the present invention, in order to solve the above-mentioned problems, video signal buses are individually arranged for each signal line drive block and supplied to the signal line groups from outside the display panel substrate. Received individual video signals,
A display device including a plurality of signal line drive blocks that performs the operation of driving the signal line groups based on these individual video signals in parallel is used.

According to the display device of the present invention, since the video signal bus is provided in each signal line drive block so as to be electrically insulated from each other, the intersection between the video signal bus and the wiring in another drive block is also provided. Since the load capacity can be reduced, the band characteristics of the video signal bus can be significantly improved.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 schematically shows a circuit arrangement of a liquid crystal display device. This liquid crystal display device is, for example, an active matrix liquid crystal display panel that displays television broadcast images in color. This liquid crystal display device includes a display panel substrate 701 using a glass substrate, a plurality of display pixels 710 arrayed in a matrix on the display panel base 701, and a display panel substrate 701 along a column of the plurality of display pixels 710. The plurality of signal lines 707 formed thereon and the plurality of display pixels 70
7, a plurality of scanning lines 708 formed on the display panel substrate 701 along a row of 7, and a thin film transistor having a coplanar structure formed at an intersection of the scanning lines 707 and the signal lines 708 and having, for example, a channel made of a polycrystalline silicon film. And a plurality of switching elements 709 composed of Each switching element 709 is connected to a corresponding scanning line 7.
In response to driving of the signal line 08, the corresponding signal line 708 is supplied to the corresponding display pixel 710. Each display pixel 710 includes a pixel electrode E1 and a counter electrode E2 that are capacitively coupled via a liquid crystal layer 711. The liquid crystal display device includes a scanning line driving circuit YD and a signal line driving circuit XD formed outside a plurality of display pixels 710 on a display panel substrate 701.
And further comprising: The signal line driver circuit XD and the scanning line driver circuit YD are formed using thin film transistors formed in the same step as the thin film transistor of the switch element 709. The scanning line driving circuit YD includes a plurality of scanning lines 708.
And the plurality of scanning lines 7 every one vertical scanning period.
08 is driven line-sequentially. The signal line driving circuit XD is connected to the plurality of signal lines 707, and switches the plurality of signal lines 707 every one horizontal scanning period in which one row of display pixels is selected by driving a scan line formed along these display pixels. Drive. The scanning line driving circuit YD and the signal line driving circuit XD are controlled by a display panel controller 702 arranged outside the display panel substrate 701.

The connection between the display panel controller 702 and the display panel substrate 701 is made only on one side of the signal line drive circuit XD to facilitate mounting. The display panel controller 702 is mounted on a printed wiring board, and the connection between the printed wiring board and the display panel board 701 is performed via a flexible wiring board.

The scanning line driving circuit YD is constituted by a shift register, for example, and operates by controlling a control signal supplied from the display panel controller 702 together with a power supply potential and a ground potential.

As shown in FIG. 2, the signal line driving circuit XD is arranged so as to divide the plurality of signal lines 707 into a plurality of signal line groups each including a predetermined number of adjacent signal lines 707. A plurality of signal line drive blocks which receive the individual video signals SV1 to SV8 supplied for these signal line groups and perform an operation of driving a plurality of signal line groups in parallel based on these individual video signals SV1 to SV8. 11, 12, 13, 14,
··· including. The odd column video signal SV1 and the even column video signal SV2 are supplied to the signal line block 11, the odd column video signal SV3 and the even column video signal SV4 are supplied to the signal line drive block 12, and the odd column video signal SV5 and the even column video are supplied. The signal SV6 is supplied to the signal line driving block 13, and the odd column video signal SV7 and the even column video signal SV8
Are supplied to the signal line drive block 14. These video signals SV1 to SV8 are supplied together with a control signal such as a clock CK and a horizontal start pulse ST. In FIG. 2, each signal line group is indicated by six adjacent signal lines 707 which are fewer than the actual ones in order to avoid complication. The following description is also described accordingly.

The signal line drive blocks 11, 12, 13, 1
Reference numeral 4 denotes first transmission lines 105, 107, 109, and 111 for transmitting the odd-numbered column video signals SV1, SV3, SV5, and SV7.
And the second transmission lines 106, 108, 110, 112 for transmitting the even column video signals SV2, SV4, SV6, SV8.
Are assigned to the six adjacent signal lines 707 and alternately assigned to the first transmission lines 105, 107, 109, 111 and the second transmission lines 106, 108, 110, 112. A group of analog switches 1 sampled and supplied to the corresponding signal line 707
13, 114, 115, 116 and 2 equal to the number of transmission lines
Two adjacent analog switches 113, 114, 115, 1
The monoclock-type shift register 101 is configured as a timing control circuit that divides the analog switches 113, 114, 115, and 116 into a plurality of analog switch groups each including 16 and sequentially performs a sampling operation on the plurality of analog switch groups. ,
102, 103, and 104. These components are similarly configured in the signal line drive blocks. When each signal line group is composed of six adjacent signal lines to avoid complication, the number of analog switch groups is three. First and second transmission lines 105 and 1
06, 107 and 108, 109 and 110, 11
Reference numerals 1 and 112 each independently constitute a video signal bus connected to the display panel controller 702. These video signal buses are provided on the display panel 701 at the boundaries between the drive blocks (101, 102, 103, 1 in this embodiment).
04 has a video signal input terminal, and is formed so as to extend crossing a connection wiring connecting the shift registers 101, 102, 103, 104 and the analog switches 113, 114, 115, 116. The video signal buses belonging to each drive block are arranged so as to be electrically insulated from each other. As a result, each video signal bus does not intersect with the wiring in another drive block, the load capacity can be reduced, and the band characteristics can be greatly improved. The first and second transmission lines have the same wiring length and parasitic capacitance, that is, wiring load, between the signal line driving blocks. The first transmission lines 105, 107, 109, 111 are odd-numbered analog switches 113, 114, 115, 11
6, and the second transmission lines 106, 108, 110, 112 are connected to the even-numbered signal lines 707 via the even-numbered analog switches 113, 114, 115, 116. You. These transmission lines 1
05 to 112 are formed in the same step as the step of forming the source / drain electrodes of the thin film transistor which is the switching element 709. Shift registers 101, 102, 103,
Numeral 104 designates a number of flip-flops equal to the number of analog switch groups connected in series.
The output terminals SR11, SR12, SR1 are shifted in the forward direction to the last flip-flop in response to K.
3: SR21, SR22, SR23; SR31, SR3
2, SR33; enable signals are sequentially generated from SR41, SR42 and SR43. Each flip-flop is a known CMOS clocked inverter circuit, and is configured by combining a thin film transistor formed in the same process as the thin film transistor of the switching element 709. still,
The shift registers 101 to 104 are of the monoclock type, but may be configured to respond to the clock CK and the reverse clock. In addition, these shift registers 1
01 to 104 are not power supplied directly from the outside,
For example, it may be configured to operate with power supplied via a power supply line and a ground line (not shown) formed as a common bus traversing the signal line drive blocks 11 to 14.

FIG. 3 shows the operation of the signal line drive circuit XD.
The shift registers 101, 102, 103 and 104 are shown in FIG.
In response to the clock CK, as shown in FIG.
SR12, SR13; SR21, SR22, SR23;
SR31, SR32, SR33; SR41, SR42,
The operation of sequentially generating the enable signal from the SR 43 is performed in parallel. That is, the enable signal is output from the output terminals SR11, SR21, SR31 and S in the first clock cycle.
R41, the output S at the second clock cycle.
Output from R12, SR22, SR32, SR42,
In the third clock cycle, the output terminals SR13, SR23, S
It is output from R33 and SR43, and is output in the same format as described above if there is a subsequent clock cycle. As a result, the odd-numbered column video signals SV1, SV3, SV5, SV7
And even-numbered video signals SV2, SV4, SV6, SV8
Are sequentially sampled by the analog switch group that receives the enable signal in the first to third clock cycles, and supplied to the corresponding signal line 707.

In the first embodiment, the width of the area 117 occupied by the video signal bus shown in FIG. 2 can be reduced. Also,
It is possible to reduce the number of overlapping portions 118 and 119 where the video signal bus intersects the wiring connecting the shift register and the analog switch. Therefore, the signal line driving circuit XD
Can be reduced, and the transmission bandwidth of the video signal line can be improved by reducing the load capacity.

A display panel controller 702 is arranged on one side of the display panel substrate 701 corresponding to the signal line drive circuit XD. This is compared with, for example, a case where a video signal is supplied to the video signal bus from one side of the display panel substrate 701 corresponding to the scanning line drive block YD and the video signal bus is extended corresponding to the span of the signal line drive circuit XD. As a result, the wiring length on the display panel substrate is shortened, and the transmission band of the video signal bus can be improved.

Further, since all the signal line drive blocks sequentially drive the adjacent signal lines 707 of each signal line group in the same direction, there is no need to further rearrange the odd column and even column video signals in accordance with the driving order. Therefore, the circuit scale of the display panel controller can be reduced.

Embodiment 2 Next, a liquid crystal display according to a second embodiment of the present invention will be described with reference to FIGS. This liquid crystal display device has the same configuration as that of the first embodiment except for the matters described below. FIG. 4 shows the configuration of the signal line driving circuit XD of the liquid crystal display device, and FIG. 5 shows the operation of the signal line driving circuit XD.

The signal line drive blocks 11 to 14 are configured as shown in FIG. Signal line drive blocks 11, 12,
Reference numerals 13 and 14 denote odd column video signals SV11, SV13 and SV.
15, first transmission lines 351 and 353 for transmitting SV17,
355, 357 and even-numbered column video signals SV12, SV1
4, a second transmission line 352 for transmitting SV16 and SV18,
354, 356, 358 and six adjacent signal lines 707, respectively, and the first transmission lines 351, 35
3, 355, 357 and second transmission lines 352, 354;
A group of analog switches 311 to 316 and 321 to 32 which are alternately assigned to 356 and 358 and sample the video signals on the corresponding transmission lines and supply them to the corresponding signal lines 707.
6, 331 to 336, 341 to 346, and a plurality of analog switch groups each including two adjacent analog switches equal in number to the number of transmission lines.
316, 321-326, 331-336, 341-
346 are provided as mono-clock-type shift registers 305, 306, 307, and 308 that are configured as timing control circuits that divide each of the analog switch groups 346 and sequentially perform a sampling operation on the plurality of analog switch groups. These components are the arrangement of the first and second signal lines 351 to 358 and the shift registers 305, 306, 307, and 3
Except for the shift direction of 08, the signal line drive blocks have the same configuration. When each signal line group is composed of six adjacent signal lines to avoid complication, the number of analog switch groups is three. First and second transmission lines 351 and 352, 353 and 354, 355
And 356, 357, and 358 each independently constitute a video signal bus connected to the display panel controller 702. These video signal buses are connected to the display panel substrate 70.
1 on the shift registers 305, 306, 307, 308
Has a video signal input terminal at one end or the other end thereof, and has shift registers 305, 306, 307, 308 and analog switches 311 to 316, 321 to 326, 331 to 3
36, 341 to 346 are formed so as to extend crossing the connection wiring connecting them. That is, the transmission lines 351 and 35
2, the video signal input terminals of the transmission lines 353 and 354 are disposed on the multi-terminal side of the shift register 306, and the video signal input terminals of the transmission lines 355 and 356 are disposed at one end of the register 305. The input terminal is arranged on one end side of the shift register 307, and the transmission lines 357 and 3
The 58 video signal input terminals are arranged on the multi-end side of the shift register 308. The first and second transmission lines have the same wiring length and parasitic capacitance, that is, wiring load, between the signal line driving blocks.

First transmission lines 351, 353, 355, 35
7 is an odd-numbered analog switch 311, 313, 31
5; 321, 323, 325; 331, 333, 33
5; connected to odd-numbered signal lines 707 via 341, 343, 345 and second transmission lines 352, 354, 35
6, 358 are even-numbered analog switches 312, 31
4, 316; 322, 324, 326; 332, 33
4, 336; 342, 344, and 346 to the even-numbered signal line 707. These transmission lines 351 to 351
58 is formed in the same step as the source / drain electrode forming step of the thin film transistor as the switching element 709. The shift registers 305, 306, 307, and 308 are composed of flip-flops equal in number to the number of analog switch groups connected in series. Shift register 3
Output terminals SR51, SR52, SR53; SR71, SR7 shift the start pulse ST input to the first flip-flop in the forward direction to the last flip-flop in response to the clock CK.
2. Generate an enable signal sequentially from SR73. The shift registers 306 and 308 shift the start pulse ST input to the last flip-flop in the reverse direction to the first flip-flop in response to the clock CK, thereby outputting the output terminals SR63, SR62, SR61; SR8.
3. An enable signal is sequentially generated from SR82 and SR81. Each flip-flop is a known CMOS clocked inverter circuit, and is formed by combining thin film transistors formed in the same process as the thin film transistor of the switching element 709.

FIG. 5 shows the operation of the signal line drive circuit XD.
The shift registers 305, 306, 307, and 308 are shown in FIG.
In response to the clock CK, as shown in FIG.
SR52, SR53; SR63, SR62, SR61;
SR71, SR72, SR73; SR83, SR82,
The operation of sequentially generating the enable signal from the SR 81 is performed in parallel. That is, the enable signal is output from the output terminals SR51, SR63, SR71 and S71 in the first clock cycle.
R83, and the output terminal S at the second clock cycle.
R52, SR62, SR72 and SR82, and output terminals SR53, SR6 in the third clock cycle.
1, output from SR73 and SR81, and output in the same format as described above if there is a subsequent clock cycle.
Thereby, the odd-numbered column video signals SV11, SV13, SV
15, SV17 and even column video signals SV12, SV1
4, SV16, and SV18 are sequentially sampled by the analog switch group that receives the enable signal in the first to third clock cycles, and supplied to the corresponding signal line 707.

In the second embodiment, the width of the area 360 occupied by the video signal bus shown in FIG. 4 can be reduced. Also,
It is possible to reduce the number of overlapping portions 361 and 362 where the video signal bus intersects with the wiring connecting the shift register and the analog switch. Therefore, the circuit width of the signal line driving circuit XD can be reduced, and the transmission band of the video signal line can be improved by reducing the load capacity.

Embodiment 3 Next, a liquid crystal display according to a third embodiment of the present invention will be described with reference to FIGS. This liquid crystal display device has the same configuration as that of the first embodiment except for the matters described below. FIG. 6 shows the configuration of the signal line drive circuit XD of the liquid crystal display device, and FIG. 7 shows the operation of the signal line drive circuit XD.

The signal line drive blocks 11 to 14 are configured as shown in FIG. Signal line drive blocks 11, 12,
Reference numerals 13 and 14 denote odd column video signals SV31, SV33, and SV.
35, first transmission lines 209, 211 for transmitting SV37,
213, 215 and even-numbered column video signals SV2, SV4, S
Second transmission lines 210, 212, and 2 for transmitting V6 and SV8.
14, 216 and six adjacent signal lines 707, respectively, and the first transmission lines 209, 211, 213,.
215 and the second transmission lines 210, 212, 214, 21
A group of analog switches 220 to 225, 226 to 231, and 232 that are alternately assigned to 6 and are supplied to the king signal line 707 where the video signal on the corresponding transmission line is to be sampled.
To 237, 238 to 243, and a plurality of analog switch groups each including two adjacent analog switches equal to the number of transmission lines.
226 to 231, 232 to 237, and 238 to 243, each of which is a monoclock shift register 205, 2 configured as a timing control circuit for sequentially performing a sampling operation on the plurality of analog switch groups.
06, 207, and 208.

These components are similarly configured in the signal line drive blocks except for the arrangement of the first and second transmission lines. When each signal line group is composed of six adjacent signal lines to avoid complication, the number of analog switch groups is three. First and second transmission lines 2
09 and 210, 211 and 212, 213 and 214, 215 and 216 each independently constitute a video signal bus connected to the display panel controller 702. These video signal buses have video signal input terminals on both ends of the shift registers 205, 206, 207, and 208 on the display panel substrate 701.
206, 207, 208 and analog switches 220-2
25, 226 to 231, 232 to 237, 238 to 24
3 is formed so as to intersect with the connection wiring connecting to the wiring 3.
The first and second transmission lines have the same wiring length and parasitic capacitance, that is, wiring load, between the signal line blocks.
The first transmission lines 209, 211, 213, and 215 are odd-numbered analog switches 220, 222, 224;
228, 230; 232, 234, 236; 238, 2
The second transmission lines 210, 212, 214, and 216 are connected to odd-numbered signal lines 707 through 40, 242, and the even-numbered analog switches 221, 223, 225;
7, 229, 231; 233, 235, 237; 23
9, 241 and 243 are connected to the even-numbered signal lines 707. These transmission lines 209 to 216 are formed in the same step as the step of forming the source / drain electrodes of the thin film transistor which is the switching element 709. The shift registers 205, 206, 207, and 208 are composed of flip-flops of the same number as the number of analog switch groups connected in series, and the start pulse ST input to the first flip-flop is supplied to the last flip-flop in response to the clock CK. By shifting the input start pulse ST in the forward direction to the last flip-flop in response to the clock CK, the output terminals SR101, SR102, S
R103; SR201, SR202, SR203; SR
301, SR302, SR303; SR401, SR4
02, and an enable signal is generated sequentially from SR403.
Each flip-flop is a known CMOS clocked inverter circuit, and is formed by combining thin film transistors formed in the same process as the thin film transistor of the switching element 709.

FIG. 7 shows the operation of the signal line drive circuit XD.
The shift registers 205, 206, 207, and 208 are shown in FIG.
As shown in FIG.
1, SR102, SR103; SR201, SR20
2, SR203; SR301, SR302, SR30
3: An operation of sequentially generating an enable signal from SR401, SR402, and SR403 is performed in parallel. That is,
The enable signal is output from the output terminal SR1 in the first clock cycle.
01, SR201, SR301, and SR401, and outputs SR102, S
Output from R202, SR302 and SR402,
In the third clock cycle, the output terminals SR103, SR20
3, output from SR 303 and SR 403, and output in the same format as described above if there is a subsequent clock cycle. As a result, the odd column video signals SV31, SV33,
SV35, SV37 and even column video signals SV32, SV
Both V34, SV36, and SV38 are sequentially sampled by the analog switch group that has received the enable signal in the first to third clock cycles, and are supplied to the corresponding signal lines 707.

In the third embodiment, the width of the area 260 occupied by the video signal bus shown in FIG. 6 can be reduced. Further, it is possible to reduce the number of overlapping portions 261 and 262 where the video signal bus intersects with the wiring connecting the shift register and the analog switch. Therefore, the circuit width of the signal line driving circuit XD can be reduced, and the transmission band of the video signal line can be improved by reducing the load capacity. Further, each of the odd column and even column video signals is supplied from the display panel controller 702 to two video signal input terminals of the opposing signal line drive block. With this configuration, the transmission band of the video signal line can be further improved.

(Embodiment 4) Next, a liquid crystal display according to a fourth embodiment of the present invention will be described with reference to FIGS. This liquid crystal display device has the same configuration as that of the first embodiment except for the matters described below. FIG. 8 shows the configuration of the signal line drive circuit XD of the liquid crystal display device, and FIG. 9 shows the operation of the signal line drive circuit XD.

The signal line drive blocks 11 to 14 are configured as shown in FIG. Signal line drive blocks 11, 12,
Reference numerals 13 and 14 denote odd column video signals SV41, SV43, and SV.
45, first transmission lines 409, 411 for transmitting SV47,
413, 415 and even-numbered column video signals SV42, SV4
4, a second transmission line 410 for transmitting SV46 and SV48,
412, 414, 416 and six adjacent signal lines 707, respectively, and the first transmission lines 409, 41
1, 413, 415 and the second transmission lines 410, 412,
A group of analog switches 420 to 425, 426 to 43 which are alternately assigned to 414 and 416, sample video signals on the corresponding transmission lines, and supply to the corresponding signal lines 707.
1, 432 to 437, 438 to 443 and a plurality of analog switch groups each including two adjacent analog switches equal to the number of transmission lines.
~ 425, 426-431, 432-437, 438 ~
443, 407, 408, and 408, each of which is a timing control circuit for sequentially sampling the analog switch groups. These components are similarly configured in the signal line drive blocks except for the arrangement of the first and second transmission lines.

If each signal line group is composed of six adjacent signal lines to avoid complication, the number of analog switch groups is three. First and second transmission lines 409
And 410, 411 and 412, 413 and 41
Reference numerals 4, 415, and 416 each independently constitute a video signal bus connected to the display panel controller 702. The transmission lines 409 to 412 have a video signal input terminal on one end side of a serial unit of the shift registers 405 and 406 on the display panel substrate 701. Transmission lines 409 and 41
0 indicates the shift register 405 and the analog switches 420 to
425 and the transmission lines 411 and 412
And 406 and analog switches 420-425 and 426-431. The transmission lines 413 to 416 are connected to the display panel substrate 7.
01 has a video signal input terminal on the other end side of the serial unit of the shift registers 407 and 408. Transmission line 413
And 414 are formed so as to extend to intersect with connection wirings connecting the shift registers 407 to 408 and the analog switches 432 to 437 and 438 to 443, and
5 and 416 are formed so as to extend crossing the connection wiring connecting the shift register 406 and the analog switches 438 to 443.

First and second signal line drive blocks 11
The transmission line has the same wiring length and parasitic capacitance as the first and second transmission lines of the signal line drive block 14, that is, the wiring load. In addition, the first and second signal line drive blocks 12
The transmission line has the same wiring length and parasitic capacitance as the first and second transmission lines of the signal line drive block 13, that is, the wiring load. The first transmission lines 409, 411, 413, and 415 are odd-numbered analog switches 420, 422, 424;
26, 428, 430; 432, 434, 436; 43
8, 440, and 442 to the odd-numbered signal lines 707, and the second transmission lines 410, 412, 414, and 416.
Are the even-numbered analog switches 421, 423, 42
5; 427, 429, 431; 433, 435, 43
7; connected to an even-numbered signal line 707 via 439, 441, and 443. The transmission lines 409 to 416 are formed in the same step as the step of forming the source / drain electrodes of the thin film transistor which is the switching element 709. The shift registers 405, 406, 407, and 408 are composed of flip-flops equal in number to the number of analog switch groups connected in series. The output ends SR501, SR502, SR503; SR6 by shifting in the forward direction.
01, SR602, SR603; SR701, SR70
2, SR703; SR801, SR802, SR803
To generate an enable signal sequentially.

FIG. 9 shows the operation of the signal line drive circuit XD.
The shift registers 405, 406, 407, and 408 are shown in FIG.
As shown in FIG.
1, SR502, SR503; SR601, SR60
2, SR603; SR701, SR702, SR70
3: An operation of sequentially generating an enable signal from SR801, SR802, and SR803 is performed in parallel. That is,
The enable signal is output from the output terminal SR5 in the first clock cycle.
01, SR601, SR701, and SR801, and the output terminals SR502, SR502 in the second clock cycle.
Output from R602, SR702 and SR802,
In the third clock cycle, the output terminals SR503, SR60
3, output from SR 703 and SR 803, and output in the same format as described above if there is a subsequent clock cycle. As a result, the odd column video signals SV41, SV43,
SV45, SV47 and even column video signals SV42, S42
Both V44, SV46, and SV48 are sequentially sampled by the analog switch group that receives the enable signal in the first to third clock cycles, and are supplied to the corresponding signal lines 707.

In the fourth embodiment, the width of the area 460 occupied by the video signal bus shown in FIG. 8 can be reduced. Further, it is possible to reduce the number of overlapping portions 461 and 462 where the video signal bus intersects the wiring connecting the shift register and the analog switch. Therefore, the circuit width of the signal line driving circuit XD can be reduced, and the transmission band of the video signal line can be improved by reducing the load capacity.

In each of the embodiments described above, the case where the signal line drive circuit XD is composed of four signal line drive blocks has been described as an example, but the present invention is not limited to this. In each of the embodiments described above, the number of video signal transmission lines for each signal line drive block may be reduced to one. In this case, the enable signal is supplied to the even-numbered analog switches at a timing different from that of the odd-numbered analog switches by, for example, doubling the number of flip-flops of the shift register.

[0037]

According to the display device of the present invention, since the video signal bus is provided for each signal line drive block so as to be electrically insulated from each other, the intersection with the wiring in another drive block is provided. As a result, the load capacity can be reduced, and the band characteristics of the video signal bus can be significantly improved. Therefore, good display performance without image distortion or the like can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a circuit arrangement of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a detailed diagram of the signal line driving circuit shown in FIG.

FIG. 3 is a timing chart of driving waveforms of the signal line driving circuit of FIG. 2;

FIG. 4 is a detailed view of a signal line driving circuit of a liquid crystal display according to a second embodiment of the present invention.

5 is a timing chart of driving waveforms of the signal line driving circuit shown in FIG.

FIG. 6 is a detailed view of a signal line driving circuit of a liquid crystal display according to a third embodiment of the present invention.

FIG. 7 is a timing chart of driving waveforms of the signal line driving circuit of FIG.

FIG. 8 is a detailed diagram of a signal line driving circuit of a liquid crystal display according to a fourth embodiment of the present invention.

FIG. 9 is a timing chart of driving waveforms of the signal line driving circuit of FIG.

[Explanation of symbols]

 701 display panel substrate 702 display panel controller 11, 12, 13, 14 signal line drive circuit block 707 signal line 708 scanning line 709 switching element 710・ Display pixel

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[Procedure amendment]

[Submission date] March 27, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 4

FIG. 3

FIG. 5

FIG. 6

FIG. 7

FIG. 8

FIG. 9

Claims (7)

[Claims] 1. A display panel substrate, a plurality of display pixels arrayed in a matrix on the display panel substrate, and a plurality of signals formed on the display panel substrate along a column of the plurality of display pixels. A scanning unit formed on the display panel substrate in order to periodically select lines and rows of the plurality of display pixels, and to connect the display pixels of the selected row to the plurality of signal lines; and A driving unit for driving display pixels of a selected row via signal lines, wherein the driving unit is arranged to divide the plurality of signal lines into a plurality of signal line groups each including a predetermined number of adjacent signal lines. A plurality of signals that receive individual video signals supplied for the signal line groups from outside the display panel substrate, and perform an operation of driving the signal line groups in parallel based on the individual video signals. A display device including a driving block. Each signal line drive block samples a corresponding video signal and supplies the sampled video signal to the predetermined number of signal lines; and a sampling unit based on a common control signal supplied from outside the display panel substrate. The display device according to claim 1, further comprising a timing control circuit that controls operation timing of the unit. 3. The sampling unit according to claim 1, wherein the sampling unit is respectively assigned to a plurality of transmission lines for transmitting a plurality of partial video signals obtained by decomposing the video signal, and the plurality of transmission lines. A plurality of analog switches which are sequentially assigned to each other and sample the partial video signal on the corresponding transmission line and supply the same to the corresponding signal line, wherein the timing control unit controls the plurality of analog switches to a number equal to the number of the transmission lines. 3. The display device according to claim 2, wherein the display device is configured to be divided into a plurality of analog switch groups formed by adjacent analog switches, and to sequentially perform the sampling operation on the plurality of analog switch groups. 4. The timing control section has a plurality of output terminals arranged along the plurality of analog switch groups and commonly connected to analog switches of the corresponding analog switch group, and an enable signal sequentially from the plurality of output terminals. The display device according to claim 3, further comprising a shift register that outputs a signal. 5. A transmission line between the plurality of signal line driving blocks, each transmission line having a video signal input terminal on at least one end side of the shift register, and intersecting with a connection wiring connecting the shift register and the plurality of analog switches. The display device according to claim 4, wherein the display device is formed so as to extend by a common length. 6. In adjacent signal line drive blocks,
6. The display device according to claim 5, wherein a shift direction of the shift register is set to a direction common to each other when a video signal input end is arranged on the same end side of the shift register. 7. In adjacent signal line drive blocks,
6. The display device according to claim 5, wherein the shift directions of the shift register are set to be opposite to each other when the video signal input terminal is disposed on one end side and the other end side of the shift register, respectively.