JPH0230028B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a driving circuit for a matrix display device, and more particularly to a method for driving a circuit for writing and reading image information in a multiple matrix display device.

Figure 1 shows the principle of a liquid crystal display device.
When an AC voltage is applied to the transparent electrodes 2 and 2' formed on the upper and lower glass substrates 1 and 1', the liquid crystal layer 3, which is a display body thinly sealed between the two substrates, is excited and the light transmission state changes. It changes and is displayed. In a liquid crystal matrix display device, the transparent electrodes 2 and 2' are formed in a matrix, and display is performed by varying the effective voltage applied to the liquid crystal at the intersections. The relationship between the effective voltage and the amount of light transmitted is as shown in Figure 2, and is usually expressed as the difference between the voltages _VNS and _VS.

FIG. 3 shows a matrix display device that displays pixels in two rows and three columns.

With reference to FIG. 3, a specific circuit operation will be described in the case where pixels in the shaded area are displayed. Here, the horizontally elongated scanning electrodes are called row electrodes X ₁ , X ₂ , and the vertically elongated signal electrodes are called column electrodes Y ₁ , Y ₂ , Y ₃ .

4 is a memory drive circuit, 5 is a frame memory, 8
is a scanning circuit, and the column electrode drive circuit 100 is composed of a line memory 6 and a selection switch circuit 7.

With the image data D _I as input, the frame memory 5 is provided with a picture display panel 9 by the memory drive circuit 4.
Image data D ₁ during one frame period corresponding to images (1, 1), (1, 2), ... (2, 2), (2, 3) formed at the intersection of the row electrode and column electrode of ,D ₂ ,
...D ₆ is memorized. At the first line of scanning,
Image data D ₁ , D ₂ , D ₃ are input to the line memory 6, and the fourth image data obtained by the selection switch circuit 7 is input to the line memory 6.
Apply a voltage V _Y with a waveform as shown in Figure b. The signal generated by the scanning circuit 8 is a waveform signal _VX that sequentially selects the row electrodes X ₁ and X ₂ at a frame period T as shown in FIG. 4A based on the image data D _I. Therefore, as shown in FIG. 4, the applied voltage seen from the liquid crystal side has a waveform of c in the shaded area of the pixel (1, 1), a waveform of d in the white area of the pixel (2, 1), and the waveform of the voltage applied in the shaded area is d. Voltage V _S > white part voltage V _NS , and a predetermined display is obtained. As is clear from FIG. 4, the effective voltage value of the voltage applied to the liquid crystal at this time is expressed as a function of the frame period T of the row electrodes.

Incidentally, as a means for improving the resolution, brightness, and contrast of a matrix display device, a multiplex matrix method as disclosed in, for example, Japanese Patent Application Laid-open No. 115198/1983 has been proposed. In this method, a plurality of signal electrodes are formed within one row of scanning electrodes, and these image data signals are applied simultaneously when selecting a scanning electrode for display.

FIG. 5 shows a dual matrix display device that displays pixels in 4 rows and 3 columns as an example of a conventional multiple matrix system.

Similar to FIG. 3, the frame memory 5 stores image data _D1 ... _D12 during one frame period corresponding to pixels (1,1)...(4,3). first,
Image data D ₁ , D ₂ ,...D ₆ are input to the line memory 6, and as in FIG. 3, the selection switch circuits 7,
Drive signals are input to the column electrodes _Y1 to _Y6 by the scanning circuit 8, and a predetermined display is obtained on the display panel 9. As shown in FIG. The display columns are formed with column electrodes divided into two groups.

In this case, the number of output terminals of the column electrode drive circuit 100 consisting of the line memory 6 and the selection switch circuit 7 increases, but the number of pixels is doubled at the same effective voltage as in the simple matrix method shown in FIG. Therefore, image quality can be improved.

Incidentally, the image data signal D input to the line memory 6 is often read out from one frame memory 5 storing image data D ₁ , D _{2 .} . . and converted into a serial data signal D. In the case of the simple matrix method shown in FIG. 3, the contents of the frame memory 5 may be sequentially read and written directly to the line memory 6.

However, in the case of the multiplex matrix method, the order of the image data in the frame memory must be alternately changed and read out, which complicates the peripheral circuitry such as the address counter. For example, in the case of FIG. 5, the image data in the frame memory 5 is D ₁ ,
Assuming D ₂ ,...D ₆ , the reading order is D ₁ ,...D 6
It is necessary to set D ₄ , D ₂ , D ₅ , D ₃ , and D ₆ .

An example of the memory drive circuit 4 shown in FIG.
As shown in the figure.

This circuit consists of a counter 41, an adder 42A, an adder 42B, a multiplexer 43, etc., which perform the operations shown in the time chart of FIG. In this way, complicating the reading order of the frame memory 5 complicates the peripheral drive circuit of the frame memory 5.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a matrix display device with a simple circuit configuration.

A feature of the matrix display device of the present invention that achieves the above object is that the column electrodes facing one row of matrix-shaped pixels of the display panel are electrically divided into a plurality of groups with a certain regularity for each row. The frame memory is divided into the same number of blocks as the number of divided column electrode groups.

Specifically, the matrix display device of the present invention is characterized in that the column electrodes facing one row of matrix-shaped pixels of the display panel are electrically divided into a plurality of groups with a certain regularity for each row. The frame memory is divided into the same number of blocks as the number of divided column electrode groups, and at least one of the frame memories divided into the plurality of blocks is sequentially designated, and the frame memory is The point is that the frame memory is driven by specifying an address.

The certain regularity for electrically dividing the column electrodes into a plurality of groups means, for example, dividing the column electrodes into four times the number of row electrodes, and dividing the column electrodes into four groups facing each row electrode.
When forming row pixels and dividing them into four groups a, b, c, d, the column electrodes are grouped sequentially from the first row to a, b, c, d, a,
b, c, d, ... multiplexing method, a, b, c,
This means that the arrangement order is regularly repeated, such as in the inverse multiplexing method, where d, d, c, b, a, a, b, c, d, . . . .

FIG. 8 shows a first embodiment of the present invention. In this figure, the same symbols as in FIG. 5 indicate the same parts, but the selection switch circuit 7, scanning circuit 8, and display panel 9 are the same as in FIG. 5, so their description will be omitted. In Figure 8, the fifth
Assume that pixels in four rows and three columns are displayed as shown in the figure.

In FIG. 8, 10 is an address selector, 1
Reference numeral 1 denotes an address counter at the time of reading, which together with switches SW ₁ , SW ₂ , and a NOT circuit constitute a memory drive circuit 4 that drives frame memories 51 and 52 .

As shown in FIG. 5, in the display panel 9, the column electrodes Y ₁ and Y ₂ , Y ₃ and Y ₄ , Y ₅ and Y ₆ , etc.
One display column is constituted by column electrodes divided into two groups. Correspondingly, the frame memory also has column electrodes Y ₁ , Y ₃ , Y ₅ and column electrodes Y ₂ , Y ₄ ,
Divide into two, each corresponding to Y ₆ . That is, the image data D ₁ , D ₂ ,
D ₃ , D ₇ , D ₈ , D ₉ are stored in the frame memory 51;
Image data of the fourth line D ₄ , D ₅ , D ₆ , D ₁₀ ,
D ₁₁ and D ₁₂ are stored in the frame memory 52.
Thereafter, the image data in the frame memories 51 and 52 are transferred to the line memory 6 by being switched by a switch.

9 and 10 are time charts for explaining the operation of the circuit shown in FIG. 8.

WE is a write/read control signal for the frame memory, and when it is logic "H", it is written, and when it is "L", it is read. CS is a chip select signal, and it is logic "H".
Chip selection is performed at , and the strobe pulse is
A write operation is performed at the rising edge of STB.

During writing, SW ₁ is switched to the STB side, and the address selector 10 uses its control signal CP ₁ to
Select write address WA and set WA as address output A. This write address signal WA is outputted from a computer or the like in the order shown in FIG. 9, for example, and specifies an address in the frame memory at the same cycle as the image data signal _DI . The chip select signal CS is a signal that determines the select block of the frame memory, and is generated at the timing shown in FIG. 9 during writing. Therefore the strobe pulse
With the rising edge of STB, the frame memory 51 stores the image data D ₁ and 3 of the first and third rows of pixels.
D ₂ , D ₃ and D ₇ , D ₈ , D ₉ are stored, and the frame memory 52 contains the image data of the second and fourth rows.
D ₄ , D ₅ , D ₆ and D ₁₀ , D ₁₁ , D ₁₂ are stored. Here, the strobe pulse STB is generated after the information of the write address signal has risen to the extent that it can be determined sufficiently.

Next, when reading, write/write in FIG.
The read control signal WE is set to "L", and the address selector 10 selects the read address signal RA, which is the output of the read counter 11, using the control signal _CP1 , and makes RA the address output A. This read address signal RA is output in the order shown in FIG. 10, for example, and is generated at twice the cycle of the image data signal D _I , and is
52 address.

The specific circuit configuration of the read counter 11 is shown in FIG. This circuit is composed of a commonly used 1-chip 4-bit hexadecimal counter circuit 111 and a gate circuit 112, and can perform the circuit operation as shown in FIG. 12.

The chip select signal CS is generated as shown in Figure 10, and is generated at one-third of the writing cycle.
Together with the NOT circuit, it constitutes a chip select circuit.
Either frame memory 51 or 52 is selected. During the period of the read address signal RA, the switch SW ₂ is switched by the clock pulse CP ₂ , and the image data in the frame memories 51 and 52 are alternately transferred to the line memory 6 by the image data signal D.
will be forwarded to. Therefore, in the line memory 6,
The order of D ₁ , D ₄ , D ₂ , D ₅ , D ₃ , and D ₆ is the same as in the conventional example shown in FIG.

Thereafter, the operations from converting to parallel data by the line memory 6 to applying voltage to the column electrodes are the same as in the conventional example, and will therefore be omitted.

In addition, in FIG. 8, the frame memory 51,
Switching of the output signal of 52 was performed by switch SW ₂ , but if frame memories 51' and 52' of tri-state output are used as shown in FIG. 13, switch SW ₂ can be omitted.

According to this embodiment, by dividing the frame memory into two, image data can be read out with a simpler circuit as shown in FIG. 11, compared to the conventional method shown in FIG. 7.

FIG. 14 shows a second embodiment of the present invention. In this figure, the same symbols as those in the above-mentioned figures indicate the same or equivalent parts.

In FIG. 14, column electrode terminals are drawn out on both sides of the display panel 9, and frame memories 51 and 52 and column electrode drive circuits 100a and 1 are connected to each other.
It is connected to line memories 61 and 62 and selection switch circuits 71 and 72 that constitute 00b.

Similarly to FIG. 8, frame memories 51 and 52
are D ₁ , D ₂ , D ₃ , D ₇ , D ₈ , D ₉ and
D ₄ , D ₅ , D ₆ , D ₁₀ , D ₁₁ , and D ₁₂ are stored.
In the first line of scanning, the frame memory 51,
Image data corresponding to the first line of scanning in 52,
D ₁ to _{D 3} and D ₄ to D ₆ are simultaneously read out and written into the respective line memories 61 and 62 to perform a predetermined display.

In this embodiment as well, by dividing the frame memory into two, the switch SW ₂ is not required and the image data can be read out with a simple circuit.

Furthermore, in this embodiment, since the column electrode terminals are drawn out on both sides of the display panel 9, it is possible to avoid increasing the density of the column electrode terminals.

FIG. 15 shows a third embodiment in which the present invention is applied to an inverted quadruple matrix method.

51, 52, 53, 54 are frame memories, 61, 62 are line memories, and 7
1 and 72 are selection switch circuits.

The decoder 12 includes frame memories 51, 52,
Control signal for selecting chips 53 and 54
This is a chip select circuit that outputs CS ₁ ...CS ₄ .

Note that the same symbols as in FIGS. 8 and 14 indicate the same or equivalent items. In FIG. 15, the screen has, for example, 8 rows and 3 columns of pixels (1,1), (1,2),...
It is formed by (8,2) and (8,3). here,
The display column unit is four groups of column electrodes Y _Aj ,
It is formed by Y _Bj , Y _Cj , and Y _Dj (j=1, 2, 3). The A column electrode Y _Aj is connected to the pixels in the first and eighth rows, and the B column electrode Y _Bj is connected to the pixels in the second and seventh rows. Similarly, the C column electrode Y _Cj and the D column electrode Y _Dj are in the third and sixth rows, respectively.
and connected to the fourth and fifth rows. Since the display column unit is divided into four groups, the frame memory is also divided into four groups 51, 52, 53, and 54, and as shown in the figure, image data D ₁ to _{D 24} are connected to each column electrode. It is stored in the frame memory as image data of the pixels in the frame memory.

First, in the first line of scanning, the first line of image data D ₁ , D ₂ ,
D ₃ and the image data D ₄ , D ₅ , D ₆ of the second row of pixels in the frame memory 52 are transferred to the line memory 61 by switching the switch SW ₂₁ so that the image data in the frame memory 51 comes first. D ₁ , D ₄ ,
Image data is transferred in the order of D ₂ , D ₅ , D ₃ , and D ₆ . At the same time, the image data D ₇ to D ₁₂ of the third and fourth rows of pixels in the frame memories 53 and 54 are transferred to the line memory by switching the switch SW ₂₂ so that the image data in the frame memory 53 comes first. Image data is transferred to 62 in the order of D ₇ , D ₁₀ , D ₈ , D ₁₁ , D ₉ , and D ₁₂ .

Next, in the second line of scanning, the image data D ₁₉ to D ₂₄ of the seventh and eighth lines of pixels in the frame memories 51 and 52 are first scanned by the image data in the frame memory 52. The image data is transferred to the line memory 61 in the order of D ₁₉ , D ₂₂ , D ₂₀ , D ₂₃ , D ₂₁ , D ₂₄ , and at the same _time , the The SW ₂₂ is switched so that the image data D ₁₃ to _{D 18} of the 6th and 6th rows are stored in the frame memory 54 first, and the image data D ₁₃ , D ₁₆ , D ₁₄ , D ₁₇ , D are stored in the line memory 62. Image data is transferred in the order of ₁₅ and _D18 , and a predetermined display is performed.

In this embodiment as well, since the frame memory is divided into four parts, image data can be read out with a simple circuit.

The above-mentioned embodiments are applied to double matrix, inverted double matrix, and inverted quadruple matrix systems, but the present invention is applicable to the general n-fold and inverted n-fold matrix systems, as well as to split row electrodes. It can also be applied to a so-called multi-stage matrix method.

Further, the present invention is applicable not only to liquid crystal displays but also to other display bodies such as electroluminescence displays and plasma displays.

As described above, according to the present invention, the frame memory is divided into the same number of blocks as the number of column electrode groups divided into a plurality of blocks, so the read operation of the frame memory is simplified, and the circuit configuration is simplified. A matrix display device can be obtained.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of a liquid crystal display device, Fig. 2 is a diagram showing the relationship between the applied voltage of the liquid crystal element and the amount of light transmission,
FIG. 3 is a configuration diagram of a conventional simple matrix display device, FIG. 4 is a diagram showing an example of driving waveforms of a liquid crystal matrix display device, and FIG. 5 is a configuration diagram of a conventional dual matrix display device. 6 is a block diagram of an example of the memory drive circuit shown in FIG. 5, FIG. 7 is a time chart of the drive operation of the memory drive circuit shown in FIG. 7, and FIG. 8 is a diagram showing the first embodiment of the present invention. There are 2
9 is a block diagram of a heavy matrix display device, FIG. 9 is an operation time chart when writing image data of the first embodiment of the present invention shown in FIG. 8, and FIG. 10 is a diagram of the operation time chart of the first embodiment of the present invention shown in FIG. 11 is a configuration diagram of an example of the read counter shown in FIG. 8; FIG. 12 is a time chart of the circuit operation of the read counter shown in FIG. 11; FIG. 13 is a time chart of the read counter shown in FIG. FIG. 14 is a block diagram showing an application of the first embodiment of the invention, FIG. 14 is a block diagram of a dual matrix display device which is a second embodiment of the invention, and FIG. 15 is a block diagram showing a third embodiment of the invention. FIG. 1 is a configuration diagram of a certain inverted quadruple matrix display device. 4...Memory drive circuit, 5, 51, 52, 5
3, 54... Frame memory, 6, 61, 62...
... Line memory, 7, 71, 72 ... Selection switch circuit, 8 ... Scanning circuit, 9 ... Display panel, 1
0... Address selector, 11... Read counter, 12... Decoder, 100, 100a, 10
0b...Column electrode drive circuit.

Claims (1)

[Scope of Claims] 1. A pixel consisting of a row electrode and a column electrode formed on one substrate and the other substrate, respectively, and a material having an electro-optic effect sandwiched between the row electrode and the column electrode. form a matrix,
In the device that performs display by applying a voltage to the row electrode and the column electrode, the pixels in the matrix are divided into pixel groups, and the number of the pixel groups is I, and the pixels included in one pixel group are divided into pixel groups. The pixels included in each pixel group are scanned at the same timing, and the pixels included in each pixel group are arranged in a matrix of n rows x J columns, and each one of the row electrodes is scanned at the same timing as the pixels included in each pixel group. Each of the column electrodes is provided in n×J pieces so as to cover one pixel of n rows×J columns included in one pixel group, and each of the column electrodes is provided in n×J pieces so as to cover one pixel of A matrix display panel configured such that K×J column electrodes out of ×J column electrodes are drawn out to the same side of the other substrate; and a row supplying a row electrode drive signal to the row electrodes. an electrode drive circuit; n frame memories each storing image data for one row of pixels on each row electrode among one screen of image data; A memory for writing image data into a memory, inputting a read address, and switching and reading image data signals from the n frame memories in accordance with the arrangement order of the terminals of the column electrodes drawn out to the same side. A matrix display comprising: a drive circuit; and a column electrode drive circuit that generates a column electrode drive signal to be supplied to the column electrodes based on image data signals corresponding to the n rows of read pixels. Device.