CA2075441A1

CA2075441A1 - Am tft lcd universal controller

Info

Publication number: CA2075441A1
Application number: CA 2075441
Authority: CA
Inventors: David D. Lee; Alan G. Lewis; Richard Bruce
Original assignee: Xerox Corp
Current assignee: Xerox Corp
Priority date: 1991-12-10
Filing date: 1992-08-06
Publication date: 1993-06-11
Also published as: JPH05303357A; EP0546780B1; EP0546780A1; DE69220762D1; DE69220762T2

Abstract

ABSTRACT OF THE DISCLOSURE
A universal, stand-alone controller integrated circuit (IC) for high resolution, active matrix liquid crystal displays (AMLCD's) incorporating the following features: (1) serial to parallel conversion of the refresh data stream to support verti-cally split panels as well as multiple scan drives, (2) data re-ordering to support various color pixel/filter arrangements in-cluding delta-triad RGB and quad RGGB color filter mosaics, (3) two-dimensional anti-aliasing image processing, (4) color/gray-scale correction/compensation due to change in operating tempera-ture, and (5) host interface with programmable control registers to hold various display configurations and control parameters.
With these features, the stand-alone AMLCD controller simplifies the graphics/display adapter design by providing a simple single-panel single-drive interface, similar to that of the CRT's but in digital format, to various types of the AMLCD's. It also reduces the functional and performance requirements of the AMLCD panel driver IC's by integrating pixel data rearrangement otherwise im-plemented in the driver IC's, hence allowing more line drivers to be integrated within a smaller driver chip. The controller of the invention establishes a universal, standard interface between the host system and AMLCD's of various panel technologies, resolutions, and different timing requirements.

Description

3 ~

~I T~ 27Iv~R~ 'ON~O~LE:E~
This invention relates to controller~ for enabliny or energizing ~lat panel, active matrix, liquld crystal displays.
BACR~RO~ND OF INV~N~O~
Flat panel, activ2 matrix (AM), liquid crystal display~
(LCD) using th~n film transi~tors ~TFT) in serie~ with each pixal alement have become popular a~ TV di~play~ or computer monitor~.
Color versions are also common, achieved by 8plitting each pixel into sub-pixel elements, each with its own color ~ilter. Annexed Fi~. 1 shows the main elements of a color display system with an active matrix liquid crystal display (AMLCD~ panel as a single module 10. The panel 10 comprises a known matrix array 11 o~
liquid crystal display elements 12 with correspondingly posl-tioned red, green and ~lue color ~ilters (not shown). The array will contain many more elements than that shown, as will be clearer below. A display elem nt, a pixel 13, consists of a thin-fil~ transistor 14 ~FT) havlng a gate 15 and a capacitor 1 representing the LCD element. One ele~trod~ 16 of th~ TM is designated its data line electrode 16. The intensity of ¢olored light transmitted by each element i5 determined by a drive volt-age applied to the pixel~s ~ata electrode 16 when the scan elec-trods 21 is pulsed high. See, ~or exampla, publications tl, 5]
as well as U.S. Patent No. 4,716,403 for a description of a typi-cal AMLCDs. The bracketed numbers are publications whose cita ~5 tions will be found in the annexed Appendix.

XRX.116.001.6 (D~91471) l-- 2~7~4~
. ~ , Two peripheral circuit~ drivinq th~ panel dire¢'cly are a row driver 20 selectlng a hor~zontal l:lne 21 and a column driver 22 driving vertical data lines 23. A~; one horizontal lin~ (row) 21 is selected, all TFT's 14 connected tv the line are turned on and data driven by column drivers 22 is loaded in~o the pix~l electrodes in parallel via condluc:tors 23.
Most AMLCD modules 10 also include a separate LCD con-troller IC 25 which provides an inter~ace to ths row ancl column driver IC's 20, 22 from the dis,play source driver, the host sys-tem's display adapter/controller 26~ a separate module. The dis-play adapter 26 usually consists o~ a RAM display data source (frame bu~fer) 27, and a programmable controller IC 28 to drive various displays with different configuration parameter~. It may also includes a RAMDAC IC 29 (color loo~-up table with digital to analog conv~rsion) to map a given color space into individu~l color components (RGB3 which are then used to drive displays tak-ing ~hese as inputs. ~ost CRT monitors take the analog input as a standard data ~ormat, b~t most color ~FT AMLCD's take the digi-tal ~GB forma~.
20 . The problem addressed is driving a high resolutio~ AMLCD
panel, which involve~ the la~k of standardizatlon in the pixel layout of the panell the interface signals and timing requ~re-ments for the panel, the panel resolution, the number of display-able colors, and refresh frequencies or re~resh scheme. This will be clearer from the following discussion. As can be seen in Fig. 1, the column driver IC 22 receives a video data stream from XRX.116.001.6 (D~91471) -2-2(~7~

the display adapter 26 vi~ the LCD controller IC 25. Many column driver IC'8 for AM~CD panel~, espe~ially for color TV'~
with panel size l~ than 3-6 lnches diagon~lly, take analog in puts. As the display re501ution lncrease~, the pixel sc~n rate increases proportlonally. Thi~, in kurn increases the input data sampling rate o the column driver as shown in Tabl~ 1 below:

~ABLB 1 COLOR ~CD ~ith 60 ~ re~ h r~te (~n~loq-R~B2 ~IX~ ~I~$
DI~PhAY R~OI.UTION ~IN~ PIx~L~L
VGA LCD 3X640 x 480 34.72 ~s 54.3 ns (912,600 pixel~) (17 n~3 Super VGA/ 3x1024 X 760 21.93 ~s 21.4 ns XGA LCD(2,334,720 pixels) (7 n~) Super-XGA 3x1280 X 1024 16.28 ~s 12.7 ns LCD (3,932~160 pixels~ 54 ns) As will be noted, with higher resolution panels, the output loads at the data terminal a~so increases, and hence the output driver circuit must be made larger to have a hi~her driving capability, Therefore, it becomes almost impractical to use analog inputs ~or high resolution (be~vond the XGA3 panels: see ~he descrip~ion in publication [1]. Furthermore, it becomes very difficult to in-tegrate high-voltage (above 8-10V~ column drivers with high fre-quency sampling circuits at the input terminals on the same chlp (i.e. hard to scale down wi~h the shrinking technol~gy). The ~astest column driver IC's with a digital input currently avail-able of fer an input samplin~ frequency of about 20 MHz, whereas a 1024 by 768 panel would require an input rate o~ 50 MHz. Even XRX.116.001.6 (D~91471) -3-2 ~
with inte~rated TFT driver~ on the panel, the input sampliny rate will remain und~r 20 MHz ~3~, A similar mi5match exl~ts in high-resolu~ion, pas~ive Super-Twisted Nematlc ~STN) LCD panel3 and a common techniqu~ t~
s resolve the mismatch is to split the panel into top and botto~
halves. Data li~es are separated ~n the mid-panel and dri~n from both sides with different column drlver~. It e~ectivaly doubles the input bandwidth without requiring high speed driver IC's at the cost of preparing a dual-æcan data stream, ~ut has a seriou5 drawback as the panel resolution increases. Splitting the data (column) line in the middle of the panel makes data lines accessible only from one side. This leads to reducing tsstability and possible repairing of the panel prior to the en-capsulation of the liquid crystal material, especially for defects caused by breaks in split lines. If ~oth ends o~ the lines are accessible, the same defect may be tolerated by short-ing the broken line outside the panel or providing drivers on both ends. To meet the input sampling requirements and to be more de~ect-tolerant, it would be more appropriate to split the panel vertically into left and right halves~ rather than split-ting it in top and bottom hal~es. Splitting the panel vert~cally does not require changing the panel layoutO Only the drivers are loaded fro~ the display adapter~controller, as if the panel were s~lit in multiple planes.
Typically, the data stream into the display device is serial as prepar~d or the most common CRT display's pixel-by-XRX.116.001.6 (D~914~ 4 - 2 ~

pixel, slngle-~can drive int~rface. Low-cos~ DRAM's or multl-ported VRAMS~s are the ~o~mon ~tora~e Por the refresh data, and high speed acces~ (static-column or page-mode in DRAM and ~eri~l-port in VRAM~ to these device~ usually prov~des a single, long serial data stream. It is not tr~vial to convert that long serial data stream to a parallel format suitabl~ ~or vertically spilt panels. For example, th~ vid~o ~æerial) port of the VRAM
shifts out data serially from 512 or mor~ serial shi~t regi6ter~
loaded in parallel, so ~he dat~l in the middle o~ the stream can-not be accessed until all prev:ious data are shifted out. I~ the horizontal resolution of khe ~er~ically split panel is shorter than the depth of the shift registers, a special technique or a separate buffer is required to convert this serial data skream into the format needed by the vertically split panel~ A software driver manipulating the frame buffer may re-arrange the da~a ac~
cordingly, but then it would become an undesirable, device-dependent driver.
The current AMLCD technology o~ers the potential for ex-cellent image quality, which may ultimately exceed that ob-tainable with high-resolution C~Tss. The so~rce of the better imaging potential results from several a~tri~ute~. A ~ew among many are~ lexibility in de~ining the color-filter mosaics, including the size, ~hape, and luminance-profile o~ individual elements, (23 addressability (meaning how the elemen~s are selected to create a line) and control of individual elements;

(3) decoupling of the image-forming function from image~

XRX~ 116~ 001 n 6 (D/914713 -5-20~5~

generating function, and other~ [4]. While it providas ~lg-ni~icant opportunitieg for a high guali.ty dlsplays, it present significant problems in producing low-cost, high per~ormance ~MLCDIs. Several display parameters must be carefully chosen considering the panel technologies, the dr~ver ICis, the ~ource drivers, manufacturing cost andl appl~ca~ions. This has been in~
vestigated by other5 using computer simulation methods or actual~
ly building the AMLCD~s wit~ various parameter~ ~4, 5~ 6, 7~.
Among many different display parameters, the resolution, the nu~-ber of gray levels on each addressable pixel and color Pilker mosaics, have been predominant factors in determining the image quality.
The panel resolution and the number of gray levels of each pixel element strongly depends on the panel technology and driver IC7s. The choice of color mosaic usually depends on ap-plications and also makes a great impact on image qua~ity.
Again, many researchers have done extensive studies to f;nd an ideal color mosaic for a given panel resolution and the nu~ber of gray levels ~4, 5, 6, 7~. Figs. 2(a)-(~3 ~how various types o~
RGB color mosaics, where R, G, and B represent red, green and blue filter elements, respectiv~lyO The larger block~ represent pix~ls made up o~ the R, G, and ~ s~bpixels. ~hile the ma~ority of existing AMLCD's use~ stripe RGB mosaics (both horizontal and vertic~l) arranged in ~any different way~, researchers have found that the delta triad and guad-green mosaics would produce supe-rior image quality [4]. Some column driver IC's pro~ide a spe-XRX.116.001.6 (D~91471) ~6-2~7~

cial function to re~arrangQ the data fo:L~at inputted accordlng to the color mo~aic of the panel, but thQ types of mosalc~ ara limited (usually stripe RGB or varlants) due to complexity o~
data re arrangement required for some special mosalc~, such a~
delta-triad or quad gre~n. The data pattern of these two color mosaic~ is harder to generate than others since a color pixel spans over two scan lines. A buffer holding a line o~ display image must hold the data over two scan line times and scramble the RGB to generate the daka stream correctly for these two mosaics. A coJ.umn driver would require three input bu~fers per two output drivers ~or the quad-green mosaic, and one more level of bufPering would be necessary to hold the data over two scan lines. It would be inappropriate for the display adapter to do this pixel rearrangement since the color mosaic is also panel or application specific. No cu~rently-available controllers provide a solution to this problem.
Another big problem confronting color AMLCD image quality is the presence of spatial guantization or aliasing artifacts that manifest themselves as jagged edg~s or stair~steps [83.
number of software and hardwaxe algorithm5 resolving this proble~
have been implemented in different levels o~ the display system, mostly for CRTI~, and some of them are being considered for ap-plication to the AMLCD's ~93. The algorithms may vary among di~-~erent AMLCD configurations such as different types of color mosaics. The implementation of the algorithm may be done in the XRX.116.001.6 (D/91471) -~-2 ~

display controller/adapter or even at a hi~h~-r l~vel in the ~oft-ware drivers. ~ut thi~ i~ not a cost-effective ~olution.
Som~ environmental f~ctors, such a~ temperatur~ and light, can noticeably affect the lmage guality o~ the TFT AMLCD.
For example, an increas~ in temperature increases both the on an~
off current o~ th~ pixel ~FT~ While the increas~ in on-current i5 beneficial to faster display operation, th~ increase in o~
current reduce~ the pixel data storage time. Combined with the liquid crystal's temperature~delpendent characteri~tics, it may lo result that operating temperature changes the gray-level o~ the LCD, as depicted in the transmiss~on versus applied voltage curve for different temperatures shown in Fig. 3 ~10]. A correction requires a temperature sensor and digitizer, temperature detec-tion ~ogic, and special logic to properly adjust the gray-levelO
Since the temperature effect is closely tied to the TFT technol-ogy and LC material ~thus panel technology specific), the correc-tion must be done in the display module set for the correct thermal characteristics o the panel~ provided by the manufac-turer. This is a costly solution which remains panel technolo~y specific.
These are some examples o~ the different kinds of r~
quirements imposed on the controller whose ~unction ls to r~ceiYe the video signal and re-order the data for driving a particular AMTFTLCD.
Prior art solutions ;nclude integrating the controller within the display/graph;cs sub-system, such as a VGA board, with XRXo116~001~6 (D/91471) -8-2 ~ 7~

the result that the controller ~s only usable with that partlcu-lar display ~y5tem. Some stand-alone controllers are al30 avall-able, but they are rather simple, providing only synchronizing clock~ and buffering o~ a ~ew pixel data, and support only the ~implier mosaics. Color image enhancement ~eatures and the vari-ous color pixel arrangements are usually carried ou~ by special graphics adapter boards and separate matrix driver XCs with limitations. This approach is costly and requires extra hardware, and is not a good solution. See, ~or example, U.S.
Patent Nos~ 4,926,166: 4,275,421; and the Hitachi HD66300T
horizontal driver chip ~or TFT-type LCDs. The support they pro-vide is very limited, for example, CRT or LCD, or dif~erent s~zed displays, or several simple color ~iltar mosaics.
SUMMARY OF T~ INVEN~ION
Thus, there is a need in ~he art for a ~lexible, ver-satile stand-alone inter~ace controller to allow interfacing to the wides~ possible range of AMTFTLCDs from various systems.
An object of the invention is a universal AMLCD control-ler implementing features to solve the problems dis~ussed in th~
previous section.
Another object is a hardware architecture of an AMLCD
controller integrating the aforementloned features to interface to the widest range of high resolution ~MLCD's from various host systems.
A further object is a programmable ~MLCD controller that will take a single-panel single-drive data stream and re-arrange XRX.116.001.6 (D/914713 -9-~ ~ 7 ~

the data stream as programmed for dlf~erent type~ of panels, hence providing a very ~imple inter~ace to thQ display adapter.
Still another ob~ect is a ~epara~e controller with a flexibls bufer for re-arrangin~ the data to match the RGB color ` 5 mosaic of an AMLCD~ whereby it~ column driver and it8 inter~ace can be greatly simpli~ied.
Another ob~ect is an AMI~D-specl~ic controller with bu~
ers to hold ad~acent pixels' data and to provide data rearrange-ments ~or both vertically split panels and different ~ype~ o~
color mosaics.
An object of ~ha invention i5 an AMLCD controller with a special logic circuit to implement local, two dimensional image enhancing algorithms cost-effectively~
Still a further object is an AMLCD programmable control-ler which provides temperature c~rrection at a reasonable cost and possessing a flexible way of controlling the correction.
In accordance with one aspect of the invention, the con-troller comprises a multiplQ line buffer memory an~ logic neces-sary to support various color pixel~ilter arrangements of th~
panel.
In accordance with another aspect o~ the invention, the controller comprises data stream conversion means, specifically, serial to parallel, to support high resolution panels and data drive chips.
In accordance with a further aspect of the invention, means are provided which in conjunction with a multipl~ line XRX.116.001.6 (D/91471) -10-~ ~ 7 ~

buf~er memory can reorganlze or ra-order the data ~trea~ to satis~y the data format required ~or multiple split di~play screens, i.e., slmultaneou~ly to supply multiple ~tream~ oP data to refresh simultaneously multiple scr~en se~ment3.
In accordance with 8till another aspect o~ the lnvention, a universal, stand-alon~ controller integrated circuit (IC) ~or active matrix liquid cryst~l di~plays ~LCD' 8) ~ provid~d which incorporates one or ~ore, and preferably all, o~ the ~ollowing ~eatures: ~1) serial to parallel conversion of the refresh data stream to support vertically split panels as well as multiple scan drive~, (2) data re-orderin~ to support various color pixel/filter arrangements including delta-triad RGB and quad RGGB
color filter mosaics, (3) two-dimensional anti-aliasing image processing, (4) color/gray-scale correction/compensation due to a change in operating temperature, and ~5~ host interface with pro-grammable control registers to hold various display con~igura-tions and control parameters.
With these features, the stand-alone AMLCD controll~r simplifies the graphics/display adapter design by proYiding a simple single-panel single-driv~ inter~ace, si~ilar to that o~
the CRT's but in di~ital ~ormat, to various types of the AMLCD's.
It also reduces the functional and performance reguirement~ o~
the ~MLCD panel driver IC's by integrating pixel data rearrange-ment otherwise implemented in the driver IC'~, hence allowing more line drivers to be integrated within a smaller driver chip.
Thers~ore, the controller o~ the in~ention as a single chip es-XRX.11~.001.16 (~/91~71~

2~7~

tabli~hes a universal, ~tandard interface between the host ~y~tem and the ~MLCDI ~ of variou~ panel techno:Logie~, resolution~, and different timing requirements, and thu~ render~ the dis-play/graphics sub-sy5tem design independent of the display pan~l technology, and vice-versa. The controller chlp can reside in either location, namely, the dl~splay adapter board in the ho~t syste~, or on the di~play module in the display.
The present inv~ntion will be better understood Prom the detailed descriptio~ given herein below in con~unction with the lo accompanying drawings, which give by way of illustration only andnot by limitation, a ~rePerred embodiment in accordance with the present invention.
SUUMARY OF DRAWINGS
In the drawings:
Fig. 1 is a block diagram of a system incorporatin~ a controller in accordance with the invention, Figs. 2~a3-2(~) ~how variou~ color ~ilter arrangements employed in AMLCDs;
Fig. 3 ls a graph showing the transmission characteri~t-ics versus appli~d rms volta~e o~ a super fluorinat~d LCD element at differe~t temperatures;
Fig. 4 is a block diagra~ of the AMLCD Module;
Fig. S is a detailed block diagram of just the contr~ller o~ Fig. 4 alone;
Fig. 6 is a detailed block diagram of the multiple line buffer o~ the controller of Fig. ~;

XRX.116.001.6 (~J91~7~ -12-~7~
Figs. 7(a)-7~b) are, respective:Ly, a view o~ the two -dimensional array used for anti-aliasing, and a detail~d block diagram of the color pixel arrangement logic u~ed in the control-ler of F~g. 4;
Fig. 8 is a detalled bloc~ diagram o~ a p~xel arrangement and logic unit used in th~ controller o~ Fig. 4.
Dl~TAIIE:D DESCRIPTION OF PlREF~RRlEI~ ~S
The present invent~on p:rovldes a universal architecture for a stand-alone controllsr th,at provldes a standard inter~ace for active matrix, thin film transistor, liquid crystal display~
(AMTFTLCD). The novel architecture of~ers the advantages, among others, that it simplifies the design of display/graphlcs adap-ters and red~ces the functions required of AMLCD driver IC , permitting more such drivers to be integrated within a single chip.
Features of the controller include the following: (1) a high speed digital lnter~ace to t~e host, with multiple line buf-fering and internal register-programmable configurations; (2) color and gray-scale image enhancing, such as subpixel averaging over time and space ~anti-aliasing~; (3) support for a variety of color pixel arrangements: (4) generation of control signals and data re-ordering for the matrix driver ICs.
A system block diagram of the controller 25 o~ the inven-tion is illustrated in Fig. 2. A conventional display panel of the color TFT AMLCD type is schematically shown at 10~ This can be one of many well-known color pixel arrangements as shown in XRX.116.001.l6 (D/91471) ~13-2 ~

Fig. 2, ~uch as quad R~GB, trlad, and stripe RGB pixels, and has been described in detail in thQ publis~ed patent and ficientific literature and ~urther deta~ls are unnecessary to comprehend the present inventlon. The panel 10 is typically prov~ded with row drivers 20 for scanning and w~th column drivers 22 providing the video lnformation or data. The input to the column driver 22 i~
dig~tal R~B signalg, and thus the column driver~ 22 will in-corporate conventional buffer~ and D/A ¢onverSers.
The present invention has to do with the controller 25 which receives certain digital video, control, and sync signals from, for example, a host computer or TV receiver (not shown) and functions to organize the data and supply the data with the usual control and sync or clock signals to the panel drivers 20, 22.
In brieP~ the single chip controller 25 of the invention provides a local line buf~er 36 which is capable of being written to and storing several (m~ lines of pixel data to be annotated and displayed. A pixel arithmetic and logic block 37 computes the spatial pixel averages, re-order~ the data to be sent to the driver IC's. A color pixel configuration block 38 rearranges the pixel data according to the color filter implemented by the speci~ic color matrix LCD 10. An internal host interface block 39 includes programmable registers to store various display para-meters and configurations. A conventional phase-locked loop (PLL~ 40 and clock ~CLK~ generator block 41 provide synchroniza tion and control siqnals for the driver IC'~ ~he video MUX
block 42 multiplexes the second video signals to the line bu~fer ~RX. 1160 001. 6 (D/914713 -14;

to display alternate displ~y sources ln real ti~e. Except ~or the conventional c~rcuitry, such a~ tha PLL 40 and CL~ generator 41, the remaining blocks are describ~d in greater detall below.
~he vldeo MUX circuit 42 and the PLL 40 are not essentlal to in-corporate in the single controller chip of the invention, and i~
desired their ~unction~ can ba E~rovlded by separate chips.
As shown in Fig. 5, the multiple line buf~er (M~B) 36 receives high-speed, serial input data strPam ~rom a display sourca 44, line by line, and stores ~hem in the ~our (m-4~ buf~-ers 45-48 for a few line times, to be used by the pixel arith-metic and lo~ics unit (PL~) 370 The color pixel arrangement logic ~CPAL) 38 toge~her with conventional decoders ~not shown) of the MLB controls the data being fetched fro~ the MLB to match the color mosaic chosen of the AMLCD 10. The PLU 37 ~etches a set of pixel data in the format necessary for vertically split panels when us~d, and performs anti-aliasing image processing to enhance the image quality and/or temperature correction. The host inter~ace logic 39 înclude5 a set of programmabl~ control reqisters 49, 50 and the interface to the host system or oPf-chip ~OM to program or load registers with various con~iguration and control parameter The clock generator 41 gen~rates synchroniz-ing clocks and control signals for both row and column drivers 20, 22 as well as .internal clocks. The output port 51 buffers the data to b2 sent to the driver IC's and controls the data transfers to match the data trans~er fo~mat required by the driver IC's.

XRX.116.00106 (D/91471) -15-The MLB 36 include~ ~our llne buf~ers 45-48, each holding the data needed by column driver~ to drive one hor~zontal line.
~ach line buf~er (Fig. 6) conelst8 of bank~ o~ small~ indepen~
dently addressed RAM modules 52, each holding a segment o~ the line data. The access unit of each RAM module i~ the data width of the RGB color components. For example, a suitahl~ number o~
RAM module8 52 for each line bu~fer, that can accommodate the various RGB mosaicg of Fig. 2 and ths resolutions o~ ~able 1, i~

4. A typical line data segment is 3 X 320 plxel~, and a typical acce~s unit i~ 4 X 3 X 8 bits (8 bits per color component).
It will be understood that, in order to rearrange a serial input data stream into a parallel format, a bu~fer holding at least two horizontal lines must be present. ~ne buffer receive6 the input data stream while the other provide~ the out-put data stream. With a line buffer comprising a number of smaller RAM blocks 52, arranged as shown in Fig. 6, when receiv-ing the serial input data, only one module 52 per line buffer 45-48 is accesged at a time. When sending out the data to the N
column drivers 22, N modules are acce~sed simultaneously. The line buffers switch their roles as the scan line chan~e~ The MLB 36 implements this by usin~ po~nters 53 to keep track of the order of the line, instead of moving buffered data among the line buffers. Two extra line buffers are provided~-a total of Pour--to hold the data of two adjacent scan lines, to allow two dimensional anti-aliasing processing using an array (3X3~ o~
pixels, in a manner known as such in the art.

XRX.116.001~6 (D~91471) -16-.
.

2 ~
To support variou~ pixel mosaic~ including the delta tri-ad ~Fig. 2(e)) and quad-green (Fig. 2(~)) color mosa~cs, the ~ize of the line buffer must be modular since the buf~er may hold th~
data ~or two scan line~ as in the case~ of those two special mosaic~, The operation of ths MLB 36 ia proqrammable by the means shown at 49, 50 to handle the difference in the input and the output scan frequenc~es ~n the case of the quad-green mosaic~
The MLB~s lnter~ace 39 to the display adapter (inputs to the MLB) remaine the ~ame reqardless o~ c:olor mosa~c~ The ML~ 36 receives the display data one pi.xel (in RGB components) at a ~ime serially, and sends out the data at the speed mat~hing the data rate required for the flick-~ree refresh.
The CPA~ unit 38 controls the access and re-ordering of the data being read out of the MLB, as pxogrammed according to the panel mosaic being driven. As a result, the controller 25 of the invention hides the panel-specific control and data rear-rangements, and thus provides a s;mp~e and universal interface to the host system. The data format sent to ~he display panel ls thus controlled by the CPA~ unit 38 in coniunction with the pro-gra~mable regist~rs 49. The CPA~ 38 ~ontrols the decoder~ of the MLB such that ~he color pixel components in the right sequence are read out, rearranges them if necessary, and sends the~ to the PLU 37 in the correct order. It also ~etches and ~uffers ap-propriate adjacent pixel components to be used by the PLU for anti-aliasing.

XRX.116.001.6 (D/91471) -17-2 ~ 7 ~
In a pr~ferred embodlment shown in Fig. 7, the CPAL 3B
comprises a controller 55 and a number o~ identical datapath~ (N
when the panel is splik N ways vertically~. The con~roller readR
the programmable regi~ter 49 and genera~es the addresses and s control signals for the MLB and the datapath. The datapath ln-clude~ an input buffer 56, threle FIF0 buffers 57, and multi-plexors 58 in between the buf~ers, to re~rrange the data ~ormat.
The input buffer 56 latches one or two ad~acent (horiæontal) color pixel data (three RGB components) as illustrated in Fig.
2(b) and composes the data sequenc~ in the panel's color com-ponent order. The FIF0 buffer 57 holds 3 by 3 color component data fetche~ ~rom three adjacent line buffers in the MLB 36 in horizontal order. Each element in a FIF0 buffer represents one color component of the RGB components of eight adjacent color pixels. All nine components ~see Fig. 7~a)) are fed simulta-neously to th~ PI~, but the center element, designated P(i, j), is the current component being displayed in the panel. Adjacent components are used for anti-aliasing processing. The PAL 38 sends out one set of data (nine components) at a time, and to-gether with the PLU 37 it implements the highly pipelined opera-tion to meet the refre h rate requirement.
Similarly to the CPAL unit 3B, the controller 25 of the invention includes N units 60 of identical PLU's 37 to implement two dimensional ant~-aliasing of the display image~, and to per-form temperature correction of gray scale on individual color components. See Fig. 8. The number N her~ is the number of scan XRX~116.001.6 ~DJ91471) -18 207~

drives required by the panel when dlvided in N vertical w~y~.
Each PLU 60 consist~ o~ several lookup tables (R~MIs) 61-64 and an adder tree 65. The lookup tables are read/wr~te RAM, so ~ome parameters of ths anti-aliasiny algorithms a~ well a3 temperature correction are programmable for specific applic~tions. The PLU
37 supports ~he anti~aliasing algorith~ based on a 3 by 3 pixel kernel. See Fig7 7(a). Both the anti-aliasing (lookup tables 61-63~ and the temperature correction (lookup kable 64) can be performed on each color component independently.
Much of anti aliasing research has ~ocused on methods o~
creating lines or edge9 that appear smooth on raster displays.
These known anti-aliasing algorithms frequently employ gray-scal~
to create a luminance distribution or ~ilter across a line or an edg~. These efforts smooth the jag~ed appearance of diagonal lS lines by lessening t~e effect of the discrete steps produced on matrix display panels. A reasonable and efficient approach is to band limit the digital images by the quantized gray-scale or luminance leYels. llhe anti-alia~ing algorithm supported by t~e PLU 37 incorporated in the pre~erred e~bodiment o~ the invention maps a spatially oriented luminance profile to the underlyinq pixel array ~3x3)~ by cali~rating the gray level of each pixel relative to adjacent pixels~ Typical luminance pro~ile~ that can be employed are Gausian, lin~ar, and trapezoidal line spread functions. It should be noted that the method of spatial band limiting with the Gaussian luminance pro~ile is a discrete ap-proximation of the way in which th~ Gaussian electron beam in a XRX.116~001.6 (D/91471) 19-2 ~

shadow-mask color CRT s~rv~s to band 1l~lit spatial ~requenc1es before they are sampled by the RGB phosphor dots at the CRT
faceplat~ These kind~ o~ algorithms are described in ths referenced publlcations ~9, 10].
Fig. 8 sho~s the hardware elements of each PLU unit 60.
As nine color component data are fed i~, they are separated $n three different weight groups, diagonally ad~acent component~, perpendicularly adja~ant compon~nts, and the center component.
The nine components values ~re used to access three corresponding loo~up tables 62, 61, 63 to fets~h their weighted contribut~ons, and the adder tree 65 computes the weighted average of the center component. The contenk of the lookup tables is programmable and algorithm speci~ic for the given pixel kernel and computing structure. The pixel kernel structure is also programmable within the maximum limit of 3x3 pixels.
The computed pixel component value 67 and current operat ing temperature information obtained from a known temperature sensor 6~ are then used to access another lookup table 64 holding data to be used in correcting the gray level. The current temperature informAtion selects the corresponding segment of the table divided in di~erent temperature se~ments, while the pixel value selects the temperature adjustment value within the seg-ment. The temperature adjustment value may not be uniform along the transmission curve, and thus the component gray value is fur-2S ther divided into several dif~erent regions as shown in Fig. 3.
The last adder 69 in the PLU adds or subtracts the temperatur~

XRX.116.001.6 (D/91471) ~o-~7~

ad~ustmen~ value to or from the origlnal value. The operatlon oP
the PLU 60 is controlled by programmable registers and both anti-aliasing and temperature correction may be turned of~ partlally or fully depending on application.
The host interface 39 (Fi~. 53 includes a byte-wide, parallel port that can be connected directly to the data bus o~ a host processor. The hos~ proces,sor may be of any type o~ con-troller or microprocessor. Th~ 'ho~t inter~ace 39 ha~ an lntern~l controller ~not shown~ handling data trans~ers ln and out o~ the programmable registers, and may use an external PROM to program the registers. The host interface port consists o~ byte,-wide data bus, address but, and data transf~r control signals.
All programmable registers incorporated in the controller 25 are readJwrite accessible, and grouped into ~our di~ferent categories to hold parameters of~ display configuration (e.g. panel resolution) (2) pixel configuration (e.g. color mosaic), (3) anti aliasing (e.g. pixel kernel), and (4) tempera-ture correction (e.g. lookup table organization~. These paramet-ers are used in various blocks as described above to genPrate correct data format and control signal5 for the panel ~nd dri~er IC's, respectively. The specific circuitry to implement thi5 i~
straightforward and will be evident to those skilled in this art from the foregoing specification teachings.
Summarizing~ while the AMLCD technology offers a sig-nificant opportunities for a high resolution, high qual,ity dis-play, it introduc~ng serious problems in producing low-cost~ high XRX.116.001.6 ~D/91471) ~lo ~ 5 ~ ~ ~

performance ~LCDIs. The combinatlon o~ several technologie~
that makes the AMLCD technology exceed the CRT technology ln ob-taining higher quality display~, for example, the panel technol-ogy, row and column driver IC' B, packaging and assembly oP panel and drivex~, and display adapter/controller~, is what bri~g~
about the probl~. A~ the pan~l technology advances, the prob-lems multiply as a lar~er and higher re~olut~on display becomes available forcing other designs, such as driver IC and display adapter, to change. ~o make suc:h changes cost-ef~ectiYe and to raise the quality of ~n overall display system, the AMLCD con-troller of this invention implements various features that could otherwi~e be implemented in other parts of the system but at a signi~icantly higher cost. Data reordering and pixel mosaic rearrangementæ vary among different panel technologies and it will be almost impractical to implement them in either driver IC's or display adapters~controll~rs. But, a local memory on a single chip to buffer a ~ew adjacent lines provides a si~ple in-terface to the ho5t system, while flexible and ~ast accesses are available to the display for various data format changes. Bu*-~ring of a few lines also provides the opportuni~y for image processing using a small but two dimensional plxel array, at a reasonably low cost. The temperature correction is of~en done in the display adapter, which is undesirable since it makes the adapter/controller technology dependent. With a minimal hardware 2S addition, the ad~ustment to the temperature change can be done ea~ily and accurately. ~ost importantly, the controller of the XRX.11~0~1.1& (~/91471) -22~

2~7~s~

~nvention establishe~ ~ programmable int~rface to variou~ type~
o~ the AM~CD's, and can thus become a standard and universal way of drlving ~MLCD panels correctly and efficlently.
Th~ controller of the invention is not limited ~or it~
image enhancement or anti-aliasing featur~ to the alyorithm de-scribed using the 3x3 array and an averaging scheme for determin-ing the intensity of each pixel along a line or an edge. Due to the ~ultiple line buffer memory provided, this lmage ~nhancement scheme can in general use known al~orithms which substitut~ in certain scan lines pixel element values derived from values stored in previous or subsequent lines and ~ollows naturally ~rom the presence of the m~ltiple scan line buffer storeO This aspect of the invention is also not limited to speci~ic algorithms. Th~
enhancements will be mainly used in overcoming jaggy or staircase appearance of lines and edyPs on these raster displays. It ultimately boils down to fixing the gray-scale intensity level for each pixel, especially at color or ar~a transitions. Exam-ples o~ suitable algorith~s are described in publications C8;
lO]t and in publications by Hewlett~Packard de~cribing their Laser Jet R~solution Enhancemen$ Technology (RET) syste~
Also, while the split screen drivinq ~eature has been d~-scribed in connection with a two-way, le~t and right hal~ spl~t, it will be understood that it is straight~orward by upward scal-ing to implement a control~er that will support mor~ split screens than two, e.g., six ~or XGA-resolution, and the invention is not limited to ~ two-way split screen.

XRX.116.001.6 (D~91471~ -23~

It also will be un~erstood that the invention is not llmited to lncorporation of all of the various feature~ a~ de-scribed herein in a co~mon, single chip, st~nd-alone controller.
To the extent that the prior art allows, the invention con templates a con~roller chip incorporating each of the featurç~
alone, as well as various combinations of the ~ea~ures, though it is recognized that the full gamut of advantages is not realized in the absence o~ one or more of the feature~. Neverthele~, in corporation of one or several features still represent~, to 'che best of our present knowledge, a decided improvement over currently-available AMLCD controllers.
To implement the controller of the invention as a single chip is a straightforward task using conventional IC processing.
The individual circuits themselves are well known in other con-texts, and are readily provided combined in a single chip in the same manner as they would be as a separate chip.
For completeness' sake, the contents of the cited references in the Appendix, and that o~ the other patents~publications re~erenced herein are hereby incorporated by reference.
While the invention has been described and illustrated in connectio~ with preferred embodiments/ many variations and modi fications as will be evident to those skilled in this art may be made therein with~ut departing from the spirit of the invention/
and ~he i~vention as set ~orth in the appended claims is thus not to be limited to th~ precise deta~ls of construction set ~orth ; XRX.116.001.6 (DJ91471~ -24-2~7~

above as such variation8 and modif~catiQn8 are intended to be in cluded within the scope o~ the appended claims.

XRX. 116 . 001. 6 (D~91471) -25-

Claims

1. A controller for an active matrix TFT LCD comprising:
(a) an input for receiving a video data stream formatted as a sequence of serial lines, (b) buffer memory means connected to the input for stor-ing a plurality of adjacent lines of the data stream, (c) means connected to the buffer memory means for re-ordering the video data into a format for parallel outputting to drive a selected LCD having one of a plurality of color subpixel arrangements, said subpixel arrangements including a delta and quad arrangement of the plural colors.

2. The controller of claim 1, wherein the subpixel ar-rangements further include horizontal, vertical, diagonal and staggered stripe subpixel arrangements.

3. The controller of claim 2, wherein the controller comprises a single integrated circuit chip.

4. The combination of the controller of claim 3 and the selected LCD.

5. A controller for an active matrix TFT LCD comprising:
(a) an input for receiving a video data stream formatted as a sequence of serial lines, (b) buffer memory means connected to the input for stor-ing a plurality of adjacent lines of the video data stream, (c) means connected to the buffer memory means for re-ordering the video data into a format for parallel outputting to XRX.116.001.6 (D/91471) -26-a selected LCD for simultaneously driving vertically split parts of the LCD.

6. The controller of claim 5, wherein the LCD is verti-cally split for driving purposes into left and right halves.

7. The controller of claim 6, wherein the controller comprises a single integrated circuit chip.

8. The combination of the controller of claim 7 and the selected LCD.

9. A controller for an active matrix TFT LCD comprising:
(a) an input for receiving a video data stream formatted as a sequence of serial lines, (b) buffer memory means connected to the input for stor-ing a plurality of adjacent lines of the video data stream, (c) means connected to the buffer memory means for re-ordering the video data to provide two-dimensional image quality enhancement for parallel outputting to a selected LCD.

10. The controller of claim 9, wherein the reordering is into a 3x3 array of pixels, and further comprising weighting means for modifying the gray scale of the center pixel of the ar-ray as a function of the intensities of the surrounding pixels in the array.

11. The controller of claim 9, wherein the controller comprises a single integrated circuit chip.

12. The combination of the controller of claim 9 and the selected LCD.

XRX.116.001.6 (D/91471) -27-

13. A controller for an active matrix TFT LCD compris-ing.
(a) an input for receiving a video data stream formatted as a sequence of serial lines, (b) buffer memory means connected to the input for stor-ing a plurality of adjacent lines of the video data stream, (c) means connected to the buffer memory means for re-ordering the video data to compensate for changing temperatures and for parallel outputting to a selected LCD, (d) means connected to the means of element (c) for detecting changing temperatures.

14. The controller of claim 13, wherein the controller comprises a single integrated circuit chip.

15. The combination of the controller of claim 13 and the selected LCD.

16. The combination into a single chip of the control-lers of claims 1, 5, 9 and 13.

17. A single chip stand-alone controller for an active matrix TFT LCD comprising:
(a) means for receiving serial video data, (b) means under user control for re-ordering the video data into one of a plurality of formats each corresponding to what is required for driving a different arrangement of color subpixels in a selected LCD, said different arrangements includ-ing horizontal, vertical, diagonal, delta triad, and quad green color subpixel arrangements.

XRX.116.001.6 (D/91471) -28-

18. The single chip controller of claim 17, wherein the means of element (b) comprised a multiple line buffer.

19. The single chip controller of claim 18, wherein the multiple line buffer is capable of storing four scan lined of video data.

20. The single chip controller of claim 17, wherein the re-ordering will allow simultaneous driving of vertically split parts of the LCD.

21. The single chip controller of claim 17, further com-prising means for two-dimensional image quality enhancement of the video image represented by the inputted video data.

22. The single chip controller of claim 17, further com-prising means for modifying the gray scale of pixels at image transitions in accordance with the intensity of surrounding pixels.

23. The single chip controller of claim 22, further com-prising means responsive to the operating temperature of the LCD
for compensating for changes in LCD properties.

24. The single chip controller of claim 23, wherein the means of element (b) comprises internal programmable registers.

25. The single chip controller of claim 18, wherein the line buffers are each divided into plural modules.

26. The single chip controller of claim 17, wherein the means of element (b) further comprises a first buffer, a multi-plexer, and a second FIFO buffer serially arranged.
XRX.116.001.6 (D/91471) -29-

27. The single chip controller of claim 21, wherein the image quality enhancement means comprises multiple lookup tables for weighted averaging of pixel intensity, and an adder of the weighted values.

28. The single chip controller of claim 27, further com-prising a temperature detector and an additional lookup table for modifying pixel intensity to compensate for temperature changes.
XRX.116.001.6 (D/91471) -30-