JP3108844B2 - Display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for performing gradation display by time modulation.

[0002]

2. Description of the Related Art Conventionally, in a display device having no gradation display function, there is a method of changing the appearance time ratio of two states, for example, white display and black display, as a method of performing pseudo gradation display. This is generally time modulation, frame (screen)
A method called modulation or frame thinning is disclosed in, for example, JP-A-61-69036. However, this method takes extra time by the number of gradations,
In order to display eight gradations with one pixel, FIG.
As described above, the time required for seven frames of the conventional binary display is required.

On the other hand, by changing the timing of inputting a reset pulse for each sub-frame (modulation time unit) disclosed in Japanese Patent Application Laid-Open No. Sho 62-56936, three frames for a conventional binary display can be obtained. A method of displaying eight gradations in a time period has been proposed.

[0004]

However, the above 3)
The method of displaying eight gradations in the time of a frame is shown in FIG.
As shown in FIG. 3B, since the reset period is long, there is a problem that the average luminance at the time of brightest display is reduced by nearly 40% as compared with the case of binary display.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a matrix display device which performs gradation display in a short time and by a time modulation method which keeps the average brightness at the time of brightest display at the same level as that at the time of binary display. It is in.

[0006]

According to the present invention, there is provided a matrix electrode comprising a scanning electrode group and an information electrode group. When n is a natural number, one frame period is required for displaying 2 ⁿ gradations. Is divided into n sub-frame periods, and a gradation display is performed by performing n selective scans on each scanning electrode within one frame period. The application interval of the information signal waveform to the information electrode is set substantially uniformly, and the time interval for selecting the scanning address is set unequally by changing the scanning start address of each subframe. And
When the ratio of the display period of each sub-frame is set arbitrarily,
In addition, the display state during the display period of each sub-frame is
Select either the bright state or the dark state according to
In this case, gradation display is performed by using

The present invention is an apparatus for performing gradation display by the time modulation, and performs one screen display by a plurality of scans. In the present invention, the one-screen scanning period is a total period of scanning required to display a final one screen, and a plurality of frames for displaying one frame of the predetermined one display screen and a plurality of frames for gradation display. A screen displayed in one scanning unit of the scanning performed one time is called a sub-frame. That is, one frame is displayed by scanning the sub-frame a predetermined number of times.

[0008]

A specific example of the driving method according to the present invention will be described with reference to FIGS.

FIG. 20 is a drive control circuit diagram. In the figure, DSP is a display unit, and A ₁₁ , A ₁₂ .
.. _A44 indicate each pixel. M1, M2, and M3 are frame memories each having a memory capacity of 4 × 4 = 16 bits. Data is sent from the data bus DB to the memories M1, M2, and M3, and write and read addresses are controlled by the control bus CB.

FC is a frame start signal, SFC is a subframe switching signal, DC is its decoder, MPX is a multiplexer for selecting one of the outputs of memories M1, M2 and M3, _Hsync is a scan clock signal, and CNT is CNT. The counter and SR are serial input parallel output shift registers, DR1 to
DR4 is an information drive circuit, DR5 to DR8 are scan drive circuits, and apply waveforms to D1 to D4 and B1 to B4.

FIG. 21 shows the gradation data of each pixel in one frame. The upper bits of each gradation data are stored in the memory M3.
The middle bit is stored in the memory M2, and the lower bit is stored in the memory M2.
1 through the data bus.

FIGS. 22A to 22C are conceptual diagrams of M1 to M3, and FIGS. 23 and 24 are driving timing charts of the circuit of FIG.

A screen for displaying the contents of the memory M1 is a first screen.
Subframe, the contents of the memory M2 are the second subframe ,
The content of the memory M3 is called a third sub- frame, and one frame scanning period is divided into six, and the first, third, first, second,.
It is assigned to the scanning periods of the second and third subframes . In the first and third subframes, the scanning selection is DR5, D
R6, DR7, and DR8 are performed in this order, and in the second subframe, DR7, DR8, DR5, and DR6 are performed in that order. Then, since only two scan lines can be selected in one of the six divided periods, each scan electrode is selected in either the first half or the second half of the divided sub-frame. In the selected scanning line, writing is first performed in 1/12 of one frame scanning period, and then display is performed until the same scanning line is scanned in a different sub-frame. Therefore, a period for displaying each sub-frame, the A ₁₁ to A ₄₄ all, first: second: third
= 1: 3: 5. Therefore, depending on the combination of subframes, 0/9, 1/9, 3/9, 4/9, 5/9,
Eight types of periods, 6/9, 8/9, and 9/9, can be selected. As a result, eight gradations can be displayed by time modulation.

FIG. 24 shows the state of display gradation of each pixel when the gradation data shown in FIGS. 21 and 22 are provided. FIG.
Numerical values shown in (1) and (2) indicate periods during which bright display is performed during the display period of one frame scanning period. Therefore, the darkest display is 0,
The brightest display is 1. FIG. 25 shows a waveform used for this display. The scanning selection signal waveform is composed of a reset pulse for setting a pixel to a dark state and a selection pulse for selecting a light state or a dark state. Hereinafter, the operation of the circuit of FIG. 20 will be described.

When the frame start signal FC is generated, the data in the memories M1 to M3 is rewritten by the control bus CB and the data bus DB. Then, the sub-frame switching signal SFC is generated, and the decoder DC sets the multiplexer MPX to select the data from the memory M1.

The counter C is synchronized with the scanning clock _Hsync.
NT applies a scan selection signal waveform from driver DR5 to B1. At this time, the data of the first row of the memory M1 is input to the shift register SR, and the drivers DR1 and D1
A dark signal waveform is applied to R2 and DR4, and a bright signal waveform is applied to DR3. Therefore, only the pixel A ₁₃ is in the bright state, A ₁₁ ,
A ₁₂ and A ₁₄ are in a dark state. In synchronization with the next scan clock H _sync counter CNT applies a scanning selection signal waveform to the driver DR6. At this time, the data of the second row of the memory M1 is input to the shift register SR.

Next, when the sub-frame switching signal SFC is generated, the decoder DC sets the multiplexer MPX to select the data from the memory M3. Thereafter, as described above, a scanning selection signal waveform and an information signal waveform are output in synchronization with the row scanning signal F. The subframe selection order and the scanning selection order within the subframe are provided with separate memory areas (not shown). ), Contents are set in advance. Here, the contents are shown in Tables 1 and 2.

[0018]

[Table 1]

[0019]

[Table 2]

When one frame is completed, a frame start signal FC is generated again, and the data in the memories M1 to M3 is rewritten to the data of the next frame.

Incidentally, a configuration may be adopted in which both the sub-frame and the scanning address are switched in synchronization with the scanning clock _Hsync without using the sub-frame switching signal SFC. In this case, the contents shown in Table 3 are set in the memory area in advance.

[0022]

[Table 3]

As described above, the gray scale driving method in the display device of the present invention has the same gray scale number display capability in a shorter time, higher luminance, and higher than the conventional gray scale driving method based on the time modulation method. Tables 4 and 5 and FIG. 26 show a comparison with the conventional example (based on binary display). Figure 26
(A) is Conventional Example 1, (b) is Conventional Example 2, and (c) is
3 shows a display period of the invention.

[0024]

[Table 4]

[0025]

[Table 5]

[0026]

【Example】

(Embodiment 1) FIG. 1 shows a display device according to an embodiment of the present invention. This display device has a display portion 101 having a matrix electrode composed of a scan electrode 201 and an information electrode 202 shown in FIG. 2, an information signal application circuit 103 for applying an information signal to liquid crystal through the information electrode 202, and a scan signal. Scanning electrode 20
1, a scanning signal application circuit 102, a scanning signal control circuit 104, an information signal control circuit 106, a drive control circuit 105, a thermistor 108 for detecting the temperature of the display unit 101, and an output of the thermistor 108. Temperature detection circuit 109 for detecting the temperature of display unit 101 based on
Is provided. An optical modulation material such as a liquid crystal is arranged between the scanning electrode 201 and the information electrode 202. Reference numeral 107 denotes a graphic controller. Data sent from the graphic controller 107 is input to a scanning signal control circuit 104 and an information signal control circuit 106 through a drive control circuit 105, and is converted into address data and display data, respectively. Further, the temperature of the liquid crystal display unit is input to the temperature detection circuit 109 via the thermistor 108, and is input to the scanning signal control circuit 104 via the drive control circuit 105 as temperature data. Then, the scanning signal applying circuit 102 generates a scanning signal according to the address data and the temperature data, and applies the scanning signal to the scanning electrode 201 of the liquid crystal display unit 101. Further, the information signal applying circuit 10 according to the display data.
3 generates an information signal, and the information electrode 202 of the display unit 101
To be applied.

In FIG. 2, reference numeral 222 denotes a pixel which is constituted by an intersection between the scanning electrode 201 and the information electrode 202 and is a display unit. Each scanning electrode 201 and information electrode 202,
A matrix (matrix electrode) of such 640 × 400 pixels is composed of 200 and 640 pixels.

FIG. 3 is a partial sectional view of the display unit 101.
In FIG. 1, reference numeral 301 denotes an analyzer, and 305, a polarizer, which are arranged in crossed Nicols. 302 and 304 are glass substrates, 303 is an optical modulator, and 306 is a spacer.

The optical modulator used in the present invention includes a first optically stable state (for example, a bright state is formed) and a second optically stable state (for example, dark state) according to an applied electric field. A material having a bistable state with respect to an electric field, in particular, a liquid crystal.

As the liquid crystal having bistability which can be used in the driving method according to the present invention, a chiral smectic liquid crystal having ferroelectricity is most preferable. Among them, chiral smectic C phase (SmC ^* ) and H phase (SmC ^* )
H ^* ), I phase (SmI ^* ), F phase (SmF ^* ), and G phase (SmG ^* ) liquid crystals are suitable. About this ferroelectric liquid crystal, "LE JOURNAL DE PHYS
IQUE LETTERS "36 (L-69) 197
5, "Ferroelectric LiquidCr
ystals ";" Applied Physics
Letters "36 (11) 1980," Submi
cro Second BistableElectr
optical Switching in Liqui
d Crystals ”;“ Solid State Physics ”16 (141)
1981, "Liquid crystal", and the ferroelectric liquid crystal disclosed therein can be used in the present invention.

More specifically, for example, desyloxybenzylidene-p'-amino-2-methylbutylcinnamate (DOBAMBC), hexyloxybenzylidene-
p'-Amino-2-chloropropylcinnamate (HO
BACPC) and 4-o- (2-methyl) -butylresorcylidene-4′-octylaniline (MBRAS). When a device is formed using these materials, the liquid crystal compound is composed of SmC ^* , SmH ^* , SmI ^* , and SmC ^* .
In order to maintain a temperature state such that mF ^* and SmG ^* , it is preferable that the element is indicated by a copper block or the like in which a heater is embedded as necessary.

FIG. 4 schematically shows an example of a ferroelectric liquid crystal cell. In the figure, 11 and 11 'are In ₂ O ₃ , SnO ₂
Or a substrate (glass plate) coated with a transparent electrode such as ITO (Indium-Tin Oxide), between which an SmC ^* phase liquid crystal in which the liquid crystal molecule layer 12 is oriented perpendicular to the glass surface is sealed. . Line 1 shown in bold
Reference numeral 3 denotes a liquid crystal molecule, and the liquid crystal molecule 13 has a dipole moment 14 in a direction perpendicular to the molecule. When a voltage equal to or higher than a certain threshold is applied between the electrodes on the substrates 11 and 11 ′, the helical structure of the liquid crystal molecules 13 is released, and the dipole moments 14 are all directed to the electric field direction.
The alignment direction of the liquid crystal molecules 13 can be changed. The liquid crystal molecules 13 have an elongated shape and exhibit refractive index anisotropy in the major axis direction and the minor axis direction. Therefore, for example, if polarizers arranged in a crossed Nicols positional relationship above and below the glass surface are placed. It can be easily understood that the liquid crystal optical modulation element changes its optical characteristics depending on the polarity of the applied voltage.

Further, when the thickness of the liquid crystal cell is sufficiently reduced (for example, 1 μm), the helical structure of the liquid crystal molecules is unwound (non-helical structure) even when no electric field is applied as shown in FIG. The child moment P or P ′ takes an orientation state of either upward 24 or downward 24 ′. When an electric field E or E 'having a polarity equal to or more than a certain threshold is applied to such a cell as shown in FIG. 5, the dipole moment is increased upward corresponding to the electric field vector of the electric field E or E'.
Or, the direction is changed to the downward direction 24 ′, and the liquid crystal molecules are aligned in one of the first stable state 23 (bright state) and the second stable state 23 ′ (dark state) accordingly.

The use of such a ferroelectric liquid crystal as an optical modulation element has two advantages. First, the response speed is extremely fast, and second, the orientation of the liquid crystal molecules has bistability. The second point will be described with reference to FIG. 5, for example. When an electric field E is applied, the liquid crystal molecules are in the first stable state 23.
In the first stable state 23 even when the electric field is cut off.
Is maintained, and when an electric field E 'in the opposite direction is applied, the liquid crystal molecules are oriented to the second stable state 23' and change the direction of the molecules.
Each stable state has a memory function. Also,
As long as the applied electric field E does not exceed a certain threshold value, each orientation state is also maintained. In order to effectively realize such a high response speed and bistability, it is preferable that the cell be as thin as possible.
-20 μm, especially 1 μm-5 μm is suitable. A liquid crystal-electro-optical device having a matrix electrode structure using a ferroelectric liquid crystal of this type has been proposed, for example, by Clark and Lagabal in U.S. Pat. No. 4,367,924.

FIG. 6 is a timing chart when eight gradations are displayed using three subframes. In the figure, FC is a frame start signal, _Hsync is a scan clock signal, MPX is a selection line of a multiplexer (not shown) for selecting one of the frame memories M1, M2, M3 (not shown), and B1 to B200. Represents a scanning electrode or a scanning address, and the count represents the number of times of scanning of the display unit in a frame.

First, a frame start signal FC is generated, and data in the memories M1 to M3 is rewritten. Then, in synchronization with the scanning clock signal _Hsync , the selection content MPX of the multiplexer and the scanning address change in the order shown in Table 6. Table 7 is obtained by rewriting the contents of Table 6 for explaining the scanning order. M1 the contents of the MPX for each H _sync, M2, M3,
.. Are periodically changed to M1, M2, M3..., And scanning is performed with no interlace in each subframe. Then, the display period of the first sub-frame, the display period of the second sub-frame,
The scanning start address of each sub-frame is set to B so that the display period ratio of the sub-frame becomes approximately 1: 2: 4.
1, B173 and B116. For example, scanning address B
Focusing on 1, the display period of the first sub-frame is 84 × H _{sync with} a count of 2 to 85, and the display period of the second sub-frame is 171 with a count of 87 to 257.
The period of × H _sync and the display period of the third sub-frame are 342 × H _sync with a count of 259 to 600, and the ratio is 84: 171: 342 ≒ 1: 2: 4.1.

FIG. 7 is a diagram simply showing the relationship between the scanning address and the display timing. As can be seen from FIG.
The scanning address selection intervals are not uniform within the frame scanning period.

[0038]

[Table 6]

[0039]

[Table 7]

When there is no change in the content of the temperature data, the period of _Hsync is constant, and the interval of application of the information signal waveform is also constant.

On the other hand, if there is a change in the content of the temperature data, the cycle of _Hsync changes accordingly, so that the application interval of the information signal waveform is not constant. However, if the temperature change is not rapid, the change of the H _sync cycle is 10% within one frame.
Therefore, it can be said that the application interval of the information signal waveform is substantially constant.

FIG. 8 shows the driving waveform used in this embodiment.
In this embodiment, the selection interval of the scanning address is set to be 1: 2: 4. However, by changing the scanning start address of each subframe, the selection interval ratio, that is, the ratio of the display period of each subframe can be arbitrarily set. Can be set. For example, when the start address of each sub-frame is set to B1, B183, and B129, it becomes approximately 1: 3: 7.

It is to be noted that a color filter is provided for each pixel of the present embodiment, so that a multi-color display device can be obtained. It is also possible to further increase the number of display gradations by combining with a gradation method other than frame modulation, for example, a pixel division method.

(Embodiment 2) FIG. 9 is a timing chart in the case where the scanning method is changed in the same apparatus as in Embodiment 1, and the scanning address and MPX change in the order of Table 8. M
The contents of the PX to each _{H sync M1, M2, M3,} M1, M
2, and M3 are changed periodically, and scanning is performed by interlacing in each subframe. The scanning start addresses of the sub-frames are set to B1, B146, and B32 so that the ratio of the display periods of the sub-frames is approximately 1: 2: 4. Interlaced scanning within a sub-frame can suppress flicker on the screen, especially when the frame frequency is as low as 40 to 20 Hertz.

FIG. 10 shows the relationship between the scanning address and the display timing at this time. In the figure, the first field selects an odd-numbered scanning address, and the second field selects an even-numbered scanning address.

The ferroelectric liquid crystal, which is the optical modulation element used in this embodiment, has a temperature characteristic in response speed, and the response becomes slow at low temperatures. Therefore, the scanning order in each subframe is changed from no interlace to interlace according to the temperature. Switch to.

In this embodiment, the method of interlacing the scanning in each sub-frame has been described. However, it is also possible to use two or more interlaced interlaces (multi-interlacing) and randomize the scanning order by the same method. is there.

[0048]

[Table 8]

(Embodiment 3) FIG. 11 shows a third embodiment of the present invention. In this embodiment, the display unit 101 is an effective display unit 101a.
And a frame portion 101b.

As shown in FIG. 12, a frame scanning electrode group 121w is provided at both ends of a scanning electrode group 121, and a frame information electrode group 122w is provided at both ends of an information electrode group 122, and they are bonded to each other.
And a frame portion 101b is formed. Frame part 1
By providing 01b, the following effects can be obtained.

The display element is housed in a chassis or a decorative box to maintain functionality, safety and aesthetics, and to protect the electrical system of the element. However, the display surface is inclined depending on the thickness of the chassis or the decorative box. It may be hidden when viewed from the direction. To avoid such a case, a frame (non-display part) is provided around the display part, and the effective display area is
The device is designed so that it is not hidden unless viewed from an angle outside a certain range.

However, in this case, the above-mentioned frame portion is
In the case of a medium having a memory property such as LC, the FLC is in an arbitrary state until an electric signal equal to or higher than the threshold is applied. Impair. Therefore, it is necessary to make the frame part uniform by a certain electric signal. However,
The memory property here is not limited to a permanent one as long as it satisfies image quality and display function as a display element. Therefore, it is necessary to apply a drive signal periodically.

Therefore, a uniform frame portion is realized by providing a frame portion driving electrode around the display portion and applying an electric signal to the electrode to drive the liquid crystal in the frame portion.

The configuration of FIG. 11 except for the display unit 101 is the same as that of the first embodiment.

FIG. 13 is a timing chart when eight gradations are displayed using three subframes. In the figure, W is a frame scanning electrode or a frame scanning address, and the other components are the same as those in the first embodiment.

First, a frame start signal FC is generated, and data in the memories M1 to M3 is rewritten. Then, in synchronization with the scanning clock signal _Hsync , the selection content MPX of the multiplexer and the scanning address change in the order shown in Table 9. M
The contents of the PX to each _{H sync M1, M2, M3,} M1, M
2, M3... Are periodically changed, and scanning is performed by interlace in each subframe. For example, in the first subframe, B
1, B3, B5... B199, B2, B4. And the count is 200, 400,
When the number reaches 600, the counting is stopped and a frame scanning address is selected. When the frame frequency is 20 to 40 Hz, the frame scanning frequency is 60 to 120 Hz, so that flickering due to the frame scanning does not occur. In the present embodiment, the frame scan is performed every 200 counts, but the frame scan is not necessarily 200 counts.
Also, it is not necessary to perform frame scanning in units of counts,
Frame scanning may be performed in units of time, such as performing frame scanning after msec.

[0057]

[Table 9]

FIG. 14 is a diagram simply showing the relationship between the scanning address and the display timing. Compared to FIG. 10, it can be seen that frame scanning is performed immediately after the counts 200, 400, and 600.

FIG. 15 shows a driving waveform used in this embodiment. FIG. 16 is a timing chart when another frame drive waveform is used. FIG. 17 shows the driving waveform at this time.

(Embodiment 4) A case where four gradations are displayed by the display device of Embodiment 1 will be described. In this case, two frame memories M1 and M2 constitute one frame (400 counts) with two subframes. When the selection order of the MPX and the scanning address is as shown in Table 10, the ratio of the display periods in each subframe is 1: 2, and as shown in Table 11, it is 1: 3. FIG. 18 is a diagram showing the relationship between the scanning address and the display timing.
(B) is a case where the selection order in Table 11 is used.

[0061]

[Table 10]

[0062]

[Table 11]

[0063]

As described above, according to the display device of the present invention, the average luminance at the time of brightest display is improved to the level of binary display, and at the same time, gradation display is performed in a short time, and more excellent image display is achieved. Can do it.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is an enlarged view of a display unit according to the first embodiment of the present invention.

FIG. 3 is a sectional view of a display unit shown in FIG. 2;

FIG. 4 is a perspective view schematically showing a liquid crystal element that can be used in the present invention.

FIG. 5 is a perspective view schematically showing a liquid crystal element that can be used in the present invention.

FIG. 6 is a drive timing chart according to the first embodiment of the present invention.

FIG. 7 is a diagram simply showing a relationship between a scanning address and a display timing according to the first embodiment of the present invention.

FIG. 8 is a driving waveform used in the first embodiment of the present invention.

FIG. 9 is a drive timing chart according to the second embodiment of the present invention.

FIG. 10 is a diagram simply showing a relationship between a scanning address and a display timing according to the second embodiment of the present invention.

FIG. 11 is a block diagram of a third embodiment of the present invention.

FIG. 12 is a diagram illustrating a display unit according to a third embodiment of the present invention.

FIG. 13 is a drive timing chart according to the third embodiment of the present invention.

FIG. 14 is a diagram simply showing a relationship between a scanning address and a display timing according to the third embodiment of the present invention.

FIG. 15 is a driving waveform used in the third embodiment of the present invention.

FIG. 16 shows another driving waveform used in the third embodiment.

FIG. 17 shows another driving waveform used in the third embodiment.

FIG. 18 is a drive timing chart according to the fourth embodiment of the present invention.

FIG. 19 is another drive timing chart of the fourth embodiment of the present invention.

FIG. 20 is a drive circuit control diagram of the present invention.

FIG. 21 is a diagram showing gradation data of each pixel in one frame according to the present invention.

FIG. 22 is a conceptual diagram of memories M1 to M3 according to the present invention.

FIG. 23 is a drive timing chart of the circuit in FIG. 20;

24 is a diagram illustrating a gray scale display state of a pixel based on the gray scale data illustrated in FIG. 21;

FIG. 25 is a driving waveform used in the circuit of FIG. 20;

FIG. 26 is a diagram showing display periods of the present invention and a conventional example.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/133 505-580 G09G 3/36

Claims (2)

(57) [Claims] 1. A matrix electrode comprising a scanning electrode group and an information electrode group. When n is a natural number, one frame period is reduced to n subframe periods in order to display 2 ⁿ gray scales. The scanning is divided and n is applied to each scanning electrode within one frame period.
A time modulation matrix display device that performs gradation display by performing selective scanning twice, wherein the application interval of information signal waveforms is set substantially uniformly to all information electrodes in one frame period; and Scanning of each sub-frame
When selecting a scan address by changing the start address
Between intervals set unevenly, the display period of each subframe
And the display period of each sub-frame.
The display state between the bright state and the dark state according to the information signal
A display device characterized in that gradation display is performed by selecting either one of them . 2. The display device according to claim 1, wherein in each sub-frame, an interlaced scan for selecting a scan electrode group discontinuously is performed .