KR20070063741A - Method and apparatus for inspecting flat panel display - Google Patents

Abstract

An apparatus and a method for inspecting a flat display device are provided to automatically determine whether a gate driving circuit is defective, by forming test signal lines and test pads on a substrate and supplying gate control signals and gate driving voltages to the pads in an auto-probe type. A gate driving circuit, a test signal lines(35,36), and test pads(25) are formed on a substrate of a flat display panel. The gate driving circuit generates scan signals and the test signal lines are connected to input terminals of the gate driving circuit. The test pads are connected to the test signal lines. A plurality of probes(37) formed in a test module(32) are contacted with the test pads to drive the gate driving circuit, thereby inspecting the defect of the gate driving circuit. Herein, the test modules generate test signals and driving signals for driving the gate driving circuit.

Description

Inspection method and apparatus for flat panel display device {Method and Apparatus for Inspecting Flat Panel Display}

1 is a perspective view showing an active matrix type liquid crystal display device.

2 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a perspective view showing an inspection module and a flexible printed circuit film attached to the inspection module.

4 is a cross-sectional view showing the inspection module and the flexible printed circuit film shown in FIG.

5 is a view illustrating in detail the signal wiring group for inspection, the pad group, and the gate driver shown in FIG.

<Description of Symbols for Main Parts of Drawings>

11, 17: polarizing plate 12, 16, 24A: glass substrate

13 color filter 14 common electrode

15 liquid crystal layer 18 gate line

19: data line 20: thin film transistor

21 pixel electrode 22 color filter substrate

23 TFT array substrate 24 Liquid crystal display panel

25, 25A, 25B, 501a to 506d: Inspection pad

26, 26A, 26B, 601a ~ 606d: Signal wiring for inspection

27: timing controller 28: data driver

29A, 29B: gate driver 31: inspection circuit chip

32: inspection module 33: signal wiring formed on the FPC

34: FPC

35, 36: signal wiring formed on the substrate of the inspection module

S / R1 to S / Rn + 1: stages of the gate shift register

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flat panel display, and more particularly, to a method and apparatus for inspecting a flat panel display, which enables automatic inspection of a flat panel display having a gate driving circuit directly formed on a substrate together with a pixel array of a display area.

In today's information society, display elements are more important than ever as visual information transfer media. Cathode ray tubes or cathode ray tubes, which are currently mainstream, have problems with weight and volume.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode display (OLED). And most of them are commercially available and commercially available.

Liquid crystal display devices can meet the trend of light and short and short of electronic products and mass production is improving, and are rapidly replacing cathode ray tubes in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption, and secures the latest mass production technology. As a result of research and development, it is rapidly developing into larger size and higher resolution.

The active matrix type liquid crystal display device includes a color filter substrate 22 and a TFT array substrate 23 bonded together with the liquid crystal layer 15 interposed therebetween as shown in FIG. The liquid crystal display shown in FIG. 1 shows a pixel array of some screens.

In the color filter substrate 22, a black matrix, a color filter 13, and a common electrode 14, which are not shown, are formed on the rear surface of the upper glass substrate 12. The polarizing plate 11 is attached on the front surface of the upper glass substrate 12. The color filter 13 includes color filters of red (R), green (G), and blue (B) colors to allow color display by transmitting visible light in a specific wavelength band.

In the TFT array substrate 23, the data lines 19 and the gate lines 18 cross each other on the front surface of the lower glass substrate 16, and TFTs 20 are formed at the intersections thereof. In addition, a pixel electrode 21 is formed in a cell region between the data line 19 and the gate line 18 on the front surface of the lower glass substrate 16. The TFT 20 drives the pixel electrode 21 by switching the data transfer path between the data line 19 and the pixel electrode 21 in response to a gate pulse (or scan signal) from the gate line 18. . The polarizing plate 17 is attached to the rear surface of the TFT array substrate 23.

The liquid crystal layer 15 adjusts the amount of light transmitted through the TFT array substrate 23 by the electric field applied thereto.

The polarizers 11 and 17 attached to the color filter substrate 22 and the TFT substrate 23 transmit light polarized in either direction, and their polarization directions when the liquid crystal 15 is in the 90 ° TN mode. Are orthogonal to each other.

An alignment film (not shown) is formed on the liquid crystal facing surfaces of the color filter substrate 22 and the array TFT substrate 23.

A manufacturing process for manufacturing an active matrix liquid crystal display device is divided into a substrate cleaning, a substrate patterning process, an alignment film forming / rubbing process, a substrate bonding / liquid crystal injection process, a mounting process, an inspection process, a repair process, and the like.

The substrate cleaning process removes foreign substances contaminated on the surface of the substrate of the liquid crystal display with a cleaning liquid.

The substrate patterning process is divided into a patterning process of a color filter substrate and a patterning process of a TFT array substrate.

In the alignment film formation / rubbing process, an alignment film is applied to each of the color filter substrate and the TFT array substrate, and the alignment film is rubbed with a rubbing cloth or the like.

In the substrate bonding / liquid crystal injection process, a color filter substrate and a TFT array substrate are bonded together using a sealant, a liquid crystal and a spacer are injected through the liquid crystal injection hole, and then the liquid crystal injection hole is sealed.

In the mounting process, a tape carrier package (hereinafter referred to as "TCP") in which integrated circuits such as a gate drive integrated circuit and a data drive integrated circuit are mounted is connected to a pad portion on a substrate. Such a drive integrated circuit may be directly mounted on a substrate by a chip on glass (COG) method in addition to the tape automated bonding method using the aforementioned TCP. Recently, a technology in which drive integrated circuits are directly formed on the lower glass substrate 16 together with the pixel array has also been developed.

The inspection process includes inspection of the drive integrated circuit, signal wiring inspection of data lines and gate lines formed on the TFT array substrate, inspection performed after the pixel electrode is formed, and inspection performed after the substrate bonding / liquid crystal injection process. In the repair process, a repair process for a signal wiring defect and a TFT defect of a substrate determined to be repaired by an inspection process is performed. Non-repairable substrates are discarded in the inspection process.

When a drive integrated circuit is mounted on a panel substrate in the form of TCP or COG, an automatic inspection device for TCP and COG chips is commercially available. In contrast, a panel in which a drive integrated circuit is directly formed on a substrate has a problem in that automatic inspection is difficult because a pad structure necessary for automatic inspection has not been developed.

Accordingly, an object of the present invention is to provide a method and apparatus for inspecting a flat panel display device which enables automatic inspection of a flat panel display device in which a gate driving circuit is directly formed on a substrate together with a pixel array of a display area.

In order to achieve the above object, an inspection method of a flat panel display device according to an embodiment of the present invention generates a scan signal on the gate lines on a substrate of a flat panel display panel where a plurality of data lines and a plurality of gate lines cross each other. Forming inspection signal wirings connected to an input terminal of the gate driving circuit together with a gate driving circuit, and a plurality of inspection pads connected to the inspection signal wirings; Defect of the gate driving circuit by driving the gate driving circuit formed on the substrate by contacting the plurality of probes formed in the inspection module for generating the control signals and driving voltages necessary for driving the gate driving circuit to the inspection pads Checking whether or not.

The flat panel display panel includes a liquid crystal display device in which a plurality of liquid crystal cells are arranged in a matrix form.

The inspection method of the flat panel display device includes generating a common voltage to be supplied to common electrodes of liquid crystal cells by the inspection module and outputting the common voltage through some of the probes; The method may further include supplying the common voltage to the common electrode of the liquid crystal cells by contacting the probe supplied with the common voltage to some of the inspection pads.

The inspection pads are arranged side by side on the substrate, the probes of the inspection module are arranged side by side corresponding to the inspection pads and are in 1: 1 contact with the inspection pads.

An inspection apparatus of a flat panel display according to an exemplary embodiment of the present invention includes an input terminal of a gate driving circuit together with a gate driving circuit for crossing a plurality of data lines and a plurality of gate lines and generating a scan signal on the gate lines. A flat panel display panel including a plurality of first signal wires connected to the plurality of first signal wires and a plurality of test pads connected to the first signal wires; A plurality of second signal wires and an inspection module for generating control signals and driving voltages for driving the gate driving circuit through a plurality of probes connected through the second signal wires; The gate driving circuits formed on the substrate of the flat panel display panel are contacted with the inspection pads to check whether the gate driving circuits are defective.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 5.

2 shows a liquid crystal display device according to the present invention.

Referring to FIG. 2, in the liquid crystal display according to the exemplary embodiment of the present invention, a plurality of data lines D1 to Dm and a plurality of gate lines G1 to Gn cross each other, and liquid crystal cells Clc are formed at an intersection thereof. And a data driver 28, gate drivers 29A and 29B, and a timing controller 27 for driving the liquid crystal display panel 24.

In the liquid crystal display panel 24, liquid crystal is injected between two glass substrates, and the data lines D1 to Dm and the gate lines G1 to Gn are orthogonal to each other on the lower glass substrate. The TFT formed at the intersection of the data lines D1 to Dm and the gate lines G1 to Gn receives data from the data lines D1 to Dm in response to a scan pulse from the gate lines G1 to Gn. Supply to the liquid crystal cell (Clc). For this purpose, the gate electrode of the TFT is connected to the gate lines G1 to Gn, and the source electrode is connected to the data lines D1 to Dm. The drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc. In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 24 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate lines G1 to Gn, or may be formed between the liquid crystal cell Clc and a separate common line.

The timing controller 27 controls the operation timing of the gate drivers 29A and 29B by using the vertical / horizontal synchronization signals V and H and the pixel clock, and the data driver 28 of the gate control signal GDC. A data control signal DDC is generated for controlling the operation timing and the polarity of the data. The gate control signal GDC includes all control signals necessary for the operation of the shift register included in the gate driver, for example, a start voltage VST, a shift clock CLK, a driving control clock GPW, and the like.

The data driver 28 stores a shift line, a register for temporarily storing digital video data RGB from the timing controller 27, and stores data one line by one line in response to a clock signal from the shift register. A latch for outputting data at the same time, a digital / analog converter for selecting an analog positive / negative gamma compensation voltage corresponding to the digital data value from the latch, and a data line to which a positive / negative gamma compensation voltage is supplied. And a multiplexer for selecting D1 to Dm, and an output buffer connected between the multiplexer and the data lines D1 to Dm. The data driver 28 receives the digital video data RGB, converts the digital video data RGB into analog positive / negative gamma compensation voltages, and converts the analog positive / negative gamma compensation voltages into pixel voltages. As a result, the data line is supplied to the data lines D1 to Dm of the liquid crystal display panel 24 under the control of the timing controller 27. The data driver 28 is mounted on TCP to be bonded to an anisotropic conductive film (ACF) on the lower glass substrate of the liquid crystal display panel 24, or to an ACF on the lower glass substrate in the form of COG. It may be directly formed on the lower glass substrate.

The gate drivers 29A and 29B are separated on both sides of the lower glass substrate of the liquid crystal display panel 24, and the data lines D1 to Dm, the gate lines G1 to Gn, TFTs, and pixel electrodes are separated from each other. Together is formed directly on the lower glass substrate. The gate drivers 23A and 23B include a shift register that is simultaneously driven in response to the gate control signal GDC from the timing controller 27 to sequentially generate scan pulses (or gate pulses). The TFTs connected to the gate lines G1 to Gn by the scan pulses generated from the gate drivers 29A and 29B are turned on, so that the pixel voltage of the data, that is, the analog gamma compensation voltage, is Liquid crystal cells Clc of one horizontal line to be supplied are sequentially selected. Data generated from the data driver 28 are supplied to the liquid crystal cells Clc of one horizontal line selected by being synchronized with the scan pulse.

On the other hand, the drive voltages with the increased swing width are supplied to the gate drivers 29A and 29B by a level shift circuit (not shown).

In order to inspect the gate drivers 29A and 29B of the liquid crystal display using an auto-probe system, pad groups having a plurality of pads arranged side by side on a lower glass substrate of the liquid crystal display panel 24. The test signal wiring groups 26A and 26B connected to the input terminals 25A and 26B, the pad groups 25A and 25B, and the gate drivers 23A and 23B and including a plurality of signal wirings are formed. The pad groups 25A and 26B have gate drivers through an inspection module 32 and a flexible printed circuit film 34 (hereinafter, referred to as “FPC”) 34 as shown in FIGS. 3 and 4. The inspection gate control signal and driving voltages including the shift clocks of 23A and 23B, and a common voltage to be supplied to the common electrode of the liquid crystal cells Clc are supplied.

3 and 4, the test module 32 includes a test circuit chip 31 formed on a substrate, signal wires 35 and 36, and probes 37. The inspection circuit chip 31 includes a timing signal generator and a level shifter to generate the inspection gate control signal and the gate driving voltages.

The test circuit chip 31 is supplied to the probes 37 through the signal wires 35 and 36.

The probes 37 are attached to the inspection module 32 side by side so as to be connected 1: 1 with the signal wires 35 and 36. Further, the probes 37 are attached to the inspection module 32 at the same pitch as the pads of the pad groups 25, 25A, and 25B formed on the lower glass substrate of the liquid crystal display panel 24. The probes 35 are electrically connected to the pads of the pad groups 25A and 25B, so that the test gate control signals, the gate driving voltages, and the common voltage are applied to the pads of the pad groups 25, 25A and 25B. And so on.

The inspection module 32 is attached to the FPC (34) by the ACF. The FPC 34 has signal wires 33 formed thereon, and the signal wires 33 connect the output pins of the test circuit chip 31 and the signal wires on the test module 32 to 1: 1.

In the inspection process of the gate drivers 29A and 29B, the inspection module 32 to which the probes 37 are attached and the FPC 34 are mounted on a jig (not shown), and mechanically or manually descend to lower the liquid crystal display panel. The pad groups may be electrically connected to the pads of the pad groups 25A and 25B formed on the lower glass substrate 24A of the 24 to control gate control signals, gate driving voltages, and common voltage Vcom. Supply to (25, 25A, 25B). Therefore, in the inspection process of the gate drivers 29A and 29B, the inspection gate control signals and the gate driving voltages generated from the inspection module 32 are supplied to the input terminals of the gate drivers 29A and 29B to provide a gate. The driving units 29A and 29B are normally driven to sequentially supply scan pulses to the gate lines G1 to Gn. In addition, the common voltage Vcom generated from the inspection module 32 is formed on the lower glass substrate 24A and is electrically connected to the common electrode of the liquid crystal cells Clc formed on the upper glass substrate. It is supplied to the common electrode of the liquid crystal cells Clc through a Au conductive ball mixed in a dot or a sealant.

In the meantime, the test data voltage is supplied to the data lines D1 to Dm in the inspection process of the gate drivers 29A and 29B from a test board (not shown). Therefore, the inspector contacts the probes 37 of the inspection module 32 with the pad groups 25A and 25B of the liquid crystal display panel 24 and performs defects of the gate drivers 29A and 29B through visual or electrical inspection. Whether the inspection circuit chip 31 and the FPC 34 are defective can be easily known.

FIG. 5 is a view showing in detail any one of the pad groups 25A and 25B formed on the lower glass substrate 24A of the liquid crystal display panel 24 and any one of the test signal wiring groups 26A and 26B. In FIG. 5, "S / R1 to S / Rn + 1" represents n + 1 stages for sequentially shifting the start voltage Vst in the gate shift registers of the gate drivers 25A and 25B.

Referring to FIG. 5, the stages S / R1 and S / Rn + 1 of the gate shift register and the probes 37 of the inspection module 32 are disposed on the lower glass substrate 24A of the liquid crystal display panel 24. Test signal wirings 601 to 606d connected between the pads 501 to 506d and the input terminals of the stages S / R1 to S / Rn + 1 and the pads 501a to 506d. ) Is formed.

In FIG. 5, "Vst" is a start voltage for generating the first scan pulse of the gate drivers 29A and 29B, and "CLK1 to CLK4, GPW1 to GPW4" are stages S / R1 to S / Rn +. It is a shift clock input to the clock terminals of 1) to instruct the scan pulse shift and output timing. In addition, "VSS" denotes a base voltage or a low potential power supply voltage, "VDD" denotes a high potential voltage voltage, and "Vcom" denotes a common voltage applied to the common electrode of the liquid crystal cells Clc. The inspection gate control signals, the gate driving voltage, the common voltage, and the like are applied to the stages S / R1 to S / Rn + 1 of the gate shift register through the probes 37. In FIG. 5, “o” 507 is an electrostatic protection device. The electrostatic protection device electrically separates the two ends when static electricity is not generated, but turns on when static electricity is generated to form a current path between both ends, thereby discharging the overvoltage and overcurrent momentarily generated by static electricity. Do it.

Among the stages S / R1 to S / Rn + 1, one or more dummy stages S / Rn + 1 are included. The dummy stage S / Rn + 1 serves to replace the defective stage when a defective stage occurs.

The gate shift register circuit formed directly on the lower glass substrate of the liquid crystal display panel 24 is disclosed in Korean Patent Application Nos. 2005-0053124, 2005-0056537, 2005-0058454, 2005- filed by the applicant of the present application. It may be implemented in circuits such as 0058142, 05-058734, 2005-0058108, and the like.

Meanwhile, in the detailed description, the liquid crystal display device has been described, but the technical idea of the present invention is not limited to the liquid crystal display device. Applicable.

As described above, the method and apparatus for inspecting a flat panel display according to the present invention form pads and signal wirings for inspecting a gate driving circuit directly formed on a substrate of a flat panel display panel on the substrate, It is possible to automatically determine whether the gate driving circuit is defective by supplying a gate control signal, a gate driving voltage, and the like by the auto probe method.

Those skilled in the art will appreciate that various changes and modifications can be made in the scope of the present invention without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

Inspection signal wiring connected to an input terminal of the gate driving circuit together with a gate driving circuit for generating scan signals to the gate lines on a substrate of a flat panel panel where a plurality of data lines and a plurality of gate lines intersect. And a plurality of inspection pads connected to the inspection signal wires; Defect of the gate driving circuit by driving the gate driving circuit formed on the substrate by contacting the plurality of probes formed in the inspection module for generating the control signals and driving voltages necessary for driving the gate driving circuit to the inspection pads Inspection method for a flat panel display device comprising the step of inspecting whether or not. The method of claim 1, The flat panel display panel includes a liquid crystal display device in which a plurality of liquid crystal cells are arranged in a matrix form. The method of claim 2, Generating a common voltage to be supplied to the common electrodes of the liquid crystal cells by the inspection module and outputting the common voltage through some of the probes; And supplying the common voltage to the common electrode of the liquid crystal cells by contacting the probe supplied with the common voltage to some of the inspection pads. The method of claim 1, The inspection pads are disposed side by side on the substrate; The probes of the inspection module are arranged in parallel with the inspection pads and are in contact with the inspection pads in a 1: 1 manner. A plurality of first signal wires connected to an input terminal of the gate driving circuit together with a gate driving circuit for crossing a plurality of data lines and a plurality of gate lines and generating a scan signal on the gate lines, and the first A flat panel display panel having a plurality of inspection pads connected to one signal wire; An inspection module configured to generate control signals and driving voltages necessary for driving the gate driving circuit through a plurality of second signal wires and a plurality of probes connected through the second signal wires; And inspecting whether the gate driving circuit is defective by driving the gate driving circuits formed on the substrate of the flat panel display panel by contacting the plurality of probes with the inspection pads. The method of claim 5, The flat panel display panel includes a liquid crystal display device having a plurality of liquid crystal cells arranged in a matrix form. The method of claim 6, The inspection module, Generating a common voltage to be supplied to the common electrodes of the liquid crystal cells and outputting the same through some of the probes; And inspecting the probe supplied with the common voltage to some of the inspection pads to supply the common voltage to the common electrodes of the liquid crystal cells. The method of claim 5, The inspection pads are disposed side by side on the substrate; And probes of the inspection module arranged in parallel with the inspection pads and contacting the inspection pads in a 1: 1 manner.

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