KR20120075096A - Liquid crystal display device and inspection method thereof - Google Patents

Abstract

A liquid crystal display and an inspection method thereof are disclosed.
According to an exemplary embodiment of the present invention, a liquid crystal display device includes a display area in which a plurality of signal wires are formed to display an image, a non-display area positioned at an edge of the display area, and a plurality of driving devices for driving the plurality of signal wires. A substrate divided into a circuit region in which a chip is formed, a flexible printed circuit that provides a signal and a voltage to a plurality of driving chips located in the circuit region, and the plurality of driving chips electrically connected to each other on the circuit region. Connection wirings for supplying signals and voltages provided from the flexible printed circuit to the plurality of driving chips, and first edges formed at upper edges of the non-display area of the substrate to provide test signals to the plurality of signal wirings. It is formed in the test pad and the circuit area of the substrate between the plurality of driving chips and a plurality of signal wirings PL comprises a second inspection pad for providing a test signal to the link, the number of driving chips comprises a plurality of transistors of the second inspection pad and electrically connected to the link portion for.

Description

Liquid crystal display device and inspection method

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and an inspection method thereof capable of inspecting whether a data link line is defective.

In today's information society, display elements are more important than ever as visual information transfer media. Cathode ray tubes or cathode ray tubes, which are currently mainstream, have problems with weight and volume. Many kinds of flat panel displays have been developed to overcome the limitations of the cathode ray tube.

The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electroluminescence (EL). Most of these are commercially available and commercially available.

Liquid crystal display devices can meet the trend of light and short and short of electronic products and mass production is improving, and are rapidly replacing cathode ray tubes in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell by using a thin film transistor (TFT) has advantages of high image quality and low power consumption. It is developing rapidly.

A manufacturing process for manufacturing an active matrix liquid crystal display device is divided into a substrate cleaning, a substrate patterning process, an alignment film forming / rubbing process, a substrate bonding / liquid crystal injection process, a mounting process, an inspection process, a repair process, and the like.

In the substrate cleaning process, foreign substances contaminated on the substrate surface of the liquid crystal display device are removed with the cleaning liquid.

In the substrate patterning process, the upper substrate is patterned and the lower substrate is patterned. A color filter, a common electrode, a black matrix, and the like are formed on the upper substrate. A signal line such as a data line and a gate line is formed on the lower substrate, a TFT is formed at an intersection of the data line and the gate line, and a pixel electrode connected to the TFT is formed in the pixel region between the data line and the gate line.

In the alignment film formation / rubbing process, an alignment film is applied to each of the upper substrate and the lower substrate, and the alignment film is rubbed with a rubbing cloth or the like.

In the substrate bonding / liquid crystal injection process, the upper substrate and the lower substrate are bonded using a real material, the liquid crystal and the spacer are injected through the liquid crystal injection hole, and then the liquid crystal injection hole is sealed.

In the liquid crystal panel mounting process, a tape carrier package (hereinafter referred to as "TCP") in which integrated circuits such as a gate drive integrated circuit and a data drive integrated circuit are mounted is connected to a pad portion on a substrate. Such a drive integrated circuit may be directly mounted on a substrate by a chip on glass (COG) method in addition to the tape automated bonding method using the aforementioned TCP.

The inspection process includes an electrical lighting test performed after various signal wirings and pixel electrodes are formed on the lower substrate, and a defect inspection of each pixel.

The repair process restores the substrate that is determined to be repairable by the inspection process. Meanwhile, defective substrates that cannot be repaired in the inspection process are discarded.

In the inspection process, defect inspection of the signal wire and the pixel electrode formed on the lower substrate is performed by using the auto probe device. At this time, the probe pin of the auto probe device is directly connected to the pad portion formed on the lower substrate to provide an inspection signal to the pad portion to inspect the defects of the signal wiring and the pixel electrode formed on the lower substrate.

In the case of the COG type liquid crystal display, an inspection transistor capable of contacting the pin on one side of the lower substrate is added to the gate and data pad portions in the inspection process, and the inspection transistor is added. . Since the driving chip is mounted on the lower substrate, the inspection transistor is positioned in an area where the driving chip is not mounted. In more detail, the inspection transistor is positioned at an area opposite to the driving chip or at one edge of the lower substrate.

The inspection transistor is electrically connected to the probe pin of the auto probe device in the inspection process. In this case, the inspection transistor is electrically connected to a signal line formed on the lower substrate. Thus, the test signal provided from the auto probe equipment is provided to signal wires formed on the lower substrate through the test transistor. As a result, defect inspection of the signal wires formed on the lower substrate is performed.

In this case, the test signal from the test transistor is applied to the signal wires through the test transistor, so that the test chip and the signal wires positioned on the opposite side of the test transistor, in particular, the data link part between the data line, is inspected. can not do. Therefore, a research method for inspecting whether a data link part is defective in a COG type liquid crystal display device should be studied.

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device and a method of inspecting the same, in which a test transistor is added to a data link portion between a driving chip and a data line to perform defect inspection on the data link portion as well as signal wiring arranged in an active region. Has its purpose.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a display area in which a plurality of signal wires are formed to display an image, a non-display area positioned at an edge of the display area, and a plurality of driving devices for driving the plurality of signal wires. A substrate divided into a circuit region in which a chip is formed, a flexible printed circuit that provides a signal and a voltage to a plurality of driving chips located in the circuit region, and the plurality of driving chips electrically connected to each other on the circuit region. Connection wirings for supplying signals and voltages provided from the flexible printed circuit to the plurality of driving chips, and first edges formed at upper edges of the non-display area of the substrate to provide test signals to the plurality of signal wirings. It is formed in the test pad and the circuit area of the substrate between the plurality of driving chips and a plurality of signal wirings PL comprises a second inspection pad for providing a test signal to the link, the number of driving chips comprises a plurality of transistors of the second inspection pad and electrically connected to the link portion for.

An inspection method of an LCD according to an exemplary embodiment of the present invention includes a display area in which a plurality of signal wires are formed to display an image, a non-display area positioned at an edge of the display area, and a plurality of signal wires. A substrate divided into a circuit region in which a plurality of driving chips including transistors are formed; a flexible printed circuit providing a signal and a voltage to a plurality of driving chips located in the circuit region; A plurality of signals formed at upper edges of the non-display area of the substrate and first connection wires for allowing the driving chips of the plurality to be electrically connected to each other and to supply signals and voltages provided from the flexible printed circuit to the plurality of driving chips. A plurality of first pads for providing a test signal with wirings and formed in a circuit area of the substrate; An inspection method of an LCD apparatus including a second inspection pad electrically connected to the plurality of transistors and providing a test signal to a link unit positioned between a driving chip and a plurality of signal wires. Contacting the pins with the first and second test pads to provide a test signal to the first and second test pads; and applying a test signal provided to the first test pad to the plurality of signal wires. Inspecting whether the plurality of signal wires are defective or not, and supplying a test signal provided to the second test pad to the plurality of transistors to turn on the plurality of transistors to turn on the plurality of transistors. And providing a test signal to check whether the link unit is defective.

In the liquid crystal display according to the exemplary embodiment of the present invention, a test transistor may be added to the data link unit to perform defect inspection on the data link unit.

1 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 2 is a detailed view of A of FIG. 1.
3 is a view showing B of FIG. 1 in detail.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a display area 101 in which a plurality of gate lines GL and a plurality of data lines DL are arranged to display an image, and the display. Non-display area 103 surrounding the edge of the area 101 and the first to fourth located at the outermost portion of the non-display area 103 to drive the plurality of data lines DL and the gate line GL. The substrate 100 is divided into a circuit region 105 in which the driving chips 110a to 110d are arranged.

The substrate 100 is provided with a first connection wire 150 for electrically connecting the first to fourth driving chips 110a to 110d. In this case, the second and third driving chips 110b and 110c of the first to fourth driving chips 110a to 110d directly receive various signals and voltages from the flexible printed circuit FPC 140. It is provided.

The second driving chip 110b provides the various signals and voltages to the first driving chip 110a directly connected through the first connection line 150. The third driving chip 110c also provides the various signals and voltages to the fourth driving chip 110d integrated and connected through the first connection line 150.

The first inspection pad 120 is provided at one edge of the upper side of the substrate 100 to provide an inspection signal to the gate line GL and the data line DL positioned on the substrate 100.

In addition, a second test pad providing a test signal to a circuit link portion 105 positioned below the substrate 100 to a data link portion positioned between the driving chips 110a to 110d and the data line DL. 130 is formed.

Each of the first and second test pads 120 and 130 is electrically connected to a probe pin of an auto probe device (not shown) during the test process to receive a test signal from the auto probe device.

The test signal provided to the first test pad 120 may be connected to the plurality of non-display areas 103 of the substrate 100 through connection wires (not shown) and transistors (not shown). Are supplied to the gate line GL and the data line DL.

That is, an inspection signal is applied to the upper portion of the substrate 100 through the first inspection pad 120 so that the inspection signal is transmitted to the gate line GL and the data line DL positioned on the substrate 100. It is supplied and performs a defect test of disconnection.

The second inspection pad 130 is formed at each side of each of the first to fourth driving chips 110a to 110d to provide an inspection signal to the first to fourth driving chips 110a to 110d.

For convenience, the second inspection pad 130 is illustrated only on the side surfaces of the first and fourth driving chips 110a and 110d among the first to fourth driving chips 110a to 110d.

The second inspection pad 130 may include an enable pad 130a for applying an enable signal to the driving chips 110a to 110d, and first and second data pads for providing first and second data signals. 130b and 130c.

A detailed description of the second inspection pad 130 and the driving chip 110a will be described later with reference to FIG. 2.

FIG. 2 is a detailed view of A of FIG. 1.

1 and 2, the first driving chip 110a includes a plurality of output pads 170, a first voltage input terminal 180b electrically connected through a first connection wire 150, and A first voltage output terminal 180a, a second voltage input terminal 190b and a second voltage output terminal 190a electrically connected through the first connection line 150 are included.

The first voltage input terminal 180b supplies the low potential voltage VSS provided from the second driving chip 110b to the first voltage output terminal 180a through the first connection line 150. The second voltage input terminal 190b supplies the high potential voltage VDD provided from the second driving chip 110b to the second voltage output terminal 190a through the first connection line 150.

In addition, the first driving chip 110a may be electrically connected to the enable wiring 160a electrically connected to the enable pad 130a of the second inspection pad 130 and the first data pad 130b. The first data wire 160b connected to each other and the second data wire 160c electrically connected to the second data pad 130c are formed.

The enable wiring 160a and the first and second data wirings 160b and 160c constitute a second connection wiring 160.

In addition, the first driving chip 110a includes a plurality of transistors formed to correspond to the number of the plurality of output pads 170 between one side of the plurality of output pads 170 and the second connection wire 160. (TR) is further included. In this case, the other side of the plurality of output pads 170 is electrically connected to the data link line DLL electrically connected to the data line DL.

The odd-numbered transistor TR of the plurality of transistors TR is connected to the first terminal connected to the enable wiring 160a and the second terminal and first data wiring 160b connected to the odd-numbered output pad 170. It is comprised with the 3rd terminal connected. The even-numbered transistor TR of the plurality of transistors TR is connected to the first terminal connected to the enable line 160a and the second terminal and second data line 160c connected to the even-numbered output pad 170. It is comprised with the 3rd terminal connected.

The enable signal provided through the enable pad 130a of the second test pad 130 is supplied to the enable wiring 160a and replaces the first data pad 130b of the second test pad 130. The first data signal provided through the first data line 160b is supplied, and the second data signal provided through the second data pad 130c of the third test pad 130 is connected to the second data line 160c. Is supplied.

When an enable signal is supplied to the enable wiring 160a, the plurality of transistors TR electrically connected to the enable wiring 160a is turned on. When the plurality of transistors TR are turned on, a first data signal is supplied to an odd-numbered output pad 170 through an odd-numbered transistor TR of the plurality of transistors TR. At the same time, a second data signal is supplied to the even-numbered output pad 170 through the even-numbered transistor TR among the plurality of transistors TR.

Accordingly, a first data signal is supplied to the data link line DLL electrically connected to the odd-numbered output pad 170 and to the data link line DLL electrically connected to the even-numbered output pad 170. The second data signal is supplied.

Therefore, as a data signal is supplied to the data link line DLL, a defect inspection relating to disconnection of the data link line DLL may be performed.

3 is a view showing B of FIG. 1 in detail.

As shown in FIGS. 1 and 3, when the inspection process for the substrate 100 is completed, the enable wiring 160a formed on each of the first to fourth driving chips 110a to 110d is mutually connected. The modification design is made to be electrically connected. The modified design of the enable wiring 160a may turn off the plurality of transistors TR formed on the first to fourth driving chips 110a to 110d to prevent interference between signals when driving the liquid crystal display. to turn off.

When the liquid crystal display is driven, a gate low voltage vgl is applied to the modified designed enable line 160a through the flexible printed circuit 140. When the gate low voltage vgl is supplied to the enable wiring 160a, the gate low voltage vgl is supplied to a plurality of transistors (TR in FIG. 2) electrically connected to the enable wiring 160a. . At the same time, the gate low voltage vgl is also supplied to the enable pad 130a electrically connected to the enable wiring 160a.

As the gate low voltage vgl is supplied to the plurality of transistors TR, the plurality of transistors TR are turned off. Therefore, when the liquid crystal display is driven, the plurality of transistors TR maintains a turn-off state.

As described above, the plurality of transistors TR are turned on by an enable signal supplied by the enable pad 130a and the enable wiring 160a during the inspection process. The inspection signal is provided to the data link line DLL electrically connected to the TR so that the defect inspection of the data link line DLL can be performed. In addition, the plurality of transistors TR are turned off by the gate low voltage vgl when the liquid crystal display is driven to prevent interference between signals.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

100: substrate 101: display area
103: non-display area 105: circuit area
110a to 110d: first to fourth driving chips 120: first inspection pad
130: 2nd test pad 130a: Enable pad
130b: first data pad 130c: second data pad
140: flexible printed circuit 150: first connection wiring
160: second connection wiring 160a: enable wiring
160b: first data wiring 160c: second data wiring
170: output pad 180a: first voltage output terminal
180b: first voltage input terminal 190a: second voltage input terminal
190b: second voltage output terminal

Claims (9)

A substrate divided into a display area in which a plurality of signal wires are formed to display an image, a non-display area positioned at an edge of the display area, and a circuit area in which a plurality of driving chips for driving the plurality of signal wires are formed;
A flexible printed circuit providing a signal and a voltage to a plurality of driving chips located in the circuit area;
A connection line positioned on the circuit area to electrically connect the plurality of driving chips to each other and to supply signals and voltages provided from the flexible printed circuit to the plurality of driving chips;
A first inspection pad formed at an upper edge of the non-display area of the substrate to provide a test signal to the plurality of signal wires; And
And a second inspection pad formed in a circuit area of the substrate and configured to provide an inspection signal to a link unit positioned between the plurality of driving chips and the plurality of signal wires.
The plurality of driving chips may include a plurality of transistors electrically connected to the second test pad and the link unit. The method according to claim 1,
The second test pad may include an enable pad for applying an enable signal to a plurality of transistors of each of the plurality of driving chips, a first data pad for providing a first data signal to an odd-numbered transistor among the plurality of transistors; And a second data pad configured to provide a second data signal to even-numbered transistors of the plurality of transistors. The method of claim 2,
Each of the plurality of driving chips includes an enable wire electrically connected to the enable pad, a first data wire electrically connected to the first data pad, and a second data wire electrically connected to the second data pad. Liquid crystal display device further comprising. The method according to claim 1,
And the plurality of transistors are enabled and turned on by a test signal provided from the second test pad during a test process. The method according to claim 1,
And the flexible circuit board supplies a gate low voltage to the second inspection pad after the inspection process is completed. 6. The method of claim 5,
And a plurality of transistors are turned off when the gate low voltage is supplied to the second test pad. A display area in which a plurality of signal wires are formed to display an image, a non-display area positioned at an edge of the display area, and a circuit area in which a plurality of driving chips including a plurality of transistors are formed to drive the plurality of signal wires. A flexible printed circuit providing a signal and a voltage to a separated substrate, a plurality of driving chips located in the circuit region, and a plurality of driving chips disposed on the circuit region to electrically connect the plurality of driving chips to each other. A first connection wire for supplying signals and voltages provided from the plurality of driving chips to the plurality of driving chips, a first inspection pad formed at an upper edge of the non-display area of the substrate to provide an inspection signal to the plurality of signal wires; A link formed in a circuit area of the substrate and positioned between the plurality of driving chips and the plurality of signal wires To provide a test signal in a test method of a liquid crystal display device comprising a second inspection pad electrically connected to the plurality of said transistors,
Contacting the probe pins of an auto probe device with the first and second test pads to provide test signals to the first and second test pads;
Inspecting whether the plurality of signal wires are defective by applying a test signal provided to the first test pad to the plurality of signal wires; And
Supplying a test signal provided to the second test pad to the plurality of transistors to turn on the plurality of transistors to provide the test signal to the link unit to inspect whether the link unit is defective Inspection method for a liquid crystal display device comprising a. The method of claim 7, wherein
And the flexible circuit board supplies a gate low voltage to the second inspection pad after the inspection process is completed. The method of claim 8,
And when the gate low voltage is supplied to the second test pad, the plurality of transistors electrically connected to the second test pad are turned off.

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