KR20070057325A - Display substrate and method for testing the same - Google Patents

Abstract

A display substrate and a method for testing the same are provided to prevent detection error due to pin contact defect during a gross test, by forming testing part in a static electricity diode part to apply test signals to gate. A gate circuit part(110) is formed at first ends of gate lines to apply gate signals to the gate lines. A data pad part(120) is formed at first ends of data lines to apply data signals to the data lines. A static electricity diode part(130) is connected to the data pad part to discharge static electricity flowed into the data pad part. A testing part(140) is electrically connected to the static electricity diode part to apply test signals to the data lines.

Description

DISPLAY SUBSTRATE AND METHOD FOR TESTING THE SAME}

1 is a plan view of a display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the gate circuit shown in FIG. 1.

3 is a partially enlarged view of the array substrate illustrated in FIG. 1.

FIG. 4 is an equivalent circuit diagram of the display panel shown in FIG. 1.

5 is a plan view of a display panel according to another exemplary embodiment of the present invention.

FIG. 6 is a partially enlarged view of the array substrate illustrated in FIG. 5.

FIG. 7 is an equivalent circuit diagram of the display panel shown in FIG. 5.

8 is a schematic perspective view of an inspection apparatus for detecting a failure of a display panel according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: array substrate 200: color filter substrate

110: gate circuit portion 120; Data pad part

130: electrostatic diode unit 140: inspection unit

The present invention relates to a display substrate and an inspection method thereof, and more particularly, to a display substrate and an inspection method thereof for improving the defect detection power.

In general, the liquid crystal display panel module includes a liquid crystal display panel and a driving device electrically connected to the liquid crystal display panel to drive the liquid crystal display panel.

The liquid crystal display panel includes an array substrate, an upper substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the upper substrate. In the manufacturing process of the liquid crystal display panel, defects caused by particles are the biggest factor in the decrease in manufacturing yield. In particular, the OPEN and SHORT defects of wiring due to particles are a major cause of direct yield reduction.

In the inspection method for detecting a wiring defect, an array test is performed by applying an electrical signal to wirings in a manufacturing process of the array substrate. Next, after the liquid crystal is injected into the display panel in which the array substrate and the color filter substrate are combined, a visual inspection is performed by providing an electrical signal and a backlight (or front light).

Before mounting the driving device for driving the liquid crystal display panel, a GROSS test for a more detailed inspection, that is, a pixel defect and a wiring defect is performed. After the gross inspection, a driving device is mounted on the liquid crystal display panel in which no defect is detected, thereby completing the liquid crystal display panel module.

In general, the gross inspection contacts the pins of the inspection apparatus with pads formed on the liquid crystal display panel, and transmits the inspection signal to the liquid crystal display panel through the pins to perform the inspection. However, there is a problem that the pins and the pads are not contacted correctly, and there is a problem in that accurate inspection results cannot be obtained due to such contact failure.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display substrate for improving defect detection power.

Another object of the present invention is to provide a method for inspecting the display substrate.

The display substrate according to the embodiment for realizing the object of the present invention includes a gate circuit portion, a data pad portion, an electrostatic diode portion, and an inspection portion. The gate circuit part is formed at one end of the gate lines to apply a signal to the gate lines. The data pad part is formed at one end of the data wires to apply a data signal to the data wires. The electrostatic diode unit is connected to the data pad unit to dissipate static electricity introduced through the data pad unit. The test unit is electrically connected to the electrostatic diode unit to apply a test signal to the data lines.

A plurality of pixel units, a gate circuit formed at one end of the gate lines to apply a signal to the gate lines, and a data input pad formed at one end of the data lines, according to another embodiment of the present invention. And a test unit connected to the data input pads and an electrostatic diode connected to the data input pads, the method comprising: detecting a first failure by applying a first test signal to the data input pads; And detecting a second failure by applying the second inspection signal to the inspection unit.

According to such a display substrate and its inspection method, it is possible to improve defect detection power such as wiring defects and pixel defects in the gross inspection process.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view of a display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the gate circuit shown in FIG. 1.

1 and 2, the display panel includes an array substrate 100, a color filter substrate 200 coupled to the array substrate 100, and the array substrate 100 and a color filter substrate ( It includes a liquid crystal layer (not shown) interposed between the 200.

The array substrate 100 includes a display area DA, a first peripheral area PA1 and a second peripheral area PA2 adjacent to the display area DA.

In the display area DA, gate lines GL extending in a first direction, data lines DL extending in a second direction crossing the first direction, and the gate lines GL and the data. The plurality of pixel portions P defined by the wirings DL are included. In each pixel portion P, a switching element TFT, a pixel electrode of a liquid crystal capacitor CLC, and a common electrode of a storage capacitor CST are formed.

A gate circuit part 110 is formed in the first peripheral area PA1 to be connected to one end of the gate lines GL to apply gate signals to the gate lines GL. As illustrated in FIG. 2, the gate circuit unit 110 is integrated in the first peripheral area PA as a shift register in which a plurality of stages are cascaded. The gate circuit unit 110 includes input terminals 111 to which a plurality of gate control signals are input.

Referring to FIG. 2, the shift register is composed of n stages SRC1, SRC2, ..., SRCn and a dummy stage SRCd, and includes a plurality of stages SRC1, SRC2, ..., SRCn, SRCd) are cascaded. Each stage is formed by integrating a plurality of thin film transistors, and has an input terminal and an output terminal.

The input terminals include an input terminal IN through which a vertical start signal STV or a previous stage output signal is input, and a control terminal CL through which an output signal of a next stage or a dummy stage SRCd is input. And a clock terminal CK to which the first clock signal CKV or the second clock signal CKVB is input, and a voltage terminal VSS to which the off voltage VSS is applied. The first clock signal CKV is provided to odd-numbered stages, and the second clock signal CKVB is provided to even-numbered stages. The output terminal is connected to the corresponding gate lines GL to output a gate signal.

The data pad unit 120, the electrostatic diode unit 130, and the inspection unit 140 are formed in the second peripheral area PA2.

The data pad unit 120 includes data input pads 121 for applying data signals to the data lines DL. The data input pads 121 are in electrical contact with output terminals of a source driving chip to receive data signals output from the source driving chip. The data input pads 121 are grouped into predetermined groups corresponding to the number of source driving chips mounted on the display panel.

The electrostatic diode unit 130 is connected to the data input pad 121 to disperse static electricity introduced from the data input pads 121. Accordingly, the pixel portion P is prevented from being damaged from the static electricity.

The inspection unit 140 includes an inspection wire 141 electrically connected to the electrostatic diode unit 130 and an inspection pad 142 that applies an inspection signal to the inspection wire 141. Although not shown, the test wiring 141 is electrically connected to a common wiring of the storage capacitor formed in the display area DA. Therefore, when the source driving chip is mounted, the test pad 141 may be floated or used as a voltage pad to which the storage common voltage is applied.

The inspection unit 140 applies the inspection signal to the data lines DL through the electrostatic diode unit 130. That is, the inspection unit 140 applies the inspection signal substantially the same to the data lines DL in a 1D inspection manner.

3 is a partially enlarged view of the array substrate illustrated in FIG. 1.

1 and 3, the array substrate includes a display area DA and a first peripheral area PA1 adjacent to the display area DA.

A plurality of gate lines GL1 and a plurality of data lines DL1, DL2, and DL3 are formed in the display area DA. A plurality of pixel portions P are defined by the gate lines GL1 and the data lines DL1, DL2, and DL3. Each pixel portion P1 includes a switching element TFT1 and the switching element TFT1. Is connected to the pixel electrode 106.

In detail, the switching element TFT1 includes a gate electrode 101 connected to a gate line GL1, a source electrode 103 connected to a data line DL1, and a drain electrode 104 connected to the pixel electrode 106. It includes. The switching element TFT1 includes a channel portion 102 interposed between the gate electrode 101 and the source and drain electrodes 103 and 104.

The electrostatic diode unit 130 and the inspection unit 140 are formed in the first peripheral area PA1. The electrostatic diode unit 130 includes a plurality of diodes D1, D2, D3, .. electrically connected to the data input pads 121, 122, 123,... The inspection unit 140 includes an inspection wire 141 electrically connected to the plurality of diodes D1, D2, D3... And an inspection pad 142 formed at one end of the inspection wire 141.

In detail, each diode D1 includes a gate electrode 131 and a source electrode 133 connected to the inspection line 141 in common, and a drain electrode 134 electrically connected to the data line DL1. .

The source electrode 133 extends from the inspection wiring 141, and the gate electrode 131 is electrically connected to the inspection wiring 141 through a connection pattern 135. The drain electrode 134 is electrically connected to the data line 1 through the connection pattern 135. The diode D1 includes a channel portion 132 interposed between the gate electrode 131 and the source and drain electrodes 133 and 134. The connection pattern 135 is a conductive pattern formed on the same layer as the pixel electrode 106.

FIG. 4 is an equivalent circuit diagram of the display panel shown in FIG. 1.

1 and 4, the display panel includes a plurality of gate lines GL1, a plurality of data lines DL1, DL2, DL3, .., a plurality of pixel units P1, and diodes ( D1, D2, D3, ...) and the inspection unit 140.

Each pixel portion P1 includes a switching element TFT, a liquid crystal capacitor CLC, and a storage capacitor CST. The gate electrode of the switching element TFT is electrically connected to the gate line GL1, and the drain electrode is electrically connected to the liquid crystal capacitor CLC and the storage capacitor CST.

The diodes D1, D2, D3,... Are electrically connected to the data lines DL1, DL2, DL3,... Each diode D1 has a gate electrode and a source electrode connected in common with the inspection unit 140, and includes a drain electrode electrically connected to the data line DL1.

Therefore, when the test signal T1 is applied from the test unit 140, the test signal T1 is applied to the diodes D1, D2, D3,... And the diodes D1, D2, D3, The test signal T1 is transmitted to the data lines DL1, DL2, DL3,... In a 1D manner via. As a result, open lines and short circuits of the data lines DL1, DL2, DL3,...

5 is a plan view of a display panel according to another exemplary embodiment of the present invention.

Referring to FIG. 5, the display panel includes an array substrate 300, a color filter substrate 200 coupled to the array substrate 300, and between the array substrate 300 and the color filter substrate 200. And a liquid crystal layer (not shown) interposed therebetween.

The array substrate 300 includes a display area DA, a first peripheral area PA1 and a second peripheral area PA2 adjacent to the display area DA.

In the display area DA, gate lines GL extending in a first direction, data lines DL extending in a second direction crossing the first direction, and the gate lines GL and the data. The plurality of pixel portions P defined by the wirings DL are included. In each pixel portion P, a switching element TFT, a pixel electrode of a liquid crystal capacitor CLC, and a common electrode of a storage capacitor CST are formed.

A gate circuit 310 is connected to one end of the gate lines GL to apply gate signals to the gate lines in the first peripheral area PA1. As shown in FIG. 2, the gate circuit unit 310 includes a shift register in which a plurality of stages are cascaded, and input terminals 311 to which control signals are input.

The data pad part 320, the electrostatic diode part 330, the first test part 340, and the second test part 350 are formed in the second peripheral area PA2.

The data pad part 320 includes data input pads for applying data signals to the data lines DL. The data input pads are in electrical contact with output terminals of a source driving chip to receive data signals output from the source driving chip. The data input pads are grouped into K groups 3020-1,..., 320 -K corresponding to K source driving chips mounted on the display panel.

The electrostatic diode unit 130 is connected to the data input pads to distribute static electricity introduced from the data input pads. That is, the electrostatic diode unit 130 is formed between the data input pads and the data lines DL and includes a plurality of diodes connected to the data lines DL.

The first test unit 340 includes a first test wire 341 electrically connected to odd-numbered diodes and a first test pad 342 for applying a test signal to the first test wire 341. The first inspection unit 340 applies the inspection signal to odd-numbered data lines through the electrostatic diode unit 330.

The second test unit 350 includes a second test wire 351 electrically connected to even-numbered diodes and a second test pad 352 to apply a test signal to the second test wire 351. The second inspection unit 350 applies the inspection signal to even-numbered data lines through the electrostatic diode unit 330. The first and second inspection units 340 and 350 may facilitate the defect inspection in a 2D inspection method.

Preferably, the first test pad 342 uses a dummy pad of the first group 320-1 on which the first source driving chip is mounted, and the second test pad 352 is mounted on the last source driving chip. A dummy pad of the K-th group 320-K is used. When the source driving chip is mounted, the first and second test pads 342 and 352 may be floated or used as voltage pads to which a common voltage of a storage capacitor is applied.

FIG. 6 is a partially enlarged view of the array substrate illustrated in FIG. 5.

5 and 6, the array substrate includes a display area DA and a first peripheral area PA1 adjacent to the display area DA.

The data pad part 320, the electrostatic diode part 330, the first test part 340, and the second test part 350 are formed in the first peripheral area PA1.

The data pad unit 320 includes a plurality of data input pads DP1, DP2, DP3,..., DPm-2, DPm-1, and DPm, and the data input pads are provided on K source driving chips. Correspondingly, they are grouped into first to K groups 320-1,..., 320 -K.

The electrostatic diode unit 330 includes a first electrostatic diode unit 330-O and a second electrostatic diode unit 330-E.

The first electrostatic diode unit 330-O includes odd-numbered diodes DO1, DO2, and DO3 electrically connected to odd-numbered data input pads DP1, DP3, and DPm-1. The diode unit 330 -E includes even-numbered diodes DE1, DE2, and DE3 electrically connected to the even-numbered data input pads DP2 and DPm-2 DPm.

The first inspection unit 340 may include a first inspection wiring 341 and the first inspection wiring 341 electrically connected to the first electrostatic diode unit 330, that is, the odd-numbered diodes DO1, DO2, and DO3. It includes a first test pad 342 for applying a test signal to the.

In detail, each diode DO1 includes a gate electrode 331 and a source electrode 333 commonly connected to the first inspection line 341, and a drain electrode 334 electrically connected to the data line DL1. do. The source electrode 333 extends from the first inspection line 341, and the gate electrode 331 is electrically connected to the first inspection line 341 through a connection pattern 335. The drain electrode 334 is electrically connected to the data line DL1 through a connection pattern 335. The diode DO1 includes a channel portion 332 interposed between the gate electrode 331 and the source and drain electrodes 333 and 334.

The second inspection unit 350 includes a second inspection wiring 351 and the second inspection wiring electrically connected to the second electrostatic diode unit 330 -E, that is, even-numbered diodes DE1, DE2, and DE3. A second test pad 352 for applying a test signal to the 351.

FIG. 7 is an equivalent circuit diagram of the display panel shown in FIG. 5.

5 and 7, the display panel includes a plurality of gate lines GL1, a plurality of data lines DL1, DL2,... DLm-1, DLm, a plurality of pixel units, and a first electrostatic diode. The unit 330-O, a second electrostatic diode unit 330-E, a first inspection unit 340, and a second inspection unit 350 are included.

Each pixel portion P1 includes a switching element TFT, a liquid crystal capacitor CLC, and a storage capacitor CST. The gate electrode of the switching element TFT is electrically connected to the gate line GL1, and the drain electrode is electrically connected to the liquid crystal capacitor CLC and the storage capacitor CST.

The first electrostatic diode unit 330-O includes odd-numbered diodes DO1 and DO3, and the odd-numbered diodes DO1 and DO3 are electrically connected to the first inspection unit 340. Each diode DO1 has a gate electrode and a source electrode connected to the first inspection unit 340 in common, and includes a drain electrode electrically connected to the odd-numbered data line DL1.

Therefore, when the first inspection signal T1 is applied from the first inspection unit 340, the first inspection signal T1 is applied to the odd-numbered diodes DO1 and DO3, and the first inspection signal T1 is applied. The first test signal T1 is transmitted to the odd-numbered data lines DL1,..., DLm-1 through the odd-numbered diodes DO1, DO3. As a result, open lines and short circuits of the odd-numbered data lines DL1 to DLm-1 may be easily checked.

Meanwhile, the second electrostatic diode unit 330 -E includes even-numbered diodes DE1 and DE3, and the even-numbered diodes DE1 and DE3 are electrically connected to the second inspection unit 350. Each diode DE1 has a gate electrode and a source electrode connected in common with the second inspection unit 350, and includes a drain electrode electrically connected to the even-numbered data line DLm.

Therefore, when the second test signal T2 is applied from the second test unit 350, the second test signal T2 is applied to the even-numbered diodes DE1 and DE3 and the second test signal T2. The first test signal T2 is transmitted to the even-numbered data lines DLm,..., And DL2 via the even-numbered diodes DE1 and DE3. As a result, open lines and short circuits of the even-numbered data lines DLm,... And DL2 can be easily checked.

As a result, a 2D test method of applying a first test signal to odd-numbered data lines through the first test unit 340 and a second test signal to even-numbered data lines through the second test unit 350. The inspection force can improve the detection power such as wiring defects and pixel defects.

In addition, a 1D inspection method of applying substantially the same inspection signal to the first inspection unit 340 formed adjacent to the first day wiring DL1 and the second inspection unit 350 formed adjacent to the last data wiring DLm. In the case of inspection, it is possible to prevent a decrease in detection power due to the delay of the inspection signal.

8 is a schematic perspective view of an inspection apparatus for detecting a failure of a display panel according to the present invention.

Referring to FIG. 8, the test apparatus may include a first signal output unit 510 for applying a test signal to the input terminal 111 of the gate circuit unit 110, and a test signal for applying the test signal to the data input pads 120. And a third signal output unit 540 for outputting a test signal to the second signal output unit 520 and the test unit 140.

In order to inspect the gross surface of the display panel 400, the inspection apparatus 500 may include the probe pins of the first to third signal output units 510, 520, and 530 to input terminals of the display panel 400. Electrical contact with the 111 and the data input pads 120 and the inspection unit 140.

Subsequently, the inspection apparatus 500 outputs the inspection signal of the first type through the first and second signal output units 510 and 520. As a result, the inspection signal of the first type is applied to the gate lines and the data lines of the display panel 400, thereby displaying the inspection image of the first mode on the display panel 400. The wiring defect is detected through the inspection image of the first mode.

Subsequently, in the state in which the probe pins of the first and second signal output units 510 and 520 are in contact with each other, the inspection apparatus 500 may test the signal to the first and second signal output units 510 and 520. The test signal of the second mode is output to the first and third signal output units 540 without outputting the signal.

The test signal of the second type applied through the third signal output unit 540 is applied to the data wires of the display panel 400 through the test unit 140, so that the display panel 400 is second. The inspection image of the mode is displayed. The inspection unit 140 includes diodes electrically connected to the data lines, and the inspection signal of the second mode is transmitted to the data lines through diodes, for example, in a second mode in a 1D or 2D manner. The test signal of is delivered. Therefore, the detection error due to the pin contact miss among the wiring defects detected in the inspection image of the first mode can be confirmed. In addition, pixel defects can be detected in a 2D manner.

Subsequently, a test signal of a third mode is applied to the first and second signal output units 510 and 520 to display the test image of the third mode on the display panel. The inspection image of the third mode is an image including patterns having various colors and shapes, and pixel defects may be detected through the inspection image of the third mode.

As described above, according to the present invention, the inspection unit for applying the inspection signal to the gate lines may be formed in the electrostatic diode unit to prevent a detection error due to a poor pin contact during the gross inspection process. As a result, manufacturing efficiency and reliability of the display panel can be improved, and material waste due to inspection errors can be prevented.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (10)

A gate circuit unit formed at one end of the gate lines to apply a signal to the gate lines; A data pad part formed at one end of the data wires to apply a data signal to the data wires; An electrostatic diode unit connected to the data pad unit to distribute static electricity introduced into the data pad unit; And And a test unit electrically connected to the electrostatic diode unit to apply a test signal to the data lines. The display substrate of claim 1, wherein the electrostatic diode unit comprises a plurality of diodes connected to the data lines, respectively. The method of claim 2, wherein the inspection unit And a test wiring electrically connected to the plurality of diodes, and a test pad connected to the test wiring and to which the test signal is applied. The method of claim 2, wherein the inspection unit A first test pad electrically connected to odd-numbered diodes of the plurality of diodes and a first test pad connected to the first test wire and to which the test signal is applied; And a second test wiring electrically connected to even-numbered diodes of the plurality of diodes, and a second test pad connected to the second test wiring and to which the test signal is applied. The data input pad of claim 4, wherein the data input pads include a plurality of data input pads formed at one end of the data wires. The first test pad is formed adjacent to the first data input pad of the data input pads, And the second test pad is formed adjacent to the last data input pad of the data input pads. The display substrate of claim 4, wherein test signals having different potentials are respectively applied to the first test pad and the second test pad. A plurality of pixel portions, a gate circuit formed at one end of the gate lines to apply a signal to the gate lines, data input pads formed at one end of the data lines, electrostatic diodes connected to the data input pads, and the In the inspection method of the display substrate including an inspection unit connected to the electrostatic diodes, Detecting a first failure by applying a first test signal to the gate circuit and the data input pads; And And applying a second inspection signal to the gate circuit and the inspection unit to detect a second defect. The method of claim 7, wherein the detecting of the first defect The method of claim 1, wherein the first test signal is applied to the data input pads in a one-to-one contact manner to detect a failure of the data lines. The method of claim 8, wherein the detecting of the second defect And detecting the detection error caused by the one-to-one contact method by the second test signal by being applied to the data lines through the electrostatic diodes. The method of claim 7, wherein the inspection unit And a first tester connected to odd-numbered electrostatic diodes connected to the odd-numbered data lines, and a second tester connected to even-numbered electrostatic diodes connected to even-numbered data lines. Detecting the second failure And detecting defects of the pixel units by applying second inspection signals having different potential levels to the first and second inspection units, respectively.

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