CN114779536B

CN114779536B - Display panel and display device

Info

Publication number: CN114779536B
Application number: CN202210457448.0A
Authority: CN
Inventors: 姜童洲; 熊雄; 郑敏栋; 丁雷鸣; 李佑路
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2023-08-08
Anticipated expiration: 2042-04-27
Also published as: WO2023207670A1; CN114779536A

Abstract

The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a display area and an isolation area, and the isolation area is positioned at one side of the display area; the isolation region comprises a first isolation region and/or a second isolation region; the first isolation region includes at least one row of pixel units and a first common electrode block; the first common electrode block is disconnected from the common electrode block of the display area; the second isolation region comprises at least one column of pixel units and a second common electrode block; the second common electrode block is disconnected from the common electrode block of the display area; each pixel unit comprises a pixel electrode, and the pixel electrode forms a capacitor with the first common electrode block or the second common electrode block. The capacitor can store charges, can be used for voltage stabilization, decoupling, filtering, an analog signal generation circuit and the like, so that the signal pulling of the display panel can be improved, and defects such as pits, noise and the like can be reduced.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the continuous development of the liquid crystal display (Liquid Crystal Display, LCD) industry, the demands of liquid crystal displays are increasing.

At present, the problems of ESD (Electro-Static discharge) and signal pulling of the liquid crystal display panel are not solved. Particularly, a small-sized liquid crystal display panel with high wiring overlapping has signal pulling, resulting in occurrence of defects such as pits and noise.

Disclosure of Invention

The application provides a display panel and a display device aiming at the defects of the prior art, which are used for solving the technical problems of signal pulling, pit, noise and the like in the prior art.

In a first aspect, an embodiment of the present application provides a display panel, including a display area and an isolation area, where the isolation area is located at one side of the display area;

the isolation region comprises a first isolation region and/or a second isolation region;

the first isolation region includes at least one row of pixel units and a first common electrode block; the first common electrode block is disconnected from the common electrode block of the display area;

the second isolation region comprises at least one column of pixel units and a second common electrode block; the second common electrode block is disconnected from the common electrode block of the display area;

each pixel unit comprises a pixel electrode, and the pixel electrode forms a capacitor with the first common electrode block or the second common electrode block.

In an alternative implementation, for the first isolation region, at least one first scan line and a plurality of first traces are included;

the pixel units in one row of pixel units are electrically connected with a first scanning line, and each pixel unit in one row of pixel units is electrically connected with a first wiring line respectively; the first wiring is disconnected with the data line of the display area; the first scanning line is used for receiving a first set voltage, and the first wiring is used for being electrically connected with a circuit to be stabilized; the first common electrode block is electrically connected with the ground terminal.

In an alternative implementation, the second isolation region is targeted;

the second isolation region comprises at least one second wiring and a plurality of second scanning lines, the pixel units in a row of pixel units are electrically connected with the second wiring, and each pixel unit in the row of pixel units is electrically connected with one second scanning line respectively; the second scanning line is disconnected with the scanning line of the display area; the second scanning line is used for receiving a second set voltage; the second wiring is used for electrically connecting the circuit to be stabilized; the second common electrode block is electrically connected with the grounding end;

alternatively, the display panel includes a non-display region surrounding the display region and the isolation region, the non-display region is provided with a GOA circuit, and a capacitor formed by the pixel unit and the second common electrode block is connected to the GOA circuit.

In an alternative implementation of the present invention,

each pixel unit further comprises a transistor for the first isolation region; the first electrode of the transistor is electrically connected with the first wiring; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the first scanning line.

Each pixel unit further comprises a transistor for the second isolation region; the first electrode of the transistor is electrically connected with the second wiring; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the second scanning line.

In an alternative implementation, the first isolation region is, for the first isolation region,

the at least one row of pixel units comprises a row of pixel units;

adjacent at least two first wirings are electrically connected together and are electrically connected with the circuit to be stabilized.

In an alternative implementation, the method further includes:

and the shading piece is used for shading at least one row of pixel units of the first isolation area.

In an alternative implementation, for the second isolation region, when the non-display region is provided with the GOA circuit:

the plurality of pixel electrodes of the at least one column of pixel units comprise a first pixel electrode group, a second pixel electrode group and a third pixel electrode group; each pixel electrode group includes at least one pixel electrode;

the second common electrode block includes a first common electrode unit, a second common electrode unit, and a third common electrode unit; the first common electrode unit, the second common electrode unit and the third common electrode unit are disconnected from each other;

the first pixel electrode group and the first common electrode unit form a first capacitor; the second pixel electrode group and the second common electrode unit form a second capacitor; the third pixel electrode group and the third common electrode unit form a third capacitor.

In an alternative implementation, the GOA circuit includes a first switching module, a second switching module, a clock generation module, and a voltage regulation module;

the first switch module is electrically connected with the second pixel electrode group and is used for receiving a first clock signal;

the second switch module is electrically connected with the first common electrode unit and is used for receiving a second clock signal;

the first pixel electrode group is electrically connected with the second pixel electrode group and is electrically connected with the clock generation module; the clock generation module is used for outputting a target clock signal;

the second common electrode unit is electrically connected with the first end of the voltage regulating module;

the second end of the voltage regulating module is electrically connected with the third common electrode unit and the grounding end respectively;

and the third end of the voltage regulating module is respectively and electrically connected with the third pixel electrode group and the clock generating module.

In an alternative implementation, the clock generation module includes a first transistor and a second transistor;

the drain electrode of the first transistor is used for receiving a high-level signal, and the drain electrode of the second transistor is used for receiving a low-level signal;

the source electrode of the first transistor is electrically connected with the source electrode of the second transistor and is used as an output end of the clock generation module for outputting a target clock signal;

the grid electrode of the first transistor is electrically connected with the first pixel electrode group and the second pixel electrode group respectively;

and the grid electrode of the second transistor is respectively and electrically connected with the third pixel electrode group and the clock generation module.

In an alternative implementation, the first switch module includes a third transistor and the second switch module includes a fourth transistor;

the grid electrode and the drain electrode of the third transistor are electrically connected, and the source electrode of the third transistor is electrically connected with the second pixel electrode group;

the gate and the drain of the fourth transistor are electrically connected, and the source of the fourth transistor is electrically connected to the first common electrode unit.

In an alternative implementation, the voltage regulation module includes a fifth transistor and a sixth transistor;

the grid electrode and the drain electrode of the fifth transistor are electrically connected;

the grid electrode and the drain electrode of the sixth transistor are electrically connected;

a drain electrode of the fifth transistor and a source electrode of the sixth transistor, and are electrically connected to the second common electrode unit;

the source electrode of the fifth transistor is electrically connected with the third common electrode unit and the grounding end respectively;

and the drain electrode of the sixth transistor is respectively and electrically connected with the third pixel electrode group and the clock generation module.

In an alternative implementation, the non-display area further includes a fourth pixel electrode group and a fourth common electrode block;

the fourth pixel electrode group and the fourth common electrode block form a fourth capacitor connected in parallel with the first capacitor formed by the first pixel electrode group and the first common electrode unit.

In a second aspect, embodiments of the present application provide a display device including a source driver and the display panel of the first aspect;

the source driver is electrically connected with the display area of the display panel.

The beneficial technical effects that technical scheme that this application embodiment provided brought include:

the display panel provided by the embodiment of the application comprises a display area and an isolation area, wherein the isolation area is positioned on one side of the display area, the isolation area can comprise a first isolation area and/or a second isolation area, and the first isolation area and/or the second isolation area are respectively isolated from the display area. The first isolation region comprises at least one row of pixel units and a first common electrode block, the second isolation region comprises at least one column of pixel units and a second common electrode block, each pixel unit comprises a pixel electrode, and the pixel electrode forms a capacitor with the first common electrode block or the second common electrode block. The capacitor can store charges, can be used for voltage stabilization, decoupling, filtering, an analog signal generation circuit and the like, so that the signal pulling of the display panel can be improved, and defects such as pits, noise and the like can be reduced.

In addition, through optimizing the display panel, only the area where at least one row or one column of pixel units are located is used as an isolation area to be isolated from the display area, the whole position layout of the pixel array of the whole display panel is not required to be changed, the capacitor is directly manufactured in the pixel array process of the display panel, the capacitor is not required to be hung externally, and meanwhile, the changing cost can be reduced.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;

FIG. 3 is an equivalent circuit diagram of a pixel unit according to an embodiment of the present application;

fig. 4a is a schematic structural diagram of another display panel according to an embodiment of the present disclosure;

fig. 4b is a schematic structural diagram of another display panel according to an embodiment of the present application.

FIG. 5 is a circuit diagram of a single analog signal generation circuit provided in an embodiment of the present application;

fig. 6 is an equivalent circuit diagram of a single analog signal generation circuit of fig. 5 provided in an embodiment of the present application.

Reference numerals:

100-display panel, 10-first isolation region, 20-display region, 30-non-display region, 40-second isolation region;

11-pixel units, 111-first pixel electrode groups, 112-second pixel electrode groups, 113-third pixel electrode groups, 12-first common electrode blocks, 121-first common electrode units, 122-second common electrode units, 123-third common electrode units;

31-GOA circuit, 32-first switch module, 33-second switch module, 34-clock generation module, 35-voltage regulation module.

Detailed Description

Examples of embodiments of the present application are illustrated in the accompanying drawings, in which like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application.

It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.

The problems of ESD (Electro-Static discharge) and signal pulling of the liquid crystal display panel have not been solved. Particularly, a small-sized liquid crystal display panel with high wiring overlapping has signal pulling, resulting in occurrence of defects such as pits and noise.

The inventor of the application researches and discovers that the capacitor is a good component for voltage stabilization, decoupling and filtering, and can well solve the defects such as pits, noise and the like caused by signal pulling of the traditional liquid crystal display panel.

The inventors of the present application considered that the capacitor could be made in the array process of the liquid crystal display panel because the liquid crystal display panel cannot perform the plug-in capacitor. The capacitance between the pixel electrode and the common electrode in the liquid crystal display panel is larger, and the liquid crystal display panel can well store more charges, so that the liquid crystal display panel can be used for voltage stabilization, decoupling, filtering and the like, and the defects such as pits, noise and the like caused by signal pulling in the prior art are solved.

Therefore, the display panel and the display device provided by the application aim to solve the technical problem that the signal pulling in the prior art causes defects such as pits, noise and the like.

The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments.

The embodiment of the application provides a display panel 100, as shown in fig. 1, 4a and 4b, the display panel 100 includes a display area 20 and an isolation area, and the isolation area is located at one side of the display area 20; in particular, the display panel 100 is a liquid crystal display panel.

The isolation regions include a first isolation region 10, and/or a second isolation region 40; the second isolation region 40 may be positioned at the leftmost or rightmost side of the display region 20.

The first isolation region 10 includes at least one row of pixel cells 11 and a first common electrode block 12; the first common electrode block is disconnected from the common electrode block (e.g., VCOM block in fig. 2) of the display area 20.

The second isolation region 40 includes at least one column of pixel cells and a second common electrode block (not shown in the drawings); the second common electrode block is disconnected from the common electrode block of the display area 20.

Each pixel cell 11 includes a pixel electrode that forms a capacitance with the first common electrode block 12 or with the second common electrode block.

The display panel 100 provided in this embodiment of the present application includes a display area 20 and an isolation area, where the isolation area is located at one side of the display area, and the isolation area may include a first isolation area 10 and/or a second isolation area 40, where the first isolation area 10 and/or the second isolation area 40 are isolated from the display area 20 respectively. The first isolation region 10 includes at least one row of pixel cells 11 and a first common electrode block 12, and the second isolation region 40 includes at least one column of pixel cells and a second common electrode block, each pixel cell 11 including a pixel electrode forming a capacitance with the first common electrode block 12 or with the second common electrode block. The capacitor can store charges, can be used for voltage stabilization, decoupling, filtering, an analog signal generation circuit and the like, so that the signal pulling of the display panel can be improved, and defects such as pits, noise and the like can be reduced.

In addition, by performing the optimization processing on the display panel, only the area where at least one row or one column of pixel units are located is isolated from the display area as an isolation area, the overall position layout of the pixel array of the whole display panel 100 is not required to be changed, the capacitor is directly manufactured in the pixel array process of the display panel 10, the capacitor is not required to be hung externally, and meanwhile, the changing cost can be reduced.

It should be noted that, the pixel units included in the first isolation region are first row pixel units in the display region 20, as shown in fig. 2, the first common electrode block 12 is disconnected from the common electrode block in the display region 20, specifically, the first common electrode block 12 and the common electrode block in the display region 20 are manufactured by adopting the same patterning process, and the obtained integral continuous common electrode block is then disconnected from the common electrode blocks in the corresponding positions of the first row pixel units 11 from the common electrode blocks in other positions, so as to form separated first common electrode blocks 12 and the common electrode blocks in the display region 20.

In fig. 1, 2, 4a, and 4b, the DP side is a side where an active driver (e.g., a source driver) is provided, and the DPO side is a side opposite to the DP side.

In fig. 2, the first isolation region 10 is located on the DPO side of the display panel 100, and the display region 20 is located on the DP side of the display panel 100.

In some embodiments, as shown in fig. 2, for the first isolation region 10, at least one first scan line (e.g., G0 in fig. 2) and a plurality of first traces (e.g., two adjacent first traces are connected together to form one trace X1-X6 in fig. 2);

the pixel units 11 in one row of pixel units are electrically connected with a first scanning line, and each pixel unit 11 in one row of pixel units is electrically connected with a first wiring line respectively; the first trace is disconnected from the data lines (e.g., data lines D1-D12 in FIG. 2) of the display area 20; the first scanning line is used for receiving a first set voltage, and the first wiring is used for being electrically connected with a circuit to be stabilized; the first common electrode block 12 is electrically connected to the ground GND.

It should be noted that, as shown in fig. 2, the first trace is disconnected from the data line of the display area 20, specifically, the first trace and the data line of the display area 20 are manufactured by the same patterning process, the obtained data line is an integral continuous data line, and then the data line at the corresponding position of the first row of pixel units is disconnected from the data lines at other positions, so as to form a separated first trace and the data line of the display area 20, where the first trace does not receive the data signal.

It should be noted that, in order to reduce the influence on the display of the display panel, in this embodiment, the first isolation area 10 includes a row of pixel units 11, correspondingly, the first isolation area 10 includes a scan line G0, where the scan line G0 is configured to receive a first set voltage, and the first set voltage is, for example, a certain constant voltage value (specifically set according to practical situations), and in a specific implementation, if the column number of the row of pixel units 11 is M, M first wirings may be correspondingly configured in this embodiment, and each first wiring is correspondingly connected to one pixel unit 11.

In some embodiments, for the second isolation region 40; the second isolation region 40 includes at least one second trace and a plurality of second scan lines, each pixel unit in a column of pixel units is electrically connected to one second trace, and each pixel unit in a column of pixel units is electrically connected to one second scan line; the second scanning line is disconnected with the scanning line of the display area; the second scanning line is used for receiving a second set voltage; the second wiring is used for electrically connecting the circuit to be stabilized; the second common electrode block is electrically connected with the grounding end; (not shown in the drawings).

Alternatively, as shown in fig. 4a and 4b, the display panel 100 includes a non-display region 30 surrounding the display region 20 and the isolation region 40, the non-display region 30 is provided with a GOA circuit 31, and a capacitor formed by the pixel unit and the second common electrode block is connected to the GOA circuit.

It should be noted that, the second trace is disconnected from the scan lines of the display area 20, specifically, the second trace and the scan lines of the display area 20 are manufactured by the same patterning process, the obtained scan lines are integrally continuous, and then the scan lines at the corresponding positions of the first row of pixel units are disconnected from the scan lines at other positions, so as to form separate second traces and the scan lines of the display area 20, where the second traces do not receive the scan signals.

In some embodiments, each pixel cell further comprises a transistor for the first isolation region 10; the first electrode of the transistor is electrically connected with the first wiring; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the first scanning line.

Each pixel cell further includes a transistor for the second isolation region 40; the first electrode of the transistor is electrically connected with the second wiring; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the second scanning line.

Alternatively, the transistor is a TFT (Thin Film Transistor ), the "control electrode" specifically refers to the gate electrode of the transistor, the "first electrode" specifically refers to the source electrode or drain electrode of the transistor, and the "second electrode" specifically refers to the drain electrode or source electrode of the transistor, respectively.

Illustratively, as shown in FIG. 3, the first pole of the transistor TFT is electrically connected to a first trace (e.g., one of the adjacent two first traces connected together to form one trace X1 in FIG. 2); a second electrode of the transistor TFT is electrically connected with the pixel electrode; the gate electrode of the transistor TFT is electrically connected to a first scan line (e.g., the first scan line G0 in fig. 2).

In some embodiments, for the first isolation region, at least one row of pixel cells comprises a row of pixel cells; adjacent at least two first wirings are electrically connected together and are electrically connected with the circuit to be stabilized.

As shown in fig. 2, in the embodiment of the present application, the first isolation region 10 includes a row of pixel units 11, correspondingly, the first isolation region 10 includes a scan line G0, where the scan line G0 is configured to receive a first set voltage, and the first set voltage is, for example, a certain constant voltage value (needs to be specifically set according to practical situations), and in a specific implementation, if the column number of the row of pixel units 11 is M, M first wirings may be correspondingly set in the embodiment of the present application, and each first wiring is correspondingly connected to one pixel unit 11.

As shown in fig. 2, two adjacent first wires in the embodiment of the present application are electrically connected together to form one wire X1-X6. The wirings X1-X6 are respectively connected with different circuits to be stabilized. In fig. 2, VCOM represents a common electrode, D1, D2 … … D12 represent data lines of the display area 20, and G1 and G2 represent scan lines of the display area 20. The control electrodes of the transistors of the first row of pixel units 11 are electrically connected to the scan line G0, and each transistor is electrically connected to a first trace. Two adjacent first wires are electrically connected together to form one wire, for example, wires X1, X2, X3, X4, X5, and X6 are each formed by connecting two adjacent first wires together.

In fig. 2, only by way of example, it is of course possible to electrically connect other numbers of adjacent first wires 3, 4, 5, etc., which is not limited in this application.

The wirings X1, X2, X3, X4, X5, and X6 may be electrically connected to different circuits to be stabilized, and the circuits to be stabilized may be constant voltage circuits, for example, VCOM (common electrode) circuits, VGH circuits, VDD circuits, etc., so as to perform voltage stabilizing filtering on VCOM, VGH, VDD, improve signal pulling, and reduce occurrence of defects such as pits and noise.

As shown in fig. 2 and 3, the transistor TFT of each pixel cell 11 of the first row is equivalent to a variable resistor R, and the capacitance formed by the pixel electrode of each pixel cell 11 of the first row and the first common electrode block 12 is equivalent to a capacitance C. The electrically connected scan line G0 of the first row of pixel units 11 receives a set voltage, which is a certain constant voltage.

The embodiment of the application can control the leakage size of the transistor TFT by changing the voltage value of the set voltage, namely the transistor TFT is equivalent to a variable resistor R controlled by the voltage. However, the capacitance of the capacitance formed by the pixel electrode of the individual pixel cell 11 and the first common electrode block 12 is limited, and thus, an increase in the overall capacitance can be achieved by connecting adjacent pixel cells 11 in parallel, thereby achieving an optimal stabilizing and filtering effect.

According to the embodiment of the application, the voltage stabilization and filtering are performed by increasing the capacitance value through the parallel capacitor, the ESD (Electrical Static Discharge, electrostatic discharge) resistance is improved by utilizing the capacitor to store charges, and meanwhile, high-frequency clutter can be filtered out, so that the voltage stability of the circuit to be stabilized is better, and the service lives of the display panel 100 and an IC (chip) are prolonged.

In some embodiments, as shown in fig. 2, further comprising: a light shielding member for shielding at least one row of the pixel units 11 of the first isolation region 10.

Optionally, the light shielding piece is Tape glue, and the Tape glue is one of the light shielding adhesive tapes, and is mainly used for pasting and shielding light in optical display devices, and is widely used for electronic display screens of notebook computers, mobile phones, PDAs, digital codes and the like. Specifically, the lcd of the display panel 100 may be attached to the Tape to perform adhesion and shading functions.

The first isolation region 10 is shielded by the light shielding member, so that the display of the display panel 100 is not disturbed, and the display image quality of the whole display panel 100 is not affected.

Optionally, the display panel 100 further includes a plurality of identifiers for identifying different circuits to be stabilized electrically connected to the pixel unit 11 by identifying the pixel unit 11.

For example, in fig. 2, a trace X1 is electrically connected to a first circuit to be stabilized, a trace X2 is electrically connected to a second circuit to be stabilized, a trace X3 is electrically connected to a third circuit to be stabilized, a trace X4 is electrically connected to a fourth circuit to be stabilized, a trace X5 is electrically connected to a fifth circuit to be stabilized, and a trace X6 is electrically connected to a sixth circuit to be stabilized.

The identification may be a pixel number, and the pixel number may be a pixel number with a color, for example, a red pixel number 1 marks a first pixel unit and a second pixel unit in the first row of pixel units 11, so that the first circuit to be stabilized is marked.

According to the embodiment of the application, the plurality of marks are arranged, the pixel unit 11 can be marked, and then different voltage stabilizing circuits electrically connected with the pixel unit 11 are marked, so that whether the voltage stabilizing circuits electrically connected with the pixel unit 11 are normal or not can be roughly confirmed through the brightness of the pixel unit 11.

In some embodiments, for the second isolation region 40, when the non-display region 30 is provided with the GOA circuit 31:

if the second isolation region 40 includes at least one column of pixel units and a second common electrode block;

the plurality of pixel electrodes of the at least one column of pixel units includes a first pixel electrode group 111, a second pixel electrode group 112, and a third pixel electrode group 113.

The second common electrode block includes a first common electrode unit 121, a second common electrode unit 122, and a third common electrode unit 123; the first, second and third common electrode units 121, 122 and 123 are all disconnected from each other.

The first pixel electrode group 111 and the first common electrode unit 121 form a first capacitance; the second pixel electrode group 112 and the second common electrode unit 122 form a second capacitance; the third pixel electrode group 113 forms a third capacitance with the third common electrode unit 123.

Each pixel electrode group comprises at least one pixel electrode, and the at least one pixel electrode is connected together.

In some embodiments, as shown in fig. 5 and 6, the GOA circuit 31 includes a first switching module 32, a second switching module 33, a clock generation module 34, and a voltage regulation module 35.

The first switch module 32 is electrically connected to the second pixel electrode set 112 and is used for receiving a first clock signal CLKa;

the second switch module 33 is electrically connected to the first common electrode unit 121 and receives the second clock signal CLKb;

the first pixel electrode group 111 is electrically connected to the second pixel electrode group 112 and to the clock generation module 34; the clock generation module 34 is configured to output a target clock signal CLK1;

the second common electrode unit 122 is electrically connected to the first end of the voltage adjustment module 35;

a second terminal of the voltage adjusting module 35 is electrically connected to the third common electrode unit 123 and the ground GND, respectively;

the third terminal of the voltage adjustment module 35 is electrically connected to the third pixel electrode group 113 and the clock generation module 34, respectively.

As shown in fig. 5 and 6, the first pixel electrode group 111 and the first common electrode unit 121 form a first capacitance C1; the second pixel electrode group 112 and the second common electrode unit 122 form a second capacitor C2; the third pixel electrode group 113 forms a third capacitance C3 with the third common electrode unit 123.

The capacitor formed by the pixel electrode of the second isolation region 40 and the second common electrode block is applied to the GOA circuit to generate an analog signal generating circuit, such as a square wave generating circuit (CLK circuit, STV circuit, etc.). The EOS (Electrical Over Stress, over electrical stress) and ESD (Electrical Static Discharge, electrostatic discharge) risks can be reduced, the total length of the high-level line can be reduced, and the power consumption can be further reduced.

As shown in fig. 5 and fig. 6, the capacitor formed by the pixel electrode of the second isolation region 40 and the second common electrode block is applied to the GOA circuit, and the working principle of the square wave generating circuit is as follows: in the first period, when the first clock signal CLKa is at the high level, the first switch module 32 is turned on, and transmits the first clock signal CLKa at the high level to the first node a to charge the first capacitor C1; when the second clock signal CLKb is at a high level, the second switch module 33 is turned on, the high-level second clock signal CLKb is transmitted to the first capacitor C1, and the first capacitor C1 increases the voltage of the first node a in a bootstrap manner according to the high-level second clock signal CLKb, so that the clock generation module 34 outputs the first level signal;

in the second period, when at least one of the first clock signal CLKa and the second clock signal CLKb is at a low level, at least one of the first switch module 32 and the second switch module 33 is turned off, and the clock generation module 34 outputs a second level signal; the first level signal and the second level signal are signals with opposite level logic states, and alternately change to form a target clock signal CLK1.

In some embodiments, the clock generation module 34 includes a first transistor T1 and a second transistor T2;

the drain electrode of the first transistor T1 is used for receiving a high-level signal VGH, and the drain electrode of the second transistor T2 is used for receiving a low-level signal VGL;

the source of the first transistor T1 is electrically connected to the source of the second transistor T2, and is used as an output terminal of the clock generation module 34 for outputting the target clock signal CLK1;

the gate of the first transistor T1 is electrically connected to the first pixel electrode group 111 and the second pixel electrode group 112, respectively;

the gate of the second transistor T2 is electrically connected to the third pixel electrode group 113 and the clock generation module 34, respectively.

In some embodiments, the first switch module 32 includes a third transistor T3, and the second switch module 33 includes a fourth transistor T4;

the gate and the drain of the third transistor T3 are electrically connected, and the source of the third transistor T3 is electrically connected to the second pixel electrode group 112;

the gate and the drain of the fourth transistor T4 are electrically connected, and the source of the fourth transistor T4 is electrically connected to the first common electrode unit 121.

In some embodiments, the voltage regulation module 35 includes a fifth transistor T5 and a sixth transistor T6;

the gate and the drain of the fifth transistor T5 are electrically connected;

the gate and the drain of the sixth transistor T6 are electrically connected;

a drain of the fifth transistor T5 and a source of the sixth transistor T6, and are electrically connected to the second common electrode unit 122;

a source of the fifth transistor T5 is electrically connected to the third common electrode unit 123 and the ground GND, respectively;

the drain of the sixth transistor T6 is electrically connected to the third pixel electrode group 113 and the clock generation module 34, respectively.

Alternatively, the transistors in the GOA circuit 31 may be TFTs (Thin Film Transistor, thin film transistors), and the transistors in the GOA circuit 31 may be N-type transistors, so that the same manufacturing process may be used to manufacture the transistors at the same time, thereby shortening the production cycle of the display panel. It should be noted that all the transistors of the GOA circuit 31 are N-type thin film transistors, which is only a preferred embodiment of the present invention, and this is not a limitation of the technical solution of the present invention. In this embodiment, at least some of the transistors may also be selectively P-type thin film transistors.

Specifically, as shown in fig. 6, when the first clock signal CLK a is in the rising delay, the third transistor T3 is turned on, at this time, the first capacitor C1 starts to store charge, the potential at the first node a rises to 10V (volts), when the second clock signal CLK b is in the high level, the voltage at the first node a will further rise until the voltage at the first node a rises to 20V, the gate-source voltage Vgs1 > Vth1 of the first transistor T1, vth1 is the threshold voltage of the first transistor T1, at this time, the first transistor T1 is turned on (i.e., turned on), the second transistor T2 is turned off, the voltage of the high level signal VGH directly falls to the point b, at this time, the target clock signal CLK1 is the high level signal VGH. When the first clock signal CLK a and the second clock signal CLK b are at other levels, the gate-source voltage Vgs1 of the first transistor T1 is less than Vth1, vth1 is the threshold voltage of the first transistor T1, the gate-source voltage Vgs2 of the second transistor T2 is greater than Vth2, vth2 is the threshold voltage of the second transistor T2, the first transistor T1 is turned off, the second transistor T2 is turned on, at this time, the voltage of the low level signal VHL directly falls to the point b, and at this time, the target clock signal CLK1 is the low level signal VGL.

The first clock signal CLK a and the second clock signal CLK b may be provided through an IC chip in the display panel. The fifth transistor T5 and the sixth transistor T6 are equivalent to diodes and function as unidirectional conduction.

The target clock signal CLK1 may be applied to the GOA circuit 31, and the GOA circuit 31 provides an input clock signal (i.e., the target clock signal CLK 1) to the GOA circuit 31, and the GOA circuit 31 outputs the scan signals Gate1, gate2, gate3 … … to each row of pixel units in the display area of the display panel.

The present embodiment directly generates the target clock signal CLK1 by using the high level signal VGH and the low level signal VGL. Therefore, the IC is not required to directly generate the target clock signal CLK1, so that the influence of the back-end pseudo capacitor on the pulling of the signal is reduced, the abnormal operation of the IC is not influenced by the abnormal back-end, and the influence on the IC is reduced. Meanwhile, the total circuit of high voltage is reduced, so that the effect of reducing power consumption can be achieved.

The square wave generating circuit provided by the embodiment of the application can enhance the ESD and EOS resistance by adopting the fast closing of the capacitor and the transistor TFT. ESD and EOS are generated by abnormal charges, and the square wave generation circuit can also limit the movement of charges.

In some embodiments, the non-display region 20 further includes a fourth pixel electrode group and a fourth common electrode block;

the fourth pixel electrode group and the fourth common electrode block form a fourth capacitance, and the capacitance value can be increased for the effect of the lifting voltage in parallel with the first pixel electrode group 111 and the first common electrode unit 121 forming the first capacitance C1. That is, the fourth pixel electrode group is electrically connected to the first pixel electrode group 111; the fourth common electrode block is electrically connected to the first common electrode unit 121. The fourth pixel electrode group includes at least one pixel electrode.

Optionally, the non-display region may further include a fifth capacitor formed by the fifth pixel electrode group and the fifth common electrode block, in parallel with the second capacitor C2 formed by the second pixel electrode group 112 and the second common electrode unit 122.

Alternatively, the non-display region may further include a sixth capacitor formed by the sixth pixel electrode group and the sixth common electrode block in parallel with the third capacitor C3 formed by the third pixel electrode group 113 and the third common electrode unit 123.

Capacitors with various capacitance values can be manufactured in the non-display area 30 through the pixel electrode and the common electrode block positioned in the non-display area 30 for various square wave generating circuits.

Based on the same inventive concept, the embodiments of the present application provide a display device including a source driver and the display panel 100 provided by any of the above embodiments;

the source driver is electrically connected to the display area 20 of the display panel 100.

As shown in fig. 1, the source driver is located on the DP side of the display panel 100, and is electrically connected to the display area 20 of the display panel 100, for outputting data signals to the pixel units of the display area 20.

The display device provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as those of the previous embodiments, and the content not shown in detail in the display device may refer to the previous embodiments, which are not described herein again.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

Those of skill in the art will appreciate that the various operations, methods, steps in the flow, actions, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed in this application may be alternated, altered, rearranged, split, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the flowcharts of the figures may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily being sequential, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for a person skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A display panel, comprising a display area and an isolation area, wherein the isolation area is positioned at one side of the display area;

the first isolation region comprises at least one row of pixel units and a first common electrode block; the first common electrode block is disconnected from the common electrode block of the display area;

each pixel unit comprises a pixel electrode, and the pixel electrode forms a capacitor with the first common electrode block or the second common electrode block;

for the first isolation region, the first isolation region comprises at least one first scanning line and a plurality of first wirings;

the pixel units in one row of pixel units are electrically connected with a first scanning line, and each pixel unit in one row of pixel units is electrically connected with a first wiring line respectively; the first wiring is disconnected with the data line of the display area; the first scanning line is used for receiving a first set voltage, and the first wiring is used for being electrically connected with a circuit to be stabilized; the first common electrode block is electrically connected with the grounding terminal.

2. The display panel of claim 1, wherein for the second isolation region;

the second isolation region comprises at least one second wiring and a plurality of second scanning lines, the pixel units in a row of pixel units are electrically connected with the second wiring, and each pixel unit in the row of pixel units is electrically connected with one second scanning line respectively; the second scanning line is disconnected with the scanning line of the display area; the second scanning line is used for receiving a second set voltage; the second wiring is used for electrically connecting a circuit to be stabilized; the second common electrode block is electrically connected with the grounding terminal.

3. The display panel of claim 2, wherein the display panel comprises,

for the first isolation region, each pixel cell further includes a transistor; a first electrode of the transistor is electrically connected with the first wiring; a second electrode of the transistor is electrically connected with the pixel electrode; a control electrode of the transistor is electrically connected with the first scanning line;

for the second isolation region, each of the pixel units further includes a transistor; the first electrode of the transistor is electrically connected with the second wiring; a second electrode of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the second scanning line.

4. The display panel of claim 1, wherein, for the first isolation region,

the at least one row of pixel units comprises a row of pixel units;

5. The display panel of claim 1, further comprising:

6. A display device comprising a source driver and the display panel according to any one of claims 1 to 5;