CN114779536A

CN114779536A - Display panel and display device

Info

Publication number: CN114779536A
Application number: CN202210457448.0A
Authority: CN
Inventors: 姜童洲; 熊雄; 郑敏栋; 丁雷鸣; 李佑路
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2022-07-22
Anticipated expiration: 2042-04-27
Also published as: WO2023207670A1; CN114779536B

Abstract

The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a display area and an isolation area, and the isolation area is positioned on one side of the display area; the isolation region comprises a first isolation region and/or a second isolation region; the first isolation region includes at least one row of pixel units and a first common electrode block; the first common electrode block is disconnected with the common electrode block in the display area; the second isolation region comprises at least one column of pixel units and a second common electrode block; the second common electrode block is disconnected with the common electrode block of the display area; each pixel unit comprises a pixel electrode, and the pixel electrode forms a capacitor with the first common electrode block or the second common electrode block. The capacitor can store electric charge, and can be used for voltage stabilization, decoupling, filtering, and analog signal generation circuit, so as to improve signal pull of display panel, thereby reducing defects such as pits and noise.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the continuous development of the Liquid Crystal Display (LCD) industry, people have higher and higher requirements on the LCD.

At present, the problems of Electro-Static discharge (ESD) and signal pull of the lcd panel are not solved. Especially, a small-sized liquid crystal display panel with high wiring overlapping has signal pull, resulting in occurrence of defects such as pits and noise.

Disclosure of Invention

This application provides a display panel and display device to the shortcoming of current mode for there is the signal pulling in solving prior art, leads to appearing like unfavorable technical problem such as hole line and noise.

In a first aspect, an embodiment of the present application provides a display panel, including a display region and an isolation region, where the isolation region is located on one side of the display region;

the isolation region comprises a first isolation region and/or a second isolation region;

the first isolation region comprises at least one row of pixel units and a first common electrode block; the first common electrode block is disconnected with the common electrode block of the display area;

the second isolation region comprises at least one column of pixel units and a second common electrode block; the second common electrode block is disconnected with the common electrode block in the display area;

each pixel unit comprises a pixel electrode, and the pixel electrode forms a capacitor with the first common electrode block or the second common electrode block.

In an optional implementation manner, for the first isolation region, the first isolation region includes at least one first scan line and a plurality of first routing lines;

the pixel units in one row of pixel units are electrically connected with a first scanning line, and each pixel unit in one row of pixel units is electrically connected with a first wiring line; the first routing is disconnected with the data line of the display area; the first scanning line is used for receiving a first set voltage, and the first wire is used for electrically connecting the voltage stabilizing circuit to be stabilized; the first common electrode block is electrically connected with a ground terminal.

In an alternative implementation, for the second isolation region;

the second isolation region comprises at least one second wiring and a plurality of second scanning lines, the pixel units in one row of pixel units are electrically connected with the second wiring, and each pixel unit in one row of pixel units is electrically connected with one second scanning line; the second scanning line is disconnected with the scanning line of the display area; the second scanning line is used for receiving a second set voltage; the second wire is used for electrically connecting the voltage stabilizing circuit to be stabilized; the second common electrode block is electrically connected with the grounding end;

or the display panel comprises a non-display area surrounding the display area and the isolation area, the non-display area is provided with a GOA circuit, and a capacitor formed by the pixel unit and the second common electrode block is connected with the GOA circuit.

In an alternative implementation form of the present invention,

for the first isolation region, each pixel cell further comprises a transistor; the first pole of the transistor is electrically connected with the first routing; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the first scanning line.

For the second isolation region, each pixel cell further comprises a transistor; the first electrode of the transistor is electrically connected with the second routing; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the second scanning line.

In an alternative implementation, for the first isolation region,

at least one row of pixel units comprises one row of pixel units;

at least two adjacent first wires are electrically connected together and are electrically connected with the voltage stabilizing circuit to be stabilized.

In an optional implementation manner, the method further includes:

the shading part is used for shading at least one row of pixel units of the first isolation area.

In an optional implementation manner, for the second isolation region, when the non-display region is provided with the GOA circuit:

the plurality of pixel electrodes of at least one column of pixel units comprise a first pixel electrode group, a second pixel electrode group and a third pixel electrode group; each pixel electrode group comprises at least one pixel electrode;

the second common electrode block comprises a first common electrode unit, a second common electrode unit and a third common electrode unit; the first common electrode unit, the second common electrode unit and the third common electrode unit are disconnected with each other;

the first pixel electrode group and the first common electrode unit form a first capacitor; the second pixel electrode group and the second common electrode unit form a second capacitor; the third pixel electrode group and the third common electrode unit form a third capacitor.

In an optional implementation manner, the GOA circuit includes a first switch module, a second switch module, a clock generation module, and a voltage regulation module;

the first switch module is electrically connected with the second pixel electrode group and used for receiving a first clock signal;

the second switch module is electrically connected with the first common electrode unit and is used for receiving a second clock signal;

the first pixel electrode group is electrically connected with the second pixel electrode group and is electrically connected with the clock generation module; the clock generation module is used for outputting a target clock signal;

the second common electrode unit is electrically connected with the first end of the voltage regulating module;

the second end of the voltage regulating module is respectively and electrically connected with the third common electrode unit and the grounding end;

and the third end of the voltage regulating module is respectively and electrically connected with the third pixel electrode group and the clock generating module.

In an alternative implementation, the clock generation module includes a first transistor and a second transistor;

the drain electrode of the first transistor is used for receiving a high-level signal, and the drain electrode of the second transistor is used for receiving a low-level signal;

the source electrode of the first transistor is electrically connected with the source electrode of the second transistor, and is used as the output end of the clock generation module for outputting a target clock signal;

the grid electrode of the first transistor is respectively and electrically connected with the first pixel electrode group and the second pixel electrode group;

and the grid electrode of the second transistor is respectively and electrically connected with the third pixel electrode group and the clock generation module.

In an alternative implementation, the first switch module includes a third transistor, and the second switch module includes a fourth transistor;

the grid electrode and the drain electrode of the third transistor are electrically connected, and the source electrode of the third transistor is electrically connected with the second pixel electrode group;

the gate and the drain of the fourth transistor are electrically connected, and the source of the fourth transistor is electrically connected to the first common electrode unit.

In an alternative implementation, the voltage regulation module includes a fifth transistor and a sixth transistor;

the grid electrode and the drain electrode of the fifth transistor are electrically connected;

a gate and a drain of the sixth transistor are electrically connected;

the drain electrode of the fifth transistor and the source electrode of the sixth transistor are both electrically connected with the second common electrode unit;

a source electrode of the fifth transistor is respectively and electrically connected with the third common electrode unit and the grounding terminal;

and the drain electrode of the sixth transistor is respectively and electrically connected with the third pixel electrode group and the clock generation module.

In an alternative implementation, the non-display area further includes a fourth pixel electrode group and a fourth common electrode block;

the fourth pixel electrode group and the fourth common electrode block form a fourth capacitor which is connected in parallel with the first capacitor formed by the first pixel electrode group and the first common electrode unit.

In a second aspect, an embodiment of the present application provides a display device, including a source driver and the display panel of the first aspect;

the source driver is electrically connected with the display area of the display panel.

The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:

the display panel that this application embodiment provided, display panel includes display area and isolation region, the isolation region is located one side of display area, the isolation region can include first isolation region and/or second isolation region, and first isolation region and/or second isolation region separate with the display area respectively. The first isolation region comprises at least one row of pixel units and a first common electrode block, the second isolation region comprises at least one column of pixel units and a second common electrode block, each pixel unit comprises a pixel electrode, and the pixel electrode and the first common electrode block or the second common electrode block form a capacitor. The capacitor can store electric charge, and can be used for voltage stabilization, decoupling, filtering, analog signal generation circuits and the like, so that signal pulling of the display panel can be improved, and defects such as pits and noise can be reduced.

In addition, by optimizing the display panel, only the area where at least one row or one column of pixel units is located is used as an isolation area to be separated from the display area, the overall position layout of the pixel array of the whole display panel is not required to be changed, the capacitor is directly manufactured in the pixel array process of the display panel, an external capacitor is not required, and meanwhile, the change cost can be reduced.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

FIG. 3 is an equivalent circuit diagram of a pixel unit according to an embodiment of the present application;

fig. 4a is a schematic structural diagram of another display panel provided in the embodiment of the present application;

fig. 4b is a schematic structural diagram of another display panel according to an embodiment of the present disclosure.

FIG. 5 is a circuit diagram of a single analog signal generating circuit according to an embodiment of the present application;

fig. 6 is an equivalent circuit diagram of a single analog signal generating circuit in fig. 5 according to an embodiment of the present application.

Reference numerals:

100-display panel, 10-first isolation region, 20-display region, 30-non-display region, 40-second isolation region;

11-pixel unit, 111-first pixel electrode group, 112-second pixel electrode group, 113-third pixel electrode group, 12-first common electrode block, 121-first common electrode unit, 122-second common electrode unit, 123-third common electrode unit;

31-GOA circuit, 32-first switch module, 33-second switch module, 34-clock generation module and 35-voltage regulation module.

Detailed Description

The present application is described in detail below and examples of embodiments of the present application are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements with the same or similar functionality throughout. In addition, if a detailed description of the known art is unnecessary for the features of the present application shown, it is omitted. The embodiments described below with reference to the accompanying drawings are exemplary only for explaining the present application and are not construed as limiting the present application.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The problems of ESD (Electro-Static discharge) and signal pull of the liquid crystal display panel are not solved at present. Particularly, a small-sized liquid crystal display panel with high wiring overlapping has signal pulling, resulting in occurrence of defects such as pits and noise.

The inventor of the application researches and discovers that the capacitor is a good component for voltage stabilization, decoupling and filtering, and can well solve the problems of pits, noise and the like caused by signal pulling of the existing liquid crystal display panel.

The inventor of the present application considers that the capacitor can be made in the array process of the liquid crystal display panel because the liquid crystal display panel cannot be externally hung with the capacitor. The capacitance value between the pixel electrode and the common electrode in the liquid crystal display panel is larger, and the liquid crystal display panel can well store more charges, so that the liquid crystal display panel can be used for voltage stabilization, decoupling, filtering and the like, and can solve the problems of pits, noise and the like caused by signal pulling in the prior art.

Therefore, the display panel and the display device provided by the application aim at solving the technical problem that in the prior art, signal pulling causes defects such as pits and noise.

The following describes the technical solution of the present application and how to solve the above technical problems in detail by specific embodiments.

The embodiment of the present application provides a display panel 100, as shown in fig. 1, fig. 4a and fig. 4b, the display panel 100 includes a display area 20 and an isolation area, the isolation area is located at one side of the display area 20; in a specific implementation, the display panel 100 is a liquid crystal display panel.

The isolation regions comprise a first isolation region 10, and/or a second isolation region 40; the second isolation region 40 may be located at the leftmost side or the rightmost side of the display region 20.

The first isolation region 10 includes at least one row of pixel cells 11 and a first common electrode block 12; the first common electrode block is disconnected from the common electrode block (e.g., the VCOM block in fig. 2) of the display region 20.

The second isolation region 40 includes at least one column of pixel units and a second common electrode block (not shown in the drawings); the second common electrode block is disconnected from the common electrode block of the display area 20.

Each pixel cell 11 includes a pixel electrode forming a capacitance with the first common electrode block 12 or with the second common electrode block.

The display panel 100 provided in the embodiment of the present application includes a display area 20 and an isolation area, where the isolation area is located at one side of the display area, and the isolation area may include a first isolation area 10 and/or a second isolation area 40, and the first isolation area 10 and/or the second isolation area 40 are isolated from the display area 20, respectively. The first isolation region 10 includes at least one row of pixel units 11 and a first common electrode block 12, the second isolation region 40 includes at least one column of pixel units and a second common electrode block, each pixel unit 11 includes a pixel electrode, and the pixel electrode forms a capacitance with the first common electrode block 12 or with the second common electrode block. The capacitor can store electric charge, and can be used for voltage stabilization, decoupling, filtering, analog signal generation circuits and the like, so that signal pulling of the display panel can be improved, and defects such as pits and noise can be reduced.

Moreover, by optimizing the display panel, only the region where at least one row or one column of pixel units is located is separated from the display region as an isolation region, the overall position layout of the pixel array of the whole display panel 100 is not required to be changed, the capacitor is directly manufactured in the pixel array process of the display panel 10, an external capacitor is not required, and meanwhile, the change cost can be reduced.

It should be noted that the pixel unit included in the first isolation region is a first row of pixel units in the display region 20, as shown in fig. 2, the first common electrode block 12 is disconnected from the common electrode block of the display region 20, specifically, the first common electrode block 12 and the common electrode block of the display region 20 are manufactured by using the same composition process, and at this time, the obtained common electrode block is an integrally continuous common electrode block, and then, the common electrode block at the position corresponding to the first row of pixel units 11 is disconnected from the common electrode blocks at other positions to form the common electrode blocks of the first common electrode block 12 and the display region 20 that are separated.

Note that the DP side in fig. 1, 2, 4a, and 4b is a side where an active driver (e.g., a source driver) is provided, and the DPO side is a side opposite to the DP side.

In fig. 2, the first isolation region 10 is located on the DPO side of the display panel 100, and the display region 20 is located on the DP side of the display panel 100.

In some embodiments, as shown in fig. 2, for the first isolation region 10, at least one first scan line (e.g., G0 in fig. 2) and a plurality of first traces (e.g., two adjacent first traces in fig. 2 are connected together to form one trace X1-X6) are included;

the pixel units 11 in a row of pixel units are all electrically connected with a first scanning line, and each pixel unit 11 in a row of pixel units is respectively electrically connected with a first wiring; the first trace is disconnected from the data lines (e.g., the data lines D1-D12 in fig. 2) of the display area 20; the first scanning line is used for receiving a first set voltage, and the first wire is used for electrically connecting the voltage stabilizing circuit to be stabilized; the first common electrode block 12 is electrically connected to the ground GND.

It should be noted that, as shown in fig. 2, the first trace is disconnected from the data line of the display area 20, specifically, the first trace and the data line of the display area 20 are manufactured by the same composition process, and at this time, the obtained data line is an integral continuous data line, and then, the data line at the position corresponding to the first row of pixel units is disconnected from the data lines at other positions to form the data line of the separated first trace and the display area 20, where the first trace does not receive the data signal.

It should be noted that, in order to reduce the influence on the display of the display panel, in the embodiment of the present application, the first isolation region 10 includes a row of pixel units 11, and correspondingly, the first isolation region 10 includes a scan line G0, the scan line G0 is configured to receive a first setting voltage, where the first setting voltage is, for example, a certain constant voltage value (which needs to be specifically set according to an actual situation), and in the specific implementation, if the number of columns of the row of pixel units 11 is M, M first routing lines may be correspondingly set in the embodiment of the present application, and each first routing line is correspondingly connected to one pixel unit 11.

In some embodiments, for the second isolation region 40; the second isolation region 40 includes at least one second trace and a plurality of second scan lines, the pixel units in a row of pixel units are electrically connected to the one second trace, and each pixel unit in a row of pixel units is electrically connected to the one second scan line; the second scanning line is disconnected with the scanning line of the display area; the second scanning line is used for receiving a second set voltage; the second wire is used for electrically connecting the voltage stabilizing circuit to be stabilized; the second common electrode block is electrically connected with the grounding end; (not shown in the figure).

Alternatively, as shown in fig. 4a and 4b, the display panel 100 includes a non-display region 30 surrounding the display region 20 and the isolation region 40, the non-display region 30 is provided with a GOA circuit 31, and a capacitor formed by the pixel unit and the second common electrode block is connected to the GOA circuit.

It should be noted that the second trace is disconnected from the scan line of the display area 20, specifically, the second trace and the scan line of the display area 20 are manufactured by the same composition process, and at this time, the obtained scan line is an integrally continuous scan line, and then the scan line at the position corresponding to the first column of pixel units is disconnected from the scan lines at other positions to form the scan line of the second trace and the display area 20, which are separated from each other, and the second trace does not receive the scan signal.

In some embodiments, for the first isolation region 10, each pixel cell further comprises a transistor; the first pole of the transistor is electrically connected with the first routing; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the first scanning line.

For the second isolation region 40, each pixel cell also includes a transistor; the first electrode of the transistor is electrically connected with the second routing; the second pole of the transistor is electrically connected with the pixel electrode; the control electrode of the transistor is electrically connected with the second scanning line.

Alternatively, the Transistor is a TFT (Thin Film Transistor), and the "control electrode" of the Transistor in the pixel unit 11 specifically refers to a gate electrode of the Transistor, the "first electrode" specifically refers to a source electrode or a drain electrode of the Transistor, and correspondingly, the "second electrode" specifically refers to a drain electrode or a source electrode of the Transistor.

Illustratively, as shown in fig. 3, the first pole of the transistor TFT is electrically connected to the first trace (as shown in fig. 2, two adjacent first traces are connected together to form one of the first traces X1); a second electrode of the transistor TFT is electrically connected to the pixel electrode; the control electrode of the transistor TFT is electrically connected to a first scan line (e.g., the first scan line G0 in fig. 2).

In some embodiments, for the first isolation region, the at least one row of pixel cells comprises one row of pixel cells; at least two adjacent first wires are electrically connected together and are electrically connected with the voltage stabilizing circuit to be stabilized.

As shown in fig. 2, in the embodiment of the present application, the first isolation region 10 includes a row of pixel units 11, correspondingly, the first isolation region 10 includes a scan line G0, the scan line G0 is configured to receive a first setting voltage, for example, the first setting voltage is a certain constant voltage value (which needs to be specifically set according to actual conditions), in specific implementation, if the number of columns of the row of pixel units 11 is M, M first traces may be correspondingly disposed in the embodiment of the present application, and each first trace is correspondingly connected to one pixel unit 11.

As shown in fig. 2, two adjacent first traces in the embodiment of the present application are electrically connected together to form one trace X1-X6. The traces X1-X6 are respectively connected with different voltage-stabilizing circuits to be stabilized. In fig. 2, VCOM denotes a common electrode, D1, D2 … … D12 denote data lines of the display area 20, and G1 and G2 denote scan lines of the display area 20. The control electrodes of the transistors of the pixel units 11 in the first row are all electrically connected with the scanning line G0, and each transistor is electrically connected with one first routing line. Two adjacent first traces are electrically connected together to form one trace, for example, traces X1, X2, X3, X4, X5 and X6, which are all formed by connecting two adjacent first traces together.

Fig. 2 is merely an example, and of course, other numbers of first traces, such as

adjacent traces

3, 4, 5, etc., may also be electrically connected, and this application is not limited thereto.

The traces X1, X2, X3, X4, X5, and X6 may be electrically connected to different voltage-stabilizing circuits, respectively, and the voltage-stabilizing circuit may be a constant voltage circuit, such as a VCOM (common electrode) circuit, a VGH circuit, a VDD circuit, etc., to perform voltage-stabilizing filtering on VCOM, VGH, and VDD, so as to improve signal pulling, thereby reducing occurrence of defects such as pits and noise.

As shown in fig. 2 and 3, the transistor TFT of each pixel unit 11 in the first row is equivalent to a variable resistor R, and the capacitance formed by the pixel electrode of each pixel unit 11 in the first row and the first common electrode block 12 is equivalent to a capacitance C. The electrically connected scan line G0 of the first row of pixel cells 11 receives a set voltage, which is a constant voltage.

The embodiment of the application can control the leakage of the transistor TFT by changing the voltage value of the set voltage, that is, the transistor TFT is equivalent to a variable resistor R controlled by a voltage. However, the capacitance value of the capacitor formed by the pixel electrode of the single pixel unit 11 and the first common electrode block 12 is limited, and therefore, the entire capacitance value can be increased by connecting the adjacent pixel units 11 in parallel, so as to achieve the optimal voltage stabilization and filtering effects.

The embodiment of the application carries out voltage stabilization and filtering through the increase of the capacitance value of the parallel capacitor, utilizes the capacitor to store charges to improve the ESD (electrostatic Discharge) resistance, and can filter out high-frequency noise waves at the same time, so that the voltage stability of the voltage stabilizing circuit is better, and the service life of the display panel 100 and an IC (chip) is prolonged.

In some embodiments, as shown in fig. 2, further comprising: and a light shielding member for shielding at least one row of pixel units 11 of the first isolation region 10.

Optionally, the light-shielding part is a Tape adhesive, which is a kind of light-shielding adhesive Tape, is mainly used in an optical display device to perform the functions of pasting and shielding light, and is widely used in electronic display screens of notebook computers, mobile phones, PDAs, numbers and the like. Specifically, the liquid crystal display screen of the display panel 100 can be glued with Tape to perform the functions of sticking and shading.

In the embodiment of the present application, the first isolation region 10 is shielded by the light shielding member, so that there is no interference to the display of the display panel 100, and the display quality of the entire display panel 100 is not affected.

Optionally, the display panel 100 further includes a plurality of marks, which are used for marking the pixel unit 11, so as to mark different voltage-to-be-stabilized circuits electrically connected to the pixel unit 11.

For example, in fig. 2, the trace X1 is electrically connected to a first voltage stabilizing circuit to be tested, the trace X2 is electrically connected to a second voltage stabilizing circuit to be tested, the trace X3 is electrically connected to a third voltage stabilizing circuit to be tested, the trace X4 is electrically connected to a fourth voltage stabilizing circuit to be tested, the trace X5 is electrically connected to a fifth voltage stabilizing circuit to be tested, and the trace X6 is electrically connected to a sixth voltage stabilizing circuit to be tested.

The mark may be a pixel serial number, and the pixel serial number may be a colored pixel serial number, for example, a red pixel serial number 1 marks a first pixel unit and a second pixel unit in the first row of pixel units 11, so as to mark the first voltage regulator circuit to be regulated.

According to the embodiment of the application, by setting the plurality of identifiers, the pixel unit 11 can be identified, and then different voltage stabilizing circuits to be electrically connected with the pixel unit 11 can be identified, so that whether the voltage stabilizing circuits to be electrically connected with the pixel unit 11 are normal or not can be roughly confirmed through the brightness of the pixel unit 11.

In some embodiments, for the second isolation region 40, when the non-display region 30 is provided with the GOA circuit 31:

if the second isolation region 40 includes at least one column of pixel units and a second common electrode block;

the plurality of pixel electrodes of at least one column of pixel units includes a first pixel electrode group 111, a second pixel electrode group 112, and a third pixel electrode group 113.

The second common electrode block includes a first common electrode unit 121, a second common electrode unit 122, and a third common electrode unit 123; the first, second, and third

common electrode units

121, 122, and 123 are all disconnected from each other.

The first pixel electrode group 111 and the first common electrode unit 121 form a first capacitor; the second pixel electrode group 112 and the second common electrode unit 122 form a second capacitor; the third pixel electrode group 113 and the third common electrode unit 123 form a third capacitance.

Each pixel electrode group includes at least one pixel electrode, and at least one pixel electrode is connected together.

In some embodiments, as shown in fig. 5 and 6, the GOA circuit 31 includes a first switching module 32, a second switching module 33, a clock generation module 34, and a voltage regulation module 35.

The first switch module 32 is electrically connected to the second pixel electrode group 112 and is configured to receive a first clock signal CLKa;

the second switching module 33 is electrically connected to the first common electrode unit 121 and configured to receive a second clock signal CLKb;

the first pixel electrode group 111 is electrically connected with the second pixel electrode group 112, and is electrically connected with the clock generation module 34; the clock generation module 34 is used for outputting a target clock signal CLK 1;

the second common electrode unit 122 is electrically connected to a first end of the voltage regulating module 35;

a second end of the voltage adjusting module 35 is electrically connected to the third common electrode unit 123 and the ground GND;

the third end of the voltage regulating module 35 is electrically connected to the third pixel electrode group 113 and the clock generating module 34.

As shown in fig. 5 and 6, the first pixel electrode group 111 and the first common electrode unit 121 form a first capacitance C1; the second pixel electrode group 112 and the second common electrode unit 122 form a second capacitor C2; the third pixel electrode group 113 and the third common electrode unit 123 form a third capacitance C3.

The embodiment of the present application utilizes the capacitance formed by the pixel electrode of the second isolation region 40 and the second common electrode block to be applied in a GOA circuit to generate an analog signal generating circuit, such as a square wave generating circuit (CLK circuit, STV circuit, etc.). The method can reduce EOS (Electrical Over Stress) and ESD (electrostatic Discharge) risks, reduce the total length of the high-level line, and further reduce power consumption.

As shown in fig. 5 and fig. 6, the capacitor formed by the pixel electrode of the second isolation region 40 and the second common electrode block is applied to the GOA circuit, and the working principle of the square wave generating circuit is as follows: in a first period, when the first clock signal CLKa is at a high level, the first switch module 32 is turned on, and transmits the first clock signal CLKa at the high level to the first node a, so as to charge the first capacitor C1; when the second clock signal CLKb is at a high level, the second switching module 33 is turned on, and transmits the high-level second clock signal CLKb to the first capacitor C1, and the first capacitor C1 raises the voltage of the first node a in a bootstrap manner according to the high-level second clock signal CLKb, so that the clock generating module 34 outputs a first level signal;

in a second time period, when at least one of the first clock signal CLKa and the second clock signal CLKb is at a low level, at least one of the first switch module 32 and the second switch module 33 is turned off, and the clock generation module 34 outputs a second level signal; the first level signal and the second level signal are signals with opposite level logic states and alternate to form the target clock signal CLK 1.

In some embodiments, the clock generation module 34 includes a first transistor T1 and a second transistor T2;

a drain of the first transistor T1 is for receiving a high level signal VGH, and a drain of the second transistor T2 is for receiving a low level signal VGL;

a source of the first transistor T1 is electrically connected to a source of the second transistor T2, and serves as an output terminal of the clock generation block 34 for outputting the target clock signal CLK 1;

a gate of the first transistor T1 electrically connected to both the first pixel electrode group 111 and the second pixel electrode group 112, respectively;

the gates of the second transistors T2 are electrically connected to the third pixel electrode group 113 and the clock generation module 34, respectively.

In some embodiments, the first switch module 32 includes a third transistor T3, and the second switch module 33 includes a fourth transistor T4;

the gate and the drain of the third transistor T3 are electrically connected, and the source of the third transistor T3 is electrically connected to the second pixel electrode group 112;

the gate and the drain of the fourth transistor T4 are electrically connected, and the source of the fourth transistor T4 is electrically connected to the first common electrode unit 121.

In some embodiments, the voltage regulation module 35 includes a fifth transistor T5 and a sixth transistor T6;

the gate and the drain of the fifth transistor T5 are electrically connected;

the gate and the drain of the sixth transistor T6 are electrically connected;

a drain electrode of the fifth transistor T5 and a source electrode of the sixth transistor T6, both of which are electrically connected to the second common electrode unit 122;

a source electrode of the fifth transistor T5 electrically connected to the third common electrode unit 123 and the ground terminal GND, respectively;

the drain of the sixth transistor T6 is electrically connected to the third pixel electrode group 113 and the clock generation module 34.

Alternatively, the transistors in the GOA circuit 31 may be Thin Film Transistors (TFTs), and the transistors in the GOA circuit 31 may be all N-type transistors, and the same manufacturing process may be used to manufacture the transistors at the same time, so as to shorten the production cycle of the display panel. It should be noted that all the transistors of the GOA circuit 31 are N-type thin film transistors, which is only a preferred embodiment of the present invention, and this does not limit the technical solution of the present invention. In this embodiment, at least a portion of the transistors may also be selectively configured as P-type thin film transistors.

Specifically, as shown in fig. 6, when the first clock signal CLK a is at the rising delay, the third transistor T3 is turned on, at which time the first capacitor C1 starts to store charges, the potential at the first node a rises to 10V (volts), when the second clock signal CLK b is at the high level, the voltage at the first node a will rise further until the voltage at the first node a rises to 20V, the gate-source voltage Vgs1 > Vth1 of the first transistor T1, Vth1 is the threshold voltage of the first transistor T1, at which time the first transistor T1 is turned on (i.e., turned on), the second transistor T2 is turned off, the voltage of the high-level signal VGH falls directly to the point b, and at which time the target clock signal CLK1 is the high-level signal VGH. When the first clock signal CLK a and the second clock signal CLK b are at other levels, the gate-source voltage Vgs1 of the first transistor T1 is less than Vth1, Vth1 is the threshold voltage of the first transistor T1, the gate-source voltage Vgs2 of the second transistor T2 is greater than Vth2, Vth2 is the threshold voltage of the second transistor T2, the first transistor T1 is turned off, the second transistor T2 is turned on, the voltage of the low-level signal VHL directly falls to point b, and the target clock signal CLK1 is the low-level signal VGL.

The first clock signal CLK a and the second clock signal CLK b may be provided through an IC chip in the display panel. The fifth transistor T5 and the sixth transistor T6 each function as a diode and perform unidirectional conduction.

The target clock signal CLK1 can be applied to the GOA circuit 31, and provides the input clock signal (i.e., the target clock signal CLK1) to the GOA circuit 31, and the GOA circuit 31 outputs the scan signals Gate1, Gate2, and Gate3 … … to each row of pixel cells in the display area of the display panel by using the clock signal (i.e., the target clock signal CLK 1).

The embodiment of the application directly generates the target clock signal CLK1 by using the high level signal VGH and the low level signal VGL. Therefore, the target clock signal CLK1 is not required to be directly generated by the IC, so that the influence of the back-end pseudo-capacitor on the pulling of the signal is reduced, and the abnormal work of the IC caused by the abnormal back-end capacitor is not influenced, thereby reducing the influence on the IC. Meanwhile, the number of high-voltage bus circuits is reduced, so that the effect of reducing power consumption can be achieved.

The square wave generation circuit of the embodiment of the application adopts the quick switching of the capacitor and the transistor TFT, so that the ESD and EOS resistance can be enhanced. The ESD and EOS are generated by abnormal charges, and the square wave generating circuit can limit the movement of the charges.

In some embodiments, the non-display area 20 further includes a fourth pixel electrode group and a fourth common electrode block;

the fourth pixel electrode group and the fourth common electrode block form a fourth capacitor, and the first capacitor C1 is formed in parallel with the first pixel electrode group 111 and the first common electrode unit 121, so that the capacitance value can be increased for the function of raising the voltage. That is, the fourth pixel electrode group is electrically connected to the first pixel electrode group 111; the fourth common electrode block is electrically connected to the first common electrode unit 121. The fourth pixel electrode group includes at least one pixel electrode.

Alternatively, the non-display region may further include a fifth capacitance formed by the fifth pixel electrode group and the fifth common electrode block in parallel with the second pixel electrode group 112 and the second common electrode unit 122 forming the second capacitance C2.

Alternatively, the non-display area may further include a sixth capacitance formed by a sixth pixel electrode group and a sixth common electrode block, in parallel with the third pixel electrode group 113 and the third common electrode unit 123 to form a third capacitance C3.

Various capacitance values of the capacitor can be made in the non-display area 30 by the pixel electrode and the common electrode block located in the non-display area 30 for various square wave generating circuits.

Based on the same inventive concept, an embodiment of the present application provides a display device, which includes a source driver and the display panel 100 provided in any of the embodiments above;

the source driver is electrically connected to the display region 20 of the display panel 100.

As shown in fig. 1, the source driver is located at the DP side of the display panel 100, and is electrically connected to the display area 20 of the display panel 100 for outputting data signals to each pixel unit of the display area 20.

The display device provided by the embodiment of the present application has the same inventive concept and the same advantageous effects as the previous embodiments, and the content not shown in detail in the display device can refer to the previous embodiments, and is not described herein again.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

Moreover, by optimizing the display panel, only the area where at least one row or one column of pixel units is located is separated from the display area as an isolation area, the overall position layout of the pixel array of the whole display panel 100 does not need to be changed, the capacitor is directly manufactured in the pixel array process of the display panel 10, an external capacitor is not needed, and meanwhile, the change cost can be reduced.

Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, various operations, methods, steps, measures, schemes in the various processes, methods, procedures that have been discussed in this application may be alternated, modified, rearranged, decomposed, combined, or eliminated. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.

In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of execution is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a few embodiments of the present application and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present application, and that these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A display panel is characterized by comprising a display area and an isolation area, wherein the isolation area is positioned at one side of the display area;

the second isolation region comprises at least one column of pixel units and a second common electrode block; the second common electrode block is disconnected with the common electrode block of the display area;

each pixel unit comprises a pixel electrode, and the pixel electrode and the first common electrode block or the second common electrode block form a capacitor.

2. The display panel according to claim 1, wherein the first isolation region comprises at least one first scan line and a plurality of first traces;

the pixel units in one row of pixel units are electrically connected with a first scanning line, and each pixel unit in one row of pixel units is electrically connected with a first wiring line; the first routing wire is disconnected with the data wire of the display area; the first scanning line is used for receiving a first set voltage, and the first wire is used for electrically connecting the voltage stabilizing circuit to be stabilized; the first common electrode block is electrically connected with a grounding terminal.

3. The display panel according to claim 1, wherein for the second isolation region;

the second isolation region comprises at least one second wiring and a plurality of second scanning lines, the pixel units in one row of pixel units are electrically connected with the second wiring, and each pixel unit in one row of pixel units is electrically connected with one second scanning line; the second scanning line is disconnected with the scanning line of the display area; the second scanning line is used for receiving a second set voltage; the second wire is used for electrically connecting the voltage stabilizing circuit to be stabilized; the second common electrode block is electrically connected with a grounding end;

or the display panel comprises a non-display area surrounding the display area and the isolation area, the non-display area is provided with a GOA circuit, and the pixel unit and the capacitor formed by the second common electrode block are connected with the GOA circuit.

4. The display panel according to claim 2 or 3,

for the first isolation region, each of the pixel cells further comprises a transistor; a first electrode of the transistor is electrically connected with the first routing; a second electrode of the transistor is electrically connected to the pixel electrode; and the control electrode of the transistor is electrically connected with the first scanning line.

For the second isolation region, each of the pixel cells further comprises a transistor; a first electrode of the transistor is electrically connected with the second routing wire; a second electrode of the transistor is electrically connected to the pixel electrode; and the control electrode of the transistor is electrically connected with the second scanning line.

5. The display panel of claim 2, wherein for the first isolation region,

the at least one row of pixel units comprises a row of pixel units;

6. The display panel according to claim 2, further comprising:

and the shading part is used for shading at least one row of pixel units of the first isolation region.

7. The display panel according to claim 3, wherein for the second isolation region, when the non-display region is provided with a GOA circuit:

the plurality of pixel electrodes of the at least one column of pixel units comprise a first pixel electrode group, a second pixel electrode group and a third pixel electrode group; each pixel electrode group comprises at least one pixel electrode;

the second common electrode block comprises a first common electrode unit, a second common electrode unit and a third common electrode unit; the first common electrode unit, the second common electrode unit and the third common electrode unit are disconnected from each other;

8. The display panel according to claim 7, wherein the GOA circuit comprises a first switch module, a second switch module, a clock generation module, and a voltage regulation module;

9. The display panel according to claim 8, wherein the clock generation block comprises a first transistor and a second transistor;

10. The display panel according to claim 8, wherein the first switch module comprises a third transistor, and wherein the second switch module comprises a fourth transistor;

the grid electrode and the drain electrode of the fourth transistor are electrically connected, and the source electrode of the fourth transistor is electrically connected with the first common electrode unit.

11. The display panel according to claim 8, wherein the voltage adjustment module comprises a fifth transistor and a sixth transistor;

a gate and a drain of the fifth transistor are electrically connected;

a gate and a drain of the sixth transistor are electrically connected;

a drain electrode of the fifth transistor and a source electrode of the sixth transistor, both of which are electrically connected to the second common electrode unit;

a source of the fifth transistor is electrically connected to the third common electrode unit and a ground terminal, respectively;

12. The display panel according to claim 8, wherein the non-display region further comprises a fourth pixel electrode group and a fourth common electrode block;

the fourth pixel electrode group and the fourth common electrode block form a fourth capacitor which is connected in parallel with a first capacitor formed by the first pixel electrode group and the first common electrode unit.

13. A display device comprising a source driver and the display panel according to any one of claims 1 to 12;