CN100476941C

CN100476941C - Method of driving a shift register, a shift register, a liquid crystal display device having the shift register

Info

Publication number: CN100476941C
Application number: CNB038124777A
Authority: CN
Inventors: 李栢远; 文胜焕
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2002-06-15
Filing date: 2003-06-13
Publication date: 2009-04-08
Anticipated expiration: 2023-06-13
Also published as: CN1860519A; KR20030095854A; KR100853720B1

Abstract

In a shift register and LCD device having the shift register that may be employed in the liquid crystal display device having a large screen size and a large resolution, the shift register includes stages connected with each other and each of the stages have a carry buffer for generating a carry signal. The pull-down transistor of each of the stages of the shift register is divided into a first pull-down transistor and a second pull-down transistor. A power voltage Vona larger than the power voltage Von applied to a clock generator is applied to the shift register. A signal delay due to the RC delay of the gate lines may be minimized, the shift register is independent of the variation of the threshold voltage of the TFTs, and image display quality may not be deteriorated.

Description

Drive shift register method, shift register, have the liquid crystal display of shift register

Technical field

The present invention relates to a kind of liquid crystal display (LCD) equipment that drives method, the shift register of shift register and have this shift register.More particularly, the present invention relates to driving method, the shift register of the shift register in a kind of amorphous silicon (a-Si) tft liquid crystal display device (non-crystalline silicon tft LCD) that can be used for having large display screen and have liquid crystal display (LCD) equipment of this shift register.

Background technology

TFT LCD equipment is divided into non-crystalline silicon tft LCD (or a-Si TFT LCD) equipment and multi-crystal TFT LCD equipment two classes.Compare with non-crystalline silicon tft LCD equipment, multi-crystal TFT LCD (or poly-Si TFT LCD) equipment has lower power consumption and low price, but makes by the technology of complexity.Thereby multi-crystal TFT LCD is used for having the display device such as the mobile phone of small display.

Non-crystalline silicon tft LCD equipment can provide large display screen and high finished product rate (or high productivity), and is used for having display device such as laptop computer, LCD monitor or the high definition television (HDTV) of large display screen.

Fig. 1 is the synoptic diagram that traditional polycrystalline SiTFT LCD is shown, and Fig. 2 is the synoptic diagram that traditional amorphous silicon film transistor LCD is shown.

As shown in Figure 1, multi-crystal TFT LCD equipment is included in the multi-crystal TFT pel array that forms on the glass substrate 10.On glass substrate 10, form data driving circuit 12 and gate driver circuit 14.IC printed board 20 is connected to terminal part 16 by grout cable 18, thereby can reduce the manufacturing cost of multi-crystal TFT LCD equipment because data driving circuit 12 and gate driver circuit 14 are integrated on the glass substrate 10, but can reduce the thickness and the minimizing power dissipation of multi-crystal TFT LCD equipment.

Yet, as shown in Figure 2, in non-crystalline silicon tft LCD equipment, data driver chip 34 is installed on the flexible printed circuit board 32 by the chip on the film (COF), and data pcb 36 is connected to data line terminal on the non-crystalline silicon tft pel array by flexible printed circuit board 32.Gate drivers chip 404 is installed on the flexible printed circuit board 32 by the chip on the film (COF), and gate pcb 42 is connected to gate line terminal on the non-crystalline silicon tft pel array by flexible printed circuit board 40.

Non-crystalline silicon tft LCD equipment has the advantage of yield rate (or throughput rate) aspect, but has the shortcoming of manufacturing cost and thickness aspect.

In addition, at the non-crystalline silicon tft LCD equipment that is used for having display image on the high-resolution large display screen, gate driver circuit need be to carrying out rapid discharge at the electric charge that is connected to accumulation on the gate line of pixel (or charging).Gate line has capacity load.

Yet, when traditional gate driver circuit was used for having the non-crystalline silicon tft LCD equipment of large display screen, the deterioration of display quality may take place.

Summary of the invention

Thereby the present invention is provided and is used for eliminating basically one or more problems that restriction and shortcoming owing to correlative technology field cause.

An aspect of of the present present invention provides a kind of shift register, and it can drive and be used for having the non-crystalline silicon tft LCD equipment of display image on the high-resolution large display screen.

Another aspect of the present invention provides a kind of liquid crystal display with above-mentioned shift register.

Another aspect of the present invention provides a kind of method that drives above-mentioned shift register.

In one aspect of the invention, provide a kind of shift register, it comprises the level of a plurality of cascades (cascade-connected).These grades receive first clock signal and the second clock signal produces a plurality of scan line driving signals that are used to select the multi-strip scanning line with order.Each the level comprise carry impact damper (carry buffer), on draw (pull-up) partly, drop-down (pull-down) partly, on draw driver portion and pull-down driver part.The carry impact damper provides carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases.Last pull portion provides first scan line driving signal corresponding to first clock signal or second clock signal to lead-out terminal.Drop-down part provides first supply voltage to lead-out terminal.On draw carry signal that driver portion response provides from previous stage and pull portion in the conducting, and second scan line driving signal of response next stage and turn-off pull portion.The carry signal that the pull-down driver partial response provides from previous stage and turn-off drop-down part, and second scan line driving signal of response next stage and pull portion in the conducting.

In another aspect of this invention, provide a kind of liquid crystal display, it comprises array of display cells, data driving circuit and gate driver circuit.Array of display cells is formed on the transparency carrier and comprises many gate lines, many data lines and a plurality of on-off element.On-off element is coupled in gate line and data line.Data driving circuit provides picture signal to every data line.Gate driver circuit comprises shift register, and this shift register comprises the level of a plurality of cascades.These grades receive first clock signal and the second clock signal produces a plurality of gate line drive signals that are used to select gate line with order.Each level comprises the carry impact damper, goes up pull portion, drop-down part, on draw driver portion and pull-down driver part.The carry impact damper provides carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases.Last pull portion provides first grid drive signal corresponding to first clock signal or second clock signal to lead-out terminal.Drop-down part provides first supply voltage to lead-out terminal.On draw carry signal that driver portion response provides from previous stage and pull portion in the conducting, and the second grid line drive signal of response next stage and turn-off pull portion.The carry signal that the pull-down driver partial response provides from previous stage and turn-off drop-down part, and the second grid line drive signal of response next stage and pull portion in the conducting.

In another aspect of this invention, provide a kind of method that drives shift register.This shift register comprises the level of a plurality of cascades.These grades receive first clock signal and the second clock signal produces a plurality of scan line driving signals that are used to select the multi-strip scanning line with order.Provide carry signal to next stage, and the second clock signal has and the first clock signal opposite phases corresponding to first clock signal or second clock signal.Then, response produces first scan line driving signal corresponding to first clock signal or second clock signal from the carry signal of previous stage output.Response reduces from second scan line driving signal of next stage output from first voltage level when first scan line driving signal of prime output.

In another aspect of this invention, provide a kind of shift register, it comprises the level of a plurality of cascades.The first order receives scan start signal, and these grades receive first clock signal and the second clock signal produces a plurality of scan line driving signals that are used to select the multi-strip scanning line with order.Each level comprises the first carry impact damper, goes up pull portion, drop-down part, on draw driver portion and the pull-down driver part and the second carry impact damper.The first carry impact damper provides first carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases.Last pull portion provides first scan line driving signal corresponding to first clock signal or second clock signal to first lead-out terminal.Drop-down part provides first supply voltage to first lead-out terminal.On draw driver portion response pull portion from second carry signal of the first carry impact damper output of previous stage and in the conducting, and second scan line driving signal of response next stage and turn-off pull portion.First carry signal that the pull-down driver partial response provides from the first carry impact damper of previous stage and turn-off drop-down part, and second scan line driving signal of response next stage and pull portion in the conducting.The second carry impact damper reduces by first voltage level of second carry signal, and exports first carry signal to put on pull portion from the first carry impact damper of previous stage.

In another aspect of this invention, provide a kind of liquid crystal display, it comprises array of display cells, data driving circuit and gate driver circuit.Array of display cells is formed on the transparency carrier and comprises many gate lines, many data lines and a plurality of on-off element.On-off element is coupled in gate line and data line.Data driving circuit provides picture signal to every data line.Gate driver circuit comprises shift register, and this shift register comprises the level of a plurality of cascades.These grades receive first clock signal and the second clock signal produces a plurality of gate line drive signals that are used to select gate line with order.Each level comprises the first carry impact damper, goes up pull portion, drop-down part, on draw driver portion and the pull-down driver part and the second carry impact damper.The first carry impact damper provides first carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases.Last pull portion provides first scan line driving signal corresponding to first clock signal or second clock signal to first lead-out terminal.Drop-down part provides first supply voltage to first lead-out terminal.On draw driver portion response pull portion from second carry signal of the first carry impact damper output of previous stage and in the conducting, and second scan line driving signal of response next stage and turn-off pull portion.First carry signal that the pull-down driver partial response provides from the first carry impact damper of previous stage and turn-off drop-down part, and second scan line driving signal of response next stage and pull portion in the conducting.The second carry impact damper reduces by first voltage level of second carry signal, and exports first carry signal from the first carry impact damper of previous stage, to put on pull portion.

In another aspect of this invention, provide a kind of shift register, it comprises the level of a plurality of cascades.These grades receive first clock signal and the second clock signal produces a plurality of scan line driving signals that are used to select the multi-strip scanning line with order.Each level comprises drawing on the drag switch device, first draws driver switch device, first device, pull-down driver switching device and second device that pulls down switch that pulls down switch on the driver switch device, second.Last drag switch device provides first scan line driving signal corresponding to first clock signal or second clock signal to the lead-out terminal of each grade.Draw driver switch response device drag switch device and in the conducting on first from the scan start signal of previous stage output or second scan line driving signal.Draw the driver switch response device to turn-off the drag switch device on second from the three scan line drive signal of next stage output.First device that pulls down switch provides first supply voltage to lead-out terminal.Pull-down driver switching device response is turn-offed the device that pulls down switch from the scan start signal of previous stage output or second scan line driving signal.Second pulls down switch response device three scan line drive signal and conducting so that first supply voltage to be provided to lead-out terminal.

In another aspect of this invention, provide a kind of liquid crystal display, it comprises array of display cells, data driving circuit and gate driver circuit.Array of display cells is formed on the transparency carrier and comprises many gate lines, many data lines and a plurality of on-off element.On-off element is coupled in gate line and data line.Data driving circuit provides picture signal to every data line.Gate driver circuit comprises shift register, and this shift register comprises the level of a plurality of cascades.These grades receive first clock signal and the second clock signal produces a plurality of gate line drive signals that are used to select gate line with order.Each level comprises drawing on the drag switch device, first draws driver switch device, first device, pull-down driver switching device and second device that pulls down switch that pulls down switch on the driver switch device, second.Last drag switch device provides first grid polar curve drive signal corresponding to first clock signal or second clock signal to the lead-out terminal of each grade.Draw driver switch response device drag switch device and in the conducting on first from the scan start signal of previous stage output or second grid line drive signal.Draw the driver switch response device to turn-off the drag switch device on second from the 3rd gate line drive signal of next stage output.First device that pulls down switch provides first supply voltage to lead-out terminal.Pull-down driver switching device response is turn-offed the device that pulls down switch from the scan start signal of previous stage output or second grid line drive signal.Second pulls down switch response device the 3rd gate line drive signal and conducting so that first supply voltage to be provided to lead-out terminal.

In another aspect of this invention, provide a kind of shift register, it comprises the level of a plurality of cascades.These grades receive first clock signal and the second clock signal produces a plurality of scan line driving signals that are used to select the multi-strip scanning line with order.Each level comprises draws the driver switch device, goes up drag switch device, first device, second that pulls down switch and pull down switch to draw to draw on the driver switch device, the 3rd on device, the capacitor, second and draw the driver switch device and the second pull-down driver switching device on the driver switch device, first on first.Draw first electrode of driver switch device to receive second source voltage on first, draw second electrode of driver switch device to receive on first, and draw the 3rd electricity of driver switch device grade coupled on first in first node from the scan start signal or first scan line driving signal of previous stage output.The 4th electrode of last drag switch device receives first clock signal or second clock signal, and the 5th electrode of last drag switch device is coupled in first node, and upward the 6th electrode of drag switch device is coupled in lead-out terminal.First the 7th electrode that pulls down switch device is coupled in lead-out terminal, and first the 8th electrode that pulls down switch device is coupled in Section Point, and first the 9th electrode that pulls down switch device receives first supply voltage.Second the tenth electrode that pulls down switch device is coupled in lead-out terminal, and second the 11 electrode that pulls down switch device receives from the second grid line drive signal of next stage output, and second the 12 electrode that pulls down switch device receives first supply voltage.Capacitor-coupled is between first node and lead-out terminal.Draw the 13 electrode of driver switch device to be coupled in first node on second, draw the 14 electrode of driver switch device to receive on second, and draw the 15 electrode of driver switch device to receive first supply voltage on second from the second grid line drive signal of next stage output.Draw the 16 electrode of driver switch device to be coupled in first node on the 3rd, draw the 17 electrode of driver switch device to be coupled in Section Point on the 3rd, and draw the 18 electrode of driver switch device to receive first supply voltage on the 3rd.Draw on first on the 19 electrode and first of driver switch device and draw the mutual coupled in common of the 20 electrode of driver switch device and receive second source voltage, and draw the 21 electrode of driver switch device to be coupled in Section Point on first.The 22 electrode of the second pull-down driver switching device is coupled in Section Point, the 23 electrode of the second pull-down driver switching device is coupled in first node, and the 24 electrode of the second pull-down driver switching device receives first supply voltage.

In another aspect of this invention, provide a kind of method that drives shift register.This shift register comprises the level of a plurality of cascades, and these grades receive first clock signal and the second clock signal produces a plurality of scan line driving signals that are used to select the multi-strip scanning line with order.Receive first clock signal or second clock signal, and provide first clock signal or second clock signal to each level.First clock signal and second clock signal have first voltage level corresponding with first voltage level of first supply voltage basically.Produce second source voltage, and provide second source voltage to each level.Second source voltage has second voltage level than the high predetermined voltage level of first voltage level.Generation is used to select to be coupled in first scan line driving signal when first sweep trace of prime.Response is brought down below the tertiary voltage level of first scan line driving signal the 4th voltage level of tertiary voltage level from second scan line driving signal of next stage output.First scan line driving signal with the 4th voltage level is provided to first sweep trace.After the tertiary voltage level that reduces by first scan line driving signal, when the voltage level of the output signal of the device that pulls down switch when the 5th voltage level fades to the 6th voltage level that is higher than the 5th voltage level, the 4th voltage level of first scan line driving signal is kept predetermined period.

In another aspect of this invention, provide a kind of method that drives shift register.This shift register comprises the level of a plurality of cascades, and these grades alternately receive first clock signal and the second clock signal that produces from clock generator, produces a plurality of scan line driving signals that are used to select the multi-strip scanning line with order.First and second clock signals have first voltage level corresponding with first voltage level of first supply voltage basically.Each the level comprise draw on the drag switch device, first draw the driver switch device on the driver switch device, second, device and pull-down driver switching device pull down switch.Last drag switch device provides first scan line driving signal corresponding to first clock signal or second clock signal to the lead-out terminal of each grade.Draw driver switch response device drag switch device and in the conducting on first from the scan start signal of previous stage output or second scan line driving signal.Draw the driver switch response device to turn-off the drag switch device on second from the three scan line drive signal of next stage output.The device that pulls down switch provides the 3rd supply voltage to lead-out terminal.Pull-down driver switching device response is turn-offed the device that pulls down switch from the scan start signal of previous stage output or second scan line driving signal.Receive first clock signal or second clock signal, and provide first clock signal or second clock signal to each level.Produce second source voltage, and provide second source voltage to each level.Second source voltage has second voltage level than the high predetermined voltage level of first voltage level.During the high level period of first clock signal or second clock signal, produce first scan line driving signal be used to select to be coupled in when first sweep trace of prime.Response is brought down below the tertiary voltage level of first scan line driving signal the 4th voltage level of tertiary voltage level from the three scan line drive signal of next stage output.First scan line driving signal with the 4th voltage level is provided to first sweep trace.After the tertiary voltage level that reduces by first scan line driving signal, when the voltage level of the output signal of the device that pulls down switch when the 5th voltage level fades to the 6th voltage level that is higher than the 5th voltage level, the 4th voltage level of first scan line driving signal is kept predetermined period.

As mentioned above, according to shift register of the present invention, this shift register comprises a plurality of levels and the carry buffer transistor that is used to produce carry signal.In having screen sizes and high-resolution liquid crystal display, can minimize owing to the RC of gate line postpones the signal delay that causes.

Carry signal is independent of the output signal of exporting from when the lead-out terminal of prime, and is transferred to gate line by the carry buffer transistor that is arranged in when prime.Therefore, can prevent because the effect of the RC load that gate line causes.

In addition, because next stage is not to be resetted by the gate line drive signal but resetted by clock signal, so image displaying quality can not worsen.

In addition, in having screen sizes and high-resolution liquid crystal display, shift register is independent of the variations in threshold voltage of thin film transistor (TFT), therefore even when the threshold voltage of thin film transistor (TFT) changes owing to the variation of environment temperature, the also exportable normal gate line drive signal of shift register, and can prevent the abnormal operation of the shift register that causes owing to the thin film transistor (TFT) threshold voltage variation.

In addition, because in having screen sizes and high-resolution liquid crystal display, shift register is independent of the threshold voltage variation of thin film transistor (TFT), so it can be enhanced.

In addition, in large-scale environment temperature, can improve the reliability of shift register.

In addition, owing to can improve the tolerance limit of threshold voltage variation, therefore can improve the yield rate of making shift register.

In addition, the pull-down transistor of each of shift register grade is divided into first pull-down transistor and second pull-down transistor.Therefore, can reduce the transistor size of the influential pull-down transistor of capacitive load of inverter (inverter), can improve the operating speed of inverter, so image displaying quality can not worsen shift register.

In addition, put on shift register greater than the supply voltage Vona of the supply voltage Von that puts on clock generator, even therefore in having screen sizes and high-resolution liquid crystal display, image displaying quality can not worsen yet.

Description of drawings

By the reference accompanying drawing the preferred embodiments of the present invention are described in detail, above-mentioned and other advantage of the present invention will become apparent, wherein:

Fig. 1 is the synoptic diagram of traditional polycrystalline SiTFT LCD;

Fig. 2 is the synoptic diagram that traditional amorphous silicon film transistor LCD is shown;

Fig. 3 is the decomposition diagram that amorphous silicon film transistor LCD according to an illustrative embodiment of the invention is shown;

Fig. 4 is the synoptic diagram that the amorphous silicon film transistor substrate of Fig. 3 is shown;

Fig. 5 is the block scheme that the data driving circuit of Fig. 4 is shown;

Fig. 6 is the block scheme that the shift register of the gate driver circuit that is used for Fig. 4 is shown;

Fig. 7 be illustrate Fig. 6 shift register the level circuit diagram;

Fig. 8 is the figure that illustrates from grade scan line driving signal of exporting of Fig. 7;

Fig. 9 is the figure that illustrates from the scan line driving signal of the shift register of Fig. 6 output;

Figure 10 illustrates the shift register of Fig. 6 and the synoptic diagram of gate line;

Figure 11 is the block scheme that the shift register that is used for gate driver circuit of first exemplary embodiment according to the present invention is shown;

Figure 12 is the circuit diagram that the N level in the shift register of Figure 11 is shown;

Figure 13 illustrates the last level in the shift register of Figure 11 and the circuit diagram of pseudo-level (dummy stage);

Figure 14 illustrates the shift register of Figure 11 and the synoptic diagram of gate line;

Figure 15 A and 15B are the layouts of last pull portion, drop-down part and carry impact damper that illustrates in the level of shift register of Figure 11;

Figure 15 C is the enlarged drawing that the carry impact damper in the shift register of Figure 15 A is shown;

Figure 16 A, 16B and 16C are the figure that illustrates from the gate line drive signal of the shift register of Fig. 7 output;

Figure 17 is the block scheme that the shift register that is used for gate driver circuit of second exemplary embodiment according to the present invention is shown;

Figure 18 is the block scheme that the shift register that is used for gate driver circuit of the 3rd exemplary embodiment according to the present invention is shown;

Figure 19 A and 19B are the figure of output that the shift register of Figure 18 is shown;

Figure 20 is the block scheme that the shift register that is used for gate driver circuit of the 4th exemplary embodiment according to the present invention is shown;

Figure 21 is the block scheme that the shift register that is used for gate driver circuit of the 5th exemplary embodiment according to the present invention is shown;

Figure 22 is the figure at the voltage of the capacitor place of Figure 21 measurement;

Figure 23 is the figure that illustrates from the gate line drive signal of the shift register of Fig. 7 output;

Figure 24 is the block scheme that the cell level of the shift register that is used for gate driver circuit of the 6th exemplary embodiment according to the present invention is shown;

Figure 25 is the figure that illustrates from the gate line drive signal of the shift register of Figure 24 output;

Figure 26 illustrates from the gate line drive signal of the shift register of Fig. 7 output with from the figure of the gate line drive signal of the shift register output of Figure 24;

Figure 27 is the power supply of the 7th exemplary embodiment according to the present invention and the block scheme of clock generator;

Figure 28 be illustrate when will the supply voltage identical putting on shift register with the supply voltage of the clock generator that puts on Figure 27, from the figure of the gate line drive signal of shift register output;

Figure 29 is the power supply of the 7th exemplary embodiment according to the present invention and the block scheme of clock generator;

Figure 30 is the exemplary circuit figure of the DC to DC converter of Figure 29;

Figure 31 be illustrate when the power supply of Figure 29 and clock generator drive shift register, from the figure of the gate line drive signal of shift register output; And

Figure 32 is when the power supply of Figure 29 and 28 and clock generator drive shift register, from the figure of the gate line drive signal of shift register output.

Embodiment

Below, describe the preferred embodiments of the present invention with reference to the accompanying drawings in detail.

Fig. 3 is the decomposition diagram that amorphous silicon film transistor LCD according to an illustrative embodiment of the invention is shown.

With reference to Fig. 3, liquid crystal display 100 comprises liquid crystal display board component 110, backlight assembly 120, chassis (chassis) 130 and case (cover case) 140.

Liquid crystal display board component 110 comprises LCD panel 112, flexible printed circuit board 116 and integrated control chip 118.LCD panel 112 comprises TFT substrate 112a and filter substrate 112b.

On TFT substrate 112a, form array of display cells, data driving circuit, gate driver circuit and external connection terminals.On filter substrate 112b, form color filter and transparent common electrode.Filter substrate 112b is in the face of TFT substrate 112a, and between filter substrate 112b and TFT substrate 112a filling liquid crystal.

Integrated control chip 118 is connected electrically to the thin film transistor (TFT) that forms on the array of display cells of TFT substrate 112a by flexible print circuit 116.Data-signal, data timing signal, grid timing signal and the supply voltage that is used for the driving grid drive circuit are offered data driving circuit and the gate driver circuit that forms on TFT substrate 112a.Array of display cells comprises many gate lines, many data lines and a plurality of on-off element, and on-off element is connected respectively to each bar of data line and each bar of gate line.Gate driver circuit is connected with gate line, and driving switch element.Data driving circuit is connected with data line, and provides picture signal to data line.

Backlight assembly 120 comprises lamp assembly 122, light pipe 124, mating plate 126, reflector plate 128 and mold framework (mold frame) 129.

Fig. 4 is the synoptic diagram that the amorphous silicon film transistor substrate of Fig. 3 is shown.

With reference to Fig. 4, employing forms the same process of TFT on TFT substrate 112a, form array of display cells 150, data driving circuit 160, gate driver circuit 170 on TFT substrate 112a, be used for data driving circuit 160 is connected to the

external connection terminals

162 and 163 and another external connection terminals 169 of being used for gate driver circuit 170 is connected to integrated control chip 118 of integrated control chip 118.

Array of display cells 150 comprise m bar data line DL1, DL2 ..., DLm and n bar gate lines G L1, GL2 ..., GLn.Data line DL1, DL2 ..., DLm extends on column direction, and gate lines G L1, GL2 ..., GLn extends on line direction.For example, the LCD panel with 2 inches screen sizes is disclosed.LCD panel has 176 data lines and 192 gate lines, thereby point resolution 525 (176 * 3) * 192 is provided.

On the point of crossing between data line and the gate line, form switching transistor (ST; Perhaps on-off element).The drain electrode of switching transistor STi is connected to data line DLi, and the grid of switching transistor STi is connected to gate lines G Li, and the source electrode of switching transistor STi is connected to pixel electrode PE.Liquid crystal LC is between pixel electrode PE and public electrode CE.On filter substrate 112b, form public electrode CE.

Therefore, the voltage that puts on pixel electrode PE and public electrode CE changes the arrangement angle of liquid crystal molecule, regulates the light quantity by liquid crystal molecule, and displayable image.

Data driving circuit 160 comprises shift register 164 and 528 switching transistors (SWT).8 data line piece BL1, BL2 ..., among the BL8 each comprises 66 switching transistors (SWT).

66 input terminals of each data line piece are connected to external connection terminals 163 jointly, and 66 lead-out terminals are connected respectively to 66 respective data lines.External connection terminals 163 has 66 data input terminals.Piece selects terminal to be connected to the lead-out terminal of shift register 164.

The source electrode of 528 switching transistors (SWT) is connected respectively to respective data lines, and the drain electrode of 528 switching transistors (SWT) is connected respectively to the corresponding data input terminal, and the grid of 528 switching transistors (SWT) is connected to piece selection terminal.In 528 switching transistors (SWT) each all is amorphous silicon TFT MOS transistor.

Thereby 66 data lines in 528 data lines are divided into 8 pieces, but and 8 each pieces of block selection signal select progressively.

Shift register 164 receives the first clock CKH, second clock CKHB by the external connection terminals 162 with three terminals and piece is selected enabling signal STH.Each lead-out terminal of shift register 164 is connected to the piece of corresponding data line piece and selects terminal.

Fig. 5 is the block scheme that the data driving circuit of Fig. 4 is shown.

With reference to Fig. 5, shift register 164 according to the present invention for example comprises 9 level SRH of cascade mutually ₁, SRH ₂..., SRH ₉The lead-out terminal OUT of each grade is connected to the input terminal IN of next stage.These levels comprise 8 level SRH ₁, SRH ₂..., SRH ₈And pseudo-level (SRC ₉).8 level SRH ₁, SRH ₂..., SRH ₈Corresponding to 8 data line pieces.Each level comprises input terminal IN, lead-out terminal OUT, control terminal CT, clock terminal CK, the first power supply voltage terminal VSS and second source voltage terminal VDD.8 level SRH ₁, SRH ₂..., SRH ₈Respectively to each data line piece BL1, BL2 ..., the piece of BL8 select terminal provide piece select enabling signal DE1, DE2 ..., DE8.Piece select enabling signal DE1, DE2 ..., DE8 be used to select each data line piece enable (enable) signal.

The first clock CKH puts on odd level SRH ₁, SRH ₃, SRH ₅, SRH ₇And SRH ₉, and second clock CKHB puts on even level SRH ₂, SRH ₄, SRH ₆, SRH ₈The first clock CKH has the opposite phases with second clock CKHB.For example, the work period of the first clock CKH and second clock CKHB is lower than 1/66ms.

The output signal of next stage (or gate line drive signal) puts on control terminal CT as control signal.

The output signal of each grade has the active cycle (or high level period) in proper order, selects the data line piece corresponding to the active cycle.

Pseudo-level SRH ₉To previous stage (SRH ₈) control terminal CT control signal is provided.

Fig. 6 is the block scheme that the shift register of the gate driver circuit that is used for Fig. 4 is shown.

With reference to Fig. 6, gate driver circuit 170 comprises shift register, and this shift register comprises a plurality of grades of SRC of mutual cascade ₁, SRC ₂..., SRC ₁₉₂With pseudo-level SRC ₁₉₃The lead-out terminal OUT of each grade is connected to the input terminal IN of next stage.These levels comprise 192 level SRC ₁, SRC ₂..., SRC ₁₉₂With pseudo-level SRC ₁₉₃

Each level comprises input terminal IN, lead-out terminal OUT, control terminal CT, the sub-CK of clock signal input terminal, the first power supply voltage terminal VSS and second source voltage terminal VDD.

First order SRC ₁Receive scan start signal STV by input terminal IN.Scan start signal STV is the pulse synchronous with vertical synchronizing signal Vsync.Each grade SRC ₁, SRC ₂..., SRC ₁₉₂Produce gate line drive signal GOUT respectively ₁, GOUT ₂..., GOUT ₁₉₂, and gate line drive signal GOUT ₁, GOUT ₂..., GOUT ₁₉₂Be connected respectively to gate line, so that select gate line.

The first clock signal ckv puts on odd level (SRC ₁, SRC ₃, SRC ₅...), and second clock signal ckvb puts on even level (SRH ₂, SRH ₄, SRH ₆...).The first clock ckb has the opposite phases with second clock ckvb.For example, the work period of the first clock ckv and second clock ckvb is about 16.6/192ms.

The work period of clock of shift register 164 that is used for data driving circuit is greater than about 8 times of the work period of the clock of the shift register 170 that is used for gate driver circuit.

Next stage SRC ₂, SRC ₃, SRC ₄Output signal GOUT ₁, GOUT ₂..., GOUT ₁₉₂Put on a grade SRC respectively as control signal ₁, SRC ₂, SRC ₃Control terminal CT.

The output signal of each grade has the active cycle (or high level period) in proper order, and selects the gate line corresponding to the active cycle.

Pseudo-level SRC ₁₉₃(or deactivation) the last level that resets (SRH ₁₉₂).Specifically, pseudo-level SRC ₁₉₃Will last level (SRC ₁₉₂) the voltage level of output signal be reduced to low voltage level (LOW) from high-voltage level (HIGH).

Fig. 7 is the circuit diagram of level that the shift register of Fig. 6 is shown, and Fig. 8 is the figure that illustrates from the scan line driving signal of the level output of Fig. 7.

With reference to Fig. 7, each level of shift register 170 comprise pull portion 171, drop-down part 172, on draw driver portion 173 and pull-down driver part 174.

Last pull portion 171 comprises the first nmos pass transistor M1, and its drain electrode is connected to the sub-CK of clock signal input terminal, grid is connected to first node N1, and source electrode is connected to lead-out terminal GOUT[N].

Drop-down part 172 comprises the second nmos pass transistor M2, and its drain electrode is connected to lead-out terminal OUT, and grid is connected to Section Point N2, and source electrode is connected to the first power supply voltage terminal VSS.

On draw driver portion 173 to comprise capacitor C and nmos pass transistor M3, M4 and M5.Capacitor C is connected first node N1 and lead-out terminal GOUT[N] between.The drain electrode of the 3rd nmos pass transistor M3 is connected to the lead-out terminal GOUT[N-1 that second source voltage VON, its grid are connected to previous stage], and its source electrode is connected to first node N1.The drain electrode of transistor M4 is connected to first node N1, and its grid is connected to Section Point N2, and its source electrode is connected to the first supply voltage VOFF.The drain electrode of transistor M5 is connected to first node N1, and its grid is connected to Section Point N2, and its source electrode is connected to the first supply voltage VOFF.The transistor size of transistor M3 is greater than about 2 times of transistor M5.

Pull-down driver part 174 comprises two nmos pass transistor M6 and M7.The drain and gate of transistor M6 is common mutually to be connected, and is connected to second source voltage VON, and its source electrode is connected to Section Point N2.The drain electrode of transistor M7 is connected to Section Point N2, and its grid is connected to first node N1, and its source electrode is connected to the first supply voltage VOFF.The transistor size of transistor M6 is greater than about 16 times of transistor M7.

As shown in Figure 8, when the first and second clock signal ckv and ckvb and scan start signal STV are provided for shift register 170, first order SRC1 responding scanning enabling signal STV preceding (initial) along and the high level period of the first clock signal ckv is postponed the schedule time of Tdr1, thereby output delay output signal GOUT1.

As mentioned above, the shift register that forms on glass substrate receives scan start signal STV, the first clock ckv and second clock ckvb, and drives the grid of the TFT that forms on the TFT substrate.

The operation of each grade of shift register below will be described.

Fig. 9 is the figure that illustrates from the scan line driving signal of the shift register of Fig. 6 output.

With reference to Fig. 9, shift register receives the first clock signal ckv or second clock signal ckvb, and provides a plurality of gate line drive signal (GOUT to many gate lines ₁, GOUT ₂, GOUT ₃...).Second clock ckvb has and the first clock ckv opposite phases.First and second clock signals are swung (swing) in the cycle of 2H, as shown in Figure 9.Have the voltage in 0 volt to 3 volts the scope from the signal of timing controller (not shown) output, and through amplification having-8 volts of voltages in 24 volts the scope, thereby obtain first and second clock signals.

Referring again to Fig. 7, the output signal of previous stage (or gate line drive signal) GOUT _N-1To capacitor C charging, and prime is worked as in setting (or activation).The output signal of next stage (or gate line drive signal) GOUT _N+1To capacitor C discharge, and reset (or deactivation) works as prime.

When the first clock signal ckv, second clock signal ckvb and scan start signal STV put on the first order, the rising edge of responding scanning enabling signal STV and the high level period of the first clock signal ckv is postponed predetermined period, with at lead-out terminal as output signal GOUT[1] output.

Capacitor C response is input to the scan start signal STV in the grid of transistor M1 by input terminal IN rising edge begins charging.When at the voltage Vc1 of capacitor C charging during greater than the threshold voltage of transistor M1, the conducting M1 that pulls up transistor, and export the high level period of the first clock ckv at lead-out terminal OUT.

When lead-out terminal OUT exports the high level period of first clock signal CKV, in the high level period of capacitor C guiding (bootstrap) this output voltage or the first clock signal ckv, thereby the grid voltage of the M1 that pulls up transistor rises on the forward voltage Von.Thereby the NMOS M1 that pulls up transistor keeps complete conducting state.Because the transistor size of transistor M3 is greater than about 2 times of transistor M4, even when transistor M4 during by scan start signal STV conducting, also conducting of transistor M2.

Simultaneously, before scan start signal STV was input in the pull-down driver part 174, the voltage of first node N1 rose to second source voltage Von by transistor M6, and turn-on transistor M2.Thereby the output signal of lead-out terminal OUT has the first supply voltage Voff basically.When scan start signal STV is input to pull-down driver part 174, this transistor turns, and the voltage of Section Point N2 is reduced to the first supply voltage Voff basically.Because the transistor size of transistor M7 is greater than about 16 times of transistor M6, even therefore transistor M6 conducting, Section Point N2 also keeps the first supply voltage Voff basically.Thereby, turn-off pull-down transistor M2.

When scan start signal STV puts on pull-down driver part 74, turn-off pull-down transistor M2, and with work period of the first clock signal ckv delay control, one clock signal ckv, to export at lead-out terminal.

When the voltage of the output signal of exporting from lead-out terminal OUT was reduced to shutoff voltage Voff (or Vss), transistor M7 turn-offed.

Owing to have only second source voltage Von to offer Section Point N2, so the voltage of Section Point N2 begins to rise to second source voltage Von from the first supply voltage Voff by transistor M6.When the voltage of the 4th node begins to rise, transistor M4 conducting, and the electric charge of capacitor is by transistor M4 discharge.Therefore, the M1 that pulls up transistor begins to turn-off.

Then, owing to output signal GOUT[N+1 from next stage output] rise to forward voltage Von, so transistor M5 conducting.Because the transistor size of transistor M5 greater than the about twice of transistor M4, is therefore compared with the situation of only transistor M4 conducting, the voltage of first node N1 is reduced to the first supply voltage Voff more quickly.

In addition, when the voltage of Section Point N2 rises to second source voltage Von, pull-down transistor M2 conducting, and the output voltage of exporting from lead-out terminal OUT fades to shutoff voltage Voff from forward voltage Von.

Because Section Point N2 is connected to transistor M6, even therefore put on the output signal GOUT[N+1 of the next stage of control terminal CT] reduce to low voltage level and transistor M5 shutoff, Section Point N2 also keeps second source voltage Von.Thereby, prevent the fault that the shutoff owing to pull-down transistor M2 causes.

As shown in Figure 8, order produces output signal GOUT[1], GOUT[2], GOUT[3] ....

As mentioned above, the output signal of capacitor C response previous stage and charging, the clock signal that puts on pull portion or drop-down part is as the output signal of working as prime and export.When producing the output signal of next stage on the gate line of the lead-out terminal that is being connected to next stage, the output signal conducting discharge transistor M5 of next stage, and to capacitor C discharge, thereby the operation cycle of termination shift register.

Above-mentioned shift register is as the gate driver circuit in the liquid crystal display with little or middle display size, but owing to postpone because of being present in the RC that resistance in the gate line and electric capacity causes, it can not be used as the gate driver circuit in the liquid crystal display with large display screen.

As shown in Figure 6, each grade reception has the first clock ckv or the second clock ckvb in 2H cycle, and the first clock ckv or second clock ckvb are put on gate line.

Specifically, the N level receives (N-1) gate-on voltage (or (N-1) gate line drive signal) by input terminal, and responds (N-1) gate-on voltage and produce N gate-on voltage (or N gate line drive signal).The N level receives (N+1) gate line drive signal by control terminal, and responds (N+1) gate line drive signal and provide gate off voltage to gate line.

Because (N-1) gate-on voltage and electric the coupling of (N-1) gate line, therefore the load electrical of (N-1) gate line ground influences the input terminal of N level.Therefore, produce signal delay, and each grade is subjected to the influence of the load of gate line.

As shown in figure 10, each bar gate line has a plurality of resistive elements and a plurality of capacity cell, and the input terminal of N level receives (N-1) output signal of (N-1) level.Because the input terminal of N level is connected to (N-1) gate line, signal delay (for example, RC postpones) therefore may take place owing to the RC load of gate line.

In addition, because each mutually cascade of level, thus signal delay since be connected to earlier stages (first order, the second level ..., (N-1) level) the front gate line (first grid polar curve, second grid line ..., (N-1) gate line) the RC load and can increase along with the increase of N.Therefore, display quality may be by severe exacerbation.In liquid crystal display, because the RC load of gate line is little, and show that the cycle of gate-on voltage is long, so signal delay can not cause the display quality of above-mentioned severe exacerbation with little or middle screen size.Yet in the liquid crystal display with large display screen size, signal delay can cause the display quality of above-mentioned severe exacerbation.

Can use external signal to replace gate line drive signal from previous stage output to activate (or setting) next stage.

Figure 11 is the block scheme that the shift register that is used for gate driver circuit of first exemplary embodiment according to the present invention is shown.

With reference to Figure 11, the gate driver circuit of first exemplary embodiment comprises a plurality of grades of SRC of mutual cascade according to the present invention ₁, SRC ₂, SRC ₃..., SRC _N, SRC _N+1And a plurality of carry impact damper CB ₁, CB ₂..., CB _NCarry impact damper CB ₁, CB ₂..., CB _NBetween two adjacent levels.The lead-out terminal OUT of each grade is connected to the input terminal IN of next stage.These levels comprise N level SRC ₁, SRC ₂, SRC ₃..., SRC _NAnd pseudo-level SRC _N+1

Each level comprises input terminal IN, lead-out terminal OUT, control terminal CT, the sub-CK of clock signal input terminal, the first power supply voltage terminal VSS, second source voltage terminal VDD and carry lead-out terminal CRR.

First order SRC ₁Receive scan start signal STV by input terminal IN.Scan start signal STV is the pulse signal synchronous with the vertical synchronizing signal Vsync that provides from the external graphics controller (not shown).

Level SRC ₂..., SRC _NThe carry voltage that provides from the carry lead-out terminal CRR of previous stage is provided by the carry impact damper.

Each grade SRC ₁, SRC ₂..., SRC ₁₉₂Produce gate line drive signal GOUT respectively ₁, GOUT ₂..., GOUT ₁₉₂, and gate line drive signal GOUT ₁, GOUT ₂..., GOUT ₁₉₂Be connected respectively to gate line, so that select gate line.

The work period of clock of shift register 164 that is used for data driving circuit is greater than about 8 times of the clock of the shift register 170 that is used for gate driver circuit.

Next stage SRC ₂, SRC ₃, SRC ₄Output signal GOUT ₂..., GOUT ₁₉₂Put on a grade SRC respectively as control signal ₁, SRC ₂, SRC ₃Control terminal CT.

Carry impact damper CB ₁, CB ₂..., CB _NThe clock signal that use provides from external power source but not from the gate line drive signal of previous stage output as carry signal, so that activate (or setting) next stage.Carry impact damper CB ₁, CB ₂..., CB _NCan be installed in the inside of each grade.

Figure 12 is the circuit diagram that the N level in the shift register of Figure 11 is shown.

With reference to Figure 12, each level of shift register comprise pull portion 171, drop-down part 172, on draw driver portion 173, pull-down driver part 174 and carry impact damper 275.

Last pull portion 171 comprises the first nmos pass transistor M1, and its drain electrode is connected to the sub-CK of clock signal input terminal, and its grid is connected to first node N1, and its source electrode is connected to lead-out terminal GOUT[N].

Drop-down part 172 comprises the second nmos pass transistor M2, and its drain electrode is connected to lead-out terminal GOUT[N], its grid is connected to Section Point N2, and its source electrode is connected to the first power supply voltage terminal VSS.

On draw driver portion 173 to comprise capacitor C and nmos pass transistor M3, M4 and M5.Capacitor C is connected first node N1 and lead-out terminal GOUT[N] between.The drain electrode of the 3rd nmos pass transistor M3 is connected to second source voltage VON, and its grid is connected to the lead-out terminal GOUT[N-1 of previous stage], and its source electrode is connected to first node N1.The drain electrode of transistor M4 is connected to first node N1, and its grid is connected to Section Point N2, and its source electrode is connected to the first supply voltage VOFF.The drain electrode of transistor M5 is connected to first node N1, and its grid is connected to Section Point N2, and its source electrode is connected to the first supply voltage VOFF.The transistor size of transistor M3 is greater than about 2 times of transistor M5.

Carry impact damper 275 comprises carry buffer transistor TR1, and the first clock ckv or second clock ckvb are outputed to next stage.Specifically, the grid of carry buffer transistor TR1 is connected to the input terminal of pull-down driver part 174, the drain electrode of carry buffer transistor TR1 is connected to clock terminal CKV or CKVB, and the source electrode of carry buffer transistor TR1 is connected to the grid of the 3rd transistor M3 of the last pull portion 173 of next stage.

The carry buffer transistor TR1 of previous stage receives the first clock ckv or second clock ckvb, and the first clock ckv or second clock ckvb be transferred to as carry signal work as prime.The RC delay that the RC load of gate line causes because the clock signal with basically consistent voltage level as carry signal, therefore can not take place.

Figure 13 illustrates the last level in the shift register of Figure 11 and the circuit diagram of pseudo-level.

With reference to Figure 13, each level of shift register comprise pull portion 171, drop-down part 172, on draw driver portion 173, pull-down driver part 174 and carry impact damper 275.Therefore in Figure 13, the similar elements in the identical label list diagrammatic sketch 12 will be omitted the detailed description of similar elements.

As shown in figure 13, because the output signal of previous stage is subjected to the influence of the RC load of gate line, so the output signal of previous stage do not put on the input terminal of each grade, clock signal put on the input terminal of each grade as carry signal.Therefore, owing to be independent of the output signal of previous stage, therefore can not take place because the RC delay that the RC load of gate line causes as the clock signal of carry signal.

Below, the top level of Figure 13 is called previous stage SRC _N, the lower stage of Figure 13 is called as prime SRC _N+1, so that describe the operation of shift register of the present invention.

Previous stage SRC _NCarry buffer transistor TR1 receive and to be used for activating (or setting) as prime SRC _N+1The first clock ckv (or control signal of the M1 that pulls up transistor), and basically the first clock ckv is transferred to as prime SRC as carry signal _N+1The RC delay that the RC load of gate line causes because the clock signal ckv with basically consistent voltage level as carry signal, therefore can not take place.

At carry signal CA[N] put on before the grid of the 3rd transistor M3, the 3rd transistor M3 remains in off state.As carry signal CA[N] when putting on the grid of the 3rd transistor M3, after predetermined period, the 3rd transistor M3 conducting is to form by its current path to capacitor C charging second source voltage Von.

When the voltage level that will have the low level clock ckv or the first supply voltage Voff put on the grid of the 3rd transistor M3, the 3rd transistor M3 turn-offed.

Figure 14 illustrates the shift register of Figure 11 and the synoptic diagram of gate line.

With reference to Figure 14, each level (SRC ₁, SRC ₂, SRC ₃...) apply a plurality of gate line drive signal (GOUT respectively by the lead-out terminal of each grade ₁, GOUT ₂, GOUT ₃...), so that select the gate line of LCD panel 150.

In addition, each level (SRC ₁, SRC ₂, SRC ₃...) by carry lead-out terminal CA carry signal is put on the input terminal of next stage.Carry signal is the first clock ckv or second clock ckvb.The first clock ckv or second clock ckvb provide from external power source, and are independent of each level.Second clock ckvb has and the first clock ckv opposite phases.

To put on from the carry signal of the carry lead-out terminal output of previous stage owing to replace when the input terminal of prime so that activate and work as prime, therefore can prevent the display quality deterioration that the RC load owing to gate line causes from the gate line drive signal of the lead-out terminal OUT output of previous stage.

Figure 15 A and 15B are the layouts of last pull portion, drop-down part and carry impact damper that illustrates in the level of shift register of Figure 11, and Figure 15 C is the enlarged drawing that the carry impact damper in the shift register of Figure 15 A is shown.

The transistor size that draws nmos pass transistor M1 and pull-down NMOS transistor M2 on Figure 12 greater than on draw driver nmos pass transistor M3, M4, M5 and pull-down driver nmos pass transistor M6, M7 so that drive the gate line that is connected to pull up transistor M1 and pull-down transistor M2.

Shown in Figure 15 A, 15B and 15C, order forms grid wiring (gate wiring) and active patterns (active pattern) in the presumptive area on insulated substrate, and on grid wiring, form a plurality of drain electrodes and multiple source electrode with ' branch ' type shape (or ' finger ' type shape), so that form and pull up transistor (M1[N] and M1[N+1]) and pull-down transistor (M2[N] and M2[N+1]).Grid wiring comprises a gate electrode (or a plurality of gate electrode) and a gate line (or many gate lines).M1[N] be the M1 that pulls up transistor of N level, and M1[N+1] be the M1 that pulls up transistor of (N+1) level.M2[N] be the pull-down transistor M2 of N level, and M2[N+1] be the pull-down transistor M2 of (N+1) level.In ' branch ' of the present invention type shape, drain electrode is from main drain electrode wiring branch, and each drain electrode is inserted in the branch of each drain electrode.For example, active patterns is made up of amorphous silicon.Below, the N level is called works as prime, and (N+1) level is called next stage.

Specifically, in being used for limiting first presumptive area of first predetermined area, form and pull up transistor the grid wiring of (M1[N] and M1[N+1]).For example, first presumptive area can have rectangular shape.On the grid wiring of (M1[N] and M1[N+1]) that pulls up transistor, form and pull up transistor the active patterns of (M1[N] and M1[N+1]).Pull up transistor main drain electrode wiring 300 branches of drain electrode from extending of (M1[N] and M1[N+1]) in downward direction, and on the active patterns of (M1[N] and M1[N+1]) that pulls up transistor, form.Between branch's (drain line) of drain electrode, form and pull up transistor each source electrode of (M1[N] and M1[N+1]).Just, between branch's (or drain line) of drain electrode, form each branch (source electrode line) of source electrode.Also can form and pull up transistor the source electrode of (M1[N] and M1[N+1]) in the outside of the drain electrode of pull up transistor (M1[N] and M1[N+1]).Each the source electrode of (M1[N] and M1[N+1]) of pulling up transistor is connected electrically to gate line by contact hole (CNT1, CNT2).For example, the width of every drain line can be about 5 μ m, and the width of every gate line can be about 5 μ m.For example, the width of main drain line can be greater than about 5 μ m.(L) is more little for distance between drain line and the source electrode line, and the characteristic of thin film transistor (TFT) (TFT) is just good more.For example, (L) is more little for the distance between drain line and the source electrode line, and transistor size (W/L) is just big more.

Specifically, in being used for limiting second presumptive area of second predetermined area, form the grid wiring of pull-down transistor (M2[N] and M2[N+1]).For example, second presumptive area can have rectangular shape.On the grid wiring of pull-down transistor (M2[N] and M2[N+1]), form the active patterns of pull-down transistor (M2[N] and M2[N+1]).The drain electrode of pull-down transistor (M2[N] and M2[N+1]) is from main drain electrode wiring 300 branches of upwards extending upward, and is formed on the active patterns of pull-down transistor (M2[N] and M2[N+1]).Each drain electrode of pull-down transistor (M2[N] and M2[N+1]) is connected electrically to gate line by contact hole (CNT1, CNT2).Between branch's (or drain line) of drain electrode, form each source electrode of pull-down transistor (M2[N] and M2[N+1]).Just, between branch's (or drain line) of drain electrode, form each branch (or source electrode line) of source electrode.Also can form and pull up transistor the source electrode of (M2[N] and M2[N+1]) in the outside of the drain electrode of pull up transistor (M2[N] and M2[N+1]).

Specifically, the a plurality of drain electrodes of the multiple source electrode of (M1[N] and M1[N+1]) and pull-down transistor (M2[N] and M2[N+1]) of pulling up transistor are connected to the first contact hole CNT1 jointly, make and pull up transistor a plurality of drain electrodes of the source electrode of (M1[N] and M1[N+1]) and pull-down transistor (M2[N] and M2[N+1]) can be connected to gate line jointly.The height of the source electrode of the height of the source electrode of (M1[N] and M1[N+1]) or pull-down transistor owing to pull up transistor (M2[N] and M2[N+1]) is different from the height of gate line, and the source electrode of therefore pull up transistor (M1[N] and M1[N+1]) or pull-down transistor (M2[N] and M2[N+1]) is received gate line by the bridging that forms between first tin indium oxide (ITO1) layer and the second contact hole CNT2.First tin indium oxide (ITO1) layer comprises conductive material.First tin indium oxide (ITO1) layer is connected to the first contact hole CNT1.

Form carry buffer transistor TR1 on adjacent to the position of the M1 that pulls up transistor, so that will put on when first clock ckv of the drain electrode of the M1 that pulls up transistor of prime or the gate electrode of the 3rd transistor M3 that second clock ckvb offers next stage.

Specifically, the gate electrode of carry buffer transistor TR1 is connected to and pulls up transistor the gate electrode of (M1[N] and M1[N+1]) jointly.The drain electrode of carry buffer transistor TR1 can be from the main drain electrode wiring branch of pull up transistor (M1[N] and M1[N+1]).The source electrode of carry buffer transistor TR1 gets around (walking around) pull up transistor (M1[N] and M1[N+1]) and pull-down transistor (M2[N] and M2[N+1]), with the gate electrode of the 3rd transistor M3 that extends to next stage.

Because the height of branch's (or source electrode line) of the source electrode of carry buffer transistor TR1 is different from the height of grid wiring of the gate electrode of the 3rd transistor M3 that is connected to next stage, so the source electrode of carry buffer transistor TR1 is by receiving the grid wiring that is connected with the gate electrode of the 3rd transistor M3 in the bridging that forms between second tin indium oxide (ITO2) layer and the 4th contact hole CNT4.Second tin indium oxide (ITO2) layer comprises conductive material.Second tin indium oxide (ITO2) layer is connected to the source electrode line of carry buffer transistor TR1 by the 3rd contact hole CNT3.

Fig. 7 and 8 shift register be used for having little or the LCD panel of screen size as 525 (176 * 3) * 192 in, but the shift register of Fig. 7 and 8 is owing to the signal delay problem is not useable for having in the LCD panel of screen sizes.

On draw or the transistor size of pull-down transistor (M1 or M2) needs to increase so that the shift register of Fig. 7 and 8 can be used for having in the LCD panel of screen sizes.Yet, because the restriction of the chip area of shift register, on draw or there is restriction in the increase of the transistor size of pull-down transistor (M1 or M2).

Therefore, reliability and the yield rate of making liquid crystal display may can not get guaranteeing because the threshold voltage of thin film transistor (TFT) owing on draw or the restriction of the transistor size of pull-down transistor (M1 or M2) and the characteristic of amorphous silicon film transistor change.

Figure 16 A, 16B and 16C are the figure that illustrates from the gate line drive signal of the shift register of Fig. 7 output.

With reference to Figure 16 A, when the thin film transistor (TFT) of shift register at room temperature has normality threshold voltage, gate line drive signal (GOUT ₁, GOUT ₂, GOUT ₃...) be similar to square wave, and have about 25 volts consistent peak voltage level.

With reference to Figure 16 B, the threshold voltage of the thin film transistor (TFT) of shift register reduces along with the rising of temperature, the gate line drive signal (GOUT ' ₁, GOUT ' ₂, GOUT ' ₃...) be similar to square wave, but the gate line drive signal (GOUT ' ₁, GOUT ' ₂, GOUT ' ₃...) have a peak voltage level of reduction.Just, first grid polar curve drive signal GOUT ' ₁Peak voltage level have about 20 volts, and second grid line drive signal GOUT ' ₂Peak voltage level be lower than 20 volts.

Shown in Figure 16 B, its waveform puts on the specific gate polar curve as the overlapped signal (override signal) of spark.The gate line drive signal (GOUT ' ₁, GOUT ' ₂, GOUT ' ₃...) owing to overlapped signal has the peak voltage level of reduction, make to produce to have the gate line drive signal of unusual waveforms.

With reference to Figure 16 C, the threshold voltage of the thin film transistor (TFT) of shift register raises along with the reduction of temperature, the gate line drive signal (GOUT " ₁, GOUT " ₂, GOUT " ₃...) be not similar to square wave, and the gate line drive signal (GOUT " ₁, GOUT " ₂, GOUT " ₃...) have a peak voltage level of reduction.Just, first grid polar curve drive signal GOUT " ₁Peak voltage level have about 22 volts, and second grid line drive signal GOUT " ₂Peak voltage level be lower than 22 volts.

When the thin film transistor (TFT) of shift register at room temperature has normality threshold voltage, the shift register operate as normal, and be similar to square wave from the gate line drive signal of shift register output, and have consistent peak voltage level.

Yet, when the threshold voltage of the thin film transistor (TFT) of shift register reduces (or rising) along with temperature and when changing, have unusual waveforms, perhaps consistent peak voltage level from the gate line drive signal of shift register output.Therefore, the undesired conducting of gate line drive signal with unusual waveforms is positioned at the switching device (on-off element) on the LCD panel, and the display quality of liquid crystal display worsens.

As shown in Figure 6, shift register has such circuit structure, wherein the gate line drive signal from previous stage output influences from the gate line drive signal when prime output, especially in liquid crystal display with large display screen size, when the threshold voltage conversion of each thin film transistor (TFT) of shift register and each level were driven by shift register sequence, some grade may do not exported the gate line drive signal.

Figure 17 is the block scheme that the shift register that is used for gate driver circuit of second exemplary embodiment according to the present invention is shown.

With reference to Figure 17, each level of shift register comprise pull portion 171, drop-down part 172, on draw driver portion 173, pull-down driver part 174, the first carry impact damper 275 and the second carry impact damper 276.Therefore in Figure 17, the similar elements in the identical label list diagrammatic sketch 7 will be omitted the detailed description of similar elements.

The first carry impact damper 275 comprises the first carry buffer transistor TR1, and the first clock ckv or second clock ckvb are outputed to next stage.

Specifically, the grid of the first carry buffer transistor TR1 is connected to the input terminal of pull-down driver part 174, the drain electrode of the first carry buffer transistor TR1 is connected to clock terminal CKV or CKVB, and the source electrode of the first carry buffer transistor TR1 is connected to the second carry impact damper 276 of next stage.

The second carry impact damper 276 comprises the second carry buffer transistor TR2 by pull-down driver part 174 or inverter control.Specifically, buffer transistor M3 is by the first clock ckv or the second clock ckvb conducting that provide from the first carry impact damper 275 to put on pull portion 171, the output voltage of pull-down driver part 174 (or inverter) has low voltage level then, and the second carry impact damper 276 turn-offs.Therefore, when carry signal was transferred to the second carry buffer transistor TR2, the voltage level of carry signal can not be lowered.

The drain electrode of the second carry buffer transistor TR2 is connected to the input terminal that draws driver portion 173 on prime, and is connected to the source electrode of the first carry buffer transistor TR1.The grid of the second carry buffer transistor TR2 is connected to the grid of transistor seconds M2 or drop-down part 172, and the source electrode of the second carry buffer transistor TR2 receives first supply voltage by the first power supply voltage terminal VOFF.

In addition, after the cycle, the second carry buffer transistor TR2 keeps conducting state at 1H, pull-down driver part 174 conductings simultaneously, and the first supply voltage Voff put on buffer transistor M3, so that turn-off buffer transistor M3.The first power supply voltage terminal VOFF is same as the power supply voltage terminal VSS of Fig. 5.

Owing to use clock signal to replace gate line drive signal from previous stage output, therefore be independent of the gate line drive signal of previous stage from the gate line drive signal of each grade output as carry signal.

Below, the top one-level of Figure 17 is called previous stage SRC _N, the following one-level of Figure 17 is called as prime SRC _N+1, so that describe the operation of shift register of the present invention.

Previous stage SRC _NCarry buffer transistor TR1 receive the first clock ckv or second clock ckvb, and the first clock ckv or second clock ckvb are transferred to as prime SRC as carry signal _N+1Owing to use clock signal as carry signal, therefore can not take place because the RC delay that the RC load of gate line causes with consistent basically voltage level.

At carry signal CA[N] put on before the grid of the 3rd transistor M3, the 3rd transistor M3 remains in off state.As carry signal CA[N] when putting on the grid of the 3rd transistor M3, after predetermined period, the 3rd transistor M3 conducting to be forming current path, by this current path second source voltage Von that on capacitor C, charges.

When to when capacitor C when charging of drawing driver portion 173 on the prime, the second carry buffer transistor TR2 turn-offs.When prime has idle condition, the supply voltage Voff that puts on the second carry buffer transistor TR2 puts on the grid of buffer transistor M3, and keeps the off state of buffer transistor M3.

Specifically, on prime, draw the 3rd transistor M3 of driver portion 173 to keep off state, and when the first carry buffer transistor TR1 of carry signal by previous stage put on the 3rd transistor M3, it faded to idle condition.Therefore, the grid of the 3rd transistor M3 has the corresponding voltage level of branch pressure voltage that forms with resistance by the resistance of the first carry buffer transistor TR1 and transistor seconds M2.

When the second carry buffer transistor TR2 turn-offs and puts on the grid of buffer transistor M3 such as the carry signal of clock signal, buffer transistor M3 conducting, and voltage Von puts on capacitor C.

Figure 18 is the block scheme that the shift register that is used for gate driver circuit of the 3rd exemplary embodiment according to the present invention is shown.

With reference to Figure 18, each level of shift register comprise pull portion 171, drop-down part 172, on draw driver portion 173, pull-down driver part 174, the first carry impact damper 275 and the second carry impact damper 376.Therefore in Figure 18, the similar elements in the identical label list diagrammatic sketch 7 will be omitted the detailed description of similar elements.

Specifically, the grid of the first carry buffer transistor TR1 is connected to the input terminal of pull-down driver part 174, the drain electrode of the first carry buffer transistor TR1 is connected to clock terminal CKV or CKVB, and the source electrode of carry buffer transistor TR1 is connected to the second carry impact damper 376 of next stage.

The second carry impact damper 376 comprises the second and the 3rd carry buffer transistor TR2 and TR3.Specifically, when the output of drop-down driver portion 174 (or inverter) had low voltage level, the second carry impact damper 376 turn-offed.Therefore, when carry signal was transferred to the second carry impact damper 376, the voltage level of carry signal can not be lowered.In addition, after the cycle, the second carry impact damper 376 keeps conducting state at 1H, and pull-down driver part 174 conductings simultaneously are so that turn-off buffer transistor M3.

The drain electrode of the second carry buffer transistor TR2 is connected to the input terminal that draws driver portion 173 on prime, and is connected to the source electrode of the first carry buffer transistor TR1 of previous stage.The grid of the second carry buffer transistor TR2 is connected to the grid of transistor seconds M2 or drop-down part 172, and the source electrode of the second carry buffer transistor TR2 is connected to the drain electrode of the 3rd carry buffer transistor TR3.The first power supply voltage terminal VOFF is same as the power supply voltage terminal VSS of Fig. 5.

Below, the top one-level of Figure 18 is called previous stage SRC _N, the following one-level of Figure 18 is called as prime SRC _N+1, so that describe the operation of shift register of the present invention.

Previous stage SRC _NCarry buffer transistor TR1 receive the first clock ckv, and the first clock ckv is transferred to as prime SRC as carry signal _N+1Because clock signal has basically consistent voltage level, therefore can not take place because the RC delay that the RC load of gate line causes.

When to when capacitor C when charging of drawing driver portion 173 on the prime, the second carry buffer transistor TR2 turn-offs.When prime has idle condition, the voltage (Voff+Vth) of the 3rd carry buffer transistor TR3 puts on the grid of buffer transistor M3, and keeps the off state of buffer transistor M3.

Specifically, on prime, draw the 3rd transistor M3 of driver portion 173 to keep off state, and when the first carry buffer transistor TR1 of carry signal by previous stage put on the 3rd transistor M3, it faded to idle condition.Therefore, the grid of the 3rd transistor M3 has the corresponding voltage level of component voltage that forms with threshold voltage by the resistance of the resistance of the first carry buffer transistor TR1, the second carry buffer transistor TR2 and the 3rd carry buffer transistor TR3.

When the second carry buffer transistor TR2 turn-offs and carry signal when putting on the grid of buffer transistor M3, buffer transistor M3 conducting, and voltage Von puts on capacitor C.

When the clock with low voltage level such as voltage level Voff put on the grid of buffer transistor M3, this buffer transistor was turn-offed.The conducting of buffer transistor M3 or turn-off time point depend on the voltage level of the voltage of the grid that puts on buffer transistor M3.

The conducting of buffer transistor M3 or turn-off time point are inversely proportional to the threshold voltage of buffer transistor M3.When the threshold voltage of buffer transistor M3 reduces owing to the rising of environment temperature, have the normality threshold voltage condition with buffer transistor M3 and compare, the conducting of buffer transistor M3 or turn-off time point become more early.When the threshold voltage of buffer transistor M3 raise owing to the reduction of environment temperature, the conducting of buffer transistor M3 or turn-off time point were delayed.Therefore, the electric charge that charges in capacitor C changes along with the variation of environment temperature, and the gate line drive signal is along with the voltage that produces owing to the electric charge that charges in capacitor C changes.

Can prevent the generation of overlapped signal.When threshold voltage step-down and the second carry buffer transistor TR2 are not turn-offed fully, overlap signal.But the discharge transistor M5 of overlapped signal conducting previous stage, and the output voltage of the M1 that pulls up transistor of reduction previous stage make and can reduce the gate line drive signal of exporting from previous stage.

According to the 3rd exemplary embodiment of the present invention, the grid of buffer transistor M3 has the corresponding voltage level of component voltage that forms with resistance by the threshold value of the resistance of the second and the 3rd carry buffer transistor TR1, buffer transistor M3 and the first carry buffer transistor TR1.Even the threshold voltage of buffer transistor M3 changes according to the variation of environment temperature, the threshold voltage of the 3rd carry buffer transistor TR3 also changes according to the variation of environment temperature, the voltage level of carry signal depends on environment temperature, and carry signal puts on the grid of buffer transistor M3, thereby offsets the effect that causes owing to variations in threshold voltage.The voltage level change of gate line drive signal can be prevented from.

Figure 19 A and 19B are the figure of output that the shift register of Figure 18 is shown.

Shown in Figure 16 A, when the thin film transistor (TFT) of shift register at room temperature has normality threshold voltage, gate line drive signal (GOUT ₁, GOUT ₂, GOUT ₃...) be similar to square wave.

With reference to Figure 19 A, the threshold voltage of the thin film transistor (TFT) of shift register reduces along with the rising of temperature, the gate line drive signal (GOUT ' ₁, GOUT ' ₂, GOUT ' ₃...) be similar to square wave, and the gate line drive signal (GOUT ' ₁, GOUT ' ₂, GOUT ' ₃...) have about 25 volts.The voltage level of the overlapped signal shown in Figure 19 A is significantly smaller than the overlapped signal shown in Figure 16 B.Normal gate line drive signal is output.

With reference to Figure 19 B, the threshold voltage of the thin film transistor (TFT) of shift register raises along with the reduction of temperature, the gate line drive signal (GOUT " ₁, GOUT " ₂, GOUT " ₃...) be similar to square wave, the gate line drive signal (GOUT " ₁, GOUT " ₂, GOUT " ₃...) have about 25 volts even voltage level.With the gate line drive signal of Figure 16 C (GOUT " ₁, GOUT " ₂, GOUT " ₃...) compare, the gate line drive signal of Figure 19 B (GOUT " ₁, GOUT " ₂, GOUT " ₃...) more be similar to square wave, and the gate line drive signal (GOUT " ₁, GOUT " ₂, GOUT " ₃...) voltage level more consistent.

Shown in Figure 19 A and 19B, because shift register comprises the carry impact damper in each level, therefore even when the threshold voltage of thin film transistor (TFT) changes owing to the variation of environment temperature, the also exportable normal gate line of shift register drive signal.

According to the 3rd exemplary embodiment of the present invention, because each level comprises first, second and the 3rd carry buffer transistor TR1, TR2 and TR3, therefore receive the first clock ckv with consistent voltage level or second clock ckvb as carry signal when prime, and can be independent of from the gate line drive signal of previous stage output from gate line drive signal when prime output.Carry signal compensation variations in threshold voltage.Therefore, shift register is independent of the threshold voltage variation of thin film transistor (TFT), and can improve reliability, throughput rate and the yield rate of making the liquid crystal display with screen sizes.

Figure 20 is the block scheme that the shift register that is used for gate driver circuit of the 4th exemplary embodiment according to the present invention is shown.

With reference to Figure 20, each level of shift register comprise pull portion 171, drop-down part 172, on draw driver portion 173, pull-down driver part 174, the first carry impact damper 275 and the second carry impact damper 476.Therefore in Figure 20, the similar elements in the identical label list diagrammatic sketch 7 will be omitted the detailed description of similar elements.

The second carry impact damper 476 comprises the second and the 4th carry buffer transistor TR2 and TR4.Specifically, when the output of drop-down driver portion 174 (or inverter) had low voltage level, the second carry impact damper 476 turn-offed.Therefore, when carry signal was transferred to the second carry impact damper 476, the voltage level of carry signal can not be lowered.In addition, after the cycle, the second carry impact damper 476 keeps conducting state at 1H, and pull-down driver part 174 conductings simultaneously are so that turn-off buffer transistor M3.

The drain electrode of the second carry buffer transistor TR2 is connected to the input terminal that draws driver portion 173 on prime, and is connected to the source electrode of the first carry buffer transistor TR1 of previous stage.The grid of the second carry buffer transistor TR2 is connected to the grid of transistor seconds M2 or drop-down part 172, and the source electrode of the second carry buffer transistor TR2 receives the first supply voltage Voff by the first power supply voltage terminal VOFF.The first power supply voltage terminal VOFF is same as the power supply voltage terminal VSS of Fig. 5.

The drain electrode of the 4th carry buffer transistor TR4 is connected to the grid of the second carry buffer transistor TR2, the grid of the 4th carry buffer transistor TR4 is connected to the drain electrode of the second carry buffer transistor TR2, and the source electrode of the 4th carry buffer transistor TR4 receives the first supply voltage Voff by the first power supply voltage terminal VOFF.

Below, the top one-level of Figure 20 is called previous stage SRC _N, the following one-level of Figure 20 is called as prime SRC _N+1, so that describe the operation of the shift register of the 4th exemplary embodiment according to the present invention.

When to when drawing the electric charging of capacitor C of driver portion 173 on the prime, the second carry buffer transistor TR2 turn-offs.When prime is in idle condition, the voltage (Voff) of the second carry buffer transistor TR2 puts on the grid of buffer transistor M3, and keeps the off state of buffer transistor M3.

Specifically, on prime, draw the 3rd transistor M3 of driver portion 173 to keep off state.When the first carry buffer transistor TR1 of carry signal by previous stage put on the 3rd transistor M3, the grid of the 3rd transistor M3 had the corresponding voltage level of branch pressure voltage that forms with resistance by the resistance of the first carry buffer transistor TR1 and the second carry buffer transistor TR2.

When the second carry buffer transistor TR2 turn-offs and carry signal when putting on the grid of buffer transistor M3, buffer transistor M3 conducting, and between buffer transistor M3 and capacitor C, form current path, make voltage Von is put on capacitor C.

When the clock with low voltage level such as voltage level Voff put on the grid of buffer transistor M3, buffer transistor M3 turn-offed.

When the carry signal that produces from previous stage puts on the grid of the 4th carry buffer transistor TR4, the 4th carry buffer transistor TR4 conducting, thus reduce the voltage level of the grid of the second carry buffer transistor TR2 fast.Just, the 4th carry buffer transistor TR4 improves the switching speed of the second carry buffer transistor TR2.Therefore, can improve the operating speed of carry impact damper.

Figure 21 is the block scheme that the shift register that is used for gate driver circuit of the 5th exemplary embodiment according to the present invention is shown.

With reference to Figure 21, each level of shift register comprise pull portion 171, drop-down part 172, on draw driver portion 173, pull-down driver part 174, the first carry impact damper 275 and the second carry impact damper 576.Therefore in Figure 21, the similar elements in the identical label list diagrammatic sketch 7 will be omitted the detailed description of similar elements.

The first carry impact damper 275 comprises the first carry buffer transistor TR1, and the first clock ckv or second clock ckvb are outputed to next stage.Specifically, the grid of the first carry buffer transistor TR1 is connected to the input terminal of pull-down driver part 174, the drain electrode of the first carry buffer transistor TR1 is connected to clock terminal CKV or CKVB, and the source electrode of carry buffer transistor TR1 is connected to the second carry impact damper 576 of next stage.

The second carry impact damper 576 comprises second, third and the 4th carry buffer transistor TR2, TR3 and TR4.Specifically, when the output of drop-down driver portion 174 (or inverter) had low voltage level, the second carry impact damper 576 turn-offed.Therefore, when carry signal was transferred to the second carry impact damper 576, the voltage level of carry signal can not be lowered.In addition, after the cycle, the second carry impact damper 576 keeps conducting state at 1H, and pull-down driver part 174 conductings simultaneously are so that turn-off buffer transistor M3.

The drain electrode of the second carry buffer transistor TR2 is connected to the input terminal that draws driver portion 173 on prime, and is connected to the source electrode of the first carry buffer transistor TR1 of previous stage.The grid of the second carry buffer transistor TR2 is connected to the grid of transistor seconds M2 or drop-down part 172, and the source electrode of the second carry buffer transistor TR2 is connected to the drain electrode of the 3rd carry buffer transistor TR3.

The drain and gate of the 3rd carry buffer transistor TR3 is common mutually to be connected, and is connected to the source electrode of the second carry buffer transistor TR2 and the source electrode of the 3rd carry buffer transistor TR3.The source electrode of the 3rd carry buffer transistor TR3 receives the first supply voltage Voff by the first power supply voltage terminal VOFF.The first power supply voltage terminal VOFF is same as the power supply voltage terminal VSS of Fig. 5.

According to the 5th exemplary embodiment of the present invention, because the carry impact damper also comprises the 4th carry buffer transistor TR4 of the conducting or the shutoff that are used to control the second carry buffer transistor TR2, therefore can improve the switching speed of the second carry buffer transistor TR2.

Figure 22 is the figure that is illustrated in the voltage that the capacitor of Figure 21 measures.Especially, the voltage when the carry impact damper has the 4th carry buffer transistor TR4, measured of ' A ' expression partly at the capacitor place, and part ' B ' expression when the carry impact damper does not have the 4th carry buffer transistor TR4 at the voltage of capacitor place measurement.

As shown in figure 22, when adding the 4th carry buffer transistor TR4 to the carry impact damper, can reduce by the turn-off time of the second carry buffer transistor TR2, can reduce conducting or the turn-off time of the 3rd transistor M3, thereby can improve the voltage of measuring at the capacitor place.Therefore, carry impact damper with the 4th carry buffer transistor TR4 can be used for having in large display screen size and the high-resolution liquid crystal display, the conducting of the 3rd transistor M3 or shutoff can be controlled by maximum voltage, and can improve the performance of shift register.

As described in embodiment above of the present invention, replacement is from the output signal (or gate line drive signal) of the lead-out terminal OUT output of previous stage, the carry impact damper that will be used for producing the carry signal of the output signal that is independent of previous stage is installed in each level, thereby prevents the shift register abnormal operation that the threshold voltage variation owing to thin film transistor (TFT) causes.In addition, can improve the reliability of shift register in the environment temperature on a large scale, and, therefore can improve the yield rate of making shift register owing to can improve the variations in threshold voltage tolerance limit.

Figure 23 is the figure that illustrates from the gate line drive signal of the shift register of Fig. 7 output.Figure 23 represents as clock signal V[CKVB] when putting on each grade, from the waveform of the output voltage (or voltage of node N2) of pull-down driver part (or inverter) output.V[GOUT (1)] output voltage of the first order that changes according to output voltage of expression from inverter output, and V[GOUT (2)] the partial output voltage that changes according to the output voltage of inverter of expression.

With reference to Figure 23, the output voltage of exporting from inverter has slow gradient, perhaps slowly rises to high-voltage level from low voltage level.Just, the operating speed of inverter is slow.

The gradient of inverter depends on the resistance of inverter and the stray capacitance C1 of pull-down transistor M2.R * C1 value is big more, and the gradient of inverter is just slow more, and the operating speed of inverter is just slow more.

Especially, when gate driver circuit or shift register drive be positioned at LCD panel with large display screen size on thin film transistor (TFT) be connected gate line the time, since on draw with the transistor size of pull-down transistor M1 and M2 and increase, draw on therefore the stray capacitance with pull-down transistor M1 and M2 also to increase.Transistor size is meant the ratio (W/L) of transistorized channel width (W) and transistorized channel length (L).Thereby R * C1 increases, and the gradient of inverter slows down.

The size of inverter needs to increase, so that improve the operating speed of inverter.In order to increase the size of inverter, need bigger layout area, and the power consumption of inverter increases.Therefore, the size of inverter need minimize.Yet when inverter was designed to have minimum dimension, the operating speed of inverter was slow.

As shown in figure 23, slow when the operating speed of inverter, particularly the output voltage of inverter is when low voltage level slowly fades to high-voltage level, and the gate line drive signal is V[Gout (1) for example], V[Gout (2)] pulse width greater than 1H.1H is meant the pulse width of clock signal.From the pulse width of the gray-scale voltage of data driving circuit 160 output also is 1H.

For example, the pixel that is connected to the lead-out terminal OUT of first grid polar curve is put on the influence of the gray-scale voltage of the data line that is connected to next gate line that is connected with next stage.Therefore, when V[Gout (1)] pulse width during greater than 1H, image displaying quality is worsened.Usually, the minimum value of gray-scale voltage is about 0 volt, gate line drive signal V[Gout (n)] the effective impulse width preferably be less than or equal to 1H.Gate line drive signal V[Gout (n)] the effective impulse width be meant gate line drive signal V[Gout (n)] in have pulse width greater than the part of 0 volt voltage level.Especially, worsen in order to alleviate image displaying quality, when the voltage level of inverter when low level fades to high level, the voltage level of gate line drive signal needs fade to low level from high level apace, and gate line drive signal V[Gout (n)] the effective impulse width preferably be less than or equal to H.

Below, be described in and have minimum inverter size under the restriction of layout area and can prevent the shift register that image displaying quality worsens.

Figure 24 is the block scheme that the cell level of the shift register that is used for gate driver circuit of the 6th exemplary embodiment according to the present invention is shown.

With reference to Figure 24, cell level comprises buffer transistor 808, keep transistor 806, discharge transistor 804, inverter 808, pull up transistor 810 and pull-down transistor 812.The cell level of Figure 24 and the cell level of Fig. 7 have some differences.

At first, the size of the size of the size of the inverter 808 of Figure 24, the M1 that pulls up transistor and pull-down transistor M2 is identical with Fig. 7.Yet pull-down transistor M2 is divided into the first pull-down transistor M2a and the second pull-down transistor M2b.For example, when the transistor size of the pull-down transistor M2 of Fig. 7 was 1, the transistor size ratio between the first pull-down transistor M2a and the second pull-down transistor M2b can be 0.1: 0.9.Best, the transistor size of the second pull-down transistor M2b is greater than the size of the first pull-down transistor M2a.

The second, the first pull-down transistor M2a is driven by the output voltage of inverter 808, the second pull-down transistor M2b by on draw driver transistor M5 and from the gate line drive signal V[Gout (n+1) of next stage output] drive.Draw the charge discharge of driver transistor M5 on second in capacitor C, charging.

Because the second pull-down transistor M2b is by the gate line drive signal V[Gout (n+1) from next stage output] drive, so gate line drive signal V[Gout (n)] the effective impulse width can be less than or equal to 1H.In addition, the transistor size with first pull-down transistor M2a of capacitive load reduces, and the operating speed of inverter improves.

Figure 25 is the figure that illustrates from the gate line drive signal of the shift register of Figure 24 output.Especially, Figure 25 illustrate when the transistor size ratio between the first pull-down transistor M2a and the second pull-down transistor M2b is about 0.1: 0.9, from the gate line drive signal of shift register output.

With reference to Figure 25, from the gate line drive signal V[Gout (n) of the shift register of Figure 25 output] the effective impulse width be less than or equal to 1H, and the output voltage gradient of the inverter of Figure 25 is suddenly in the output voltage gradient of the inverter of Figure 23.The operating speed of the inverter of Figure 25 is faster than the operating speed of the inverter of Figure 23.

Figure 26 illustrates from the gate line drive signal of the shift register of Fig. 7 output with from the figure of the gate line drive signal of the shift register output of Figure 24.Figure 26 illustrates the output voltage of the inverter of Figure 23 and 25 simultaneously.The output voltage of the inverter of Figure 23 is V[INVERTER '], the output voltage of the shift register of Figure 23 is V[Gout '], the output voltage of the inverter of Figure 25 is V[INVERTER], and the output voltage of the shift register of Figure 25 is V[Gout].

With reference to Figure 26, the gradient of the output voltage V [INVERTER] of the inverter 808 of Figure 24 in rise of output voltage along greater than the output voltage V of the inverter of Figure 23 [INVERTER '].With reference to Figure 26 ' A ' and ' A "; compare with the voltage level of the output voltage V of the shift register of Figure 23 [Gout ']; the voltage level of the output voltage V of the shift register of Figure 24 [Gout] fades to low level from high level more quickly, thereby gate line drive signal V[Gout (n)] the effective impulse width can be less than or equal to 1H.

Figure 27 is the power supply of the 7th exemplary embodiment according to the present invention and the block scheme of clock generator.

With reference to Figure 27, power supply can be a DC to DC converter 710, and the output supply voltage Von of DC to DC converter 710 puts on clock generator 720 and shift register 170.Clock generator 720 receives supply voltage Von and Voff, and clocking ckv and ckvb, to provide clock signal ckv and ckvb to shift register 170.Just, clock generator 720 and shift register 170 are driven by same power supplies voltage Von.

Figure 28 be illustrate when will the supply voltage identical putting on shift register with the supply voltage of the clock generator that puts on Figure 27, from the figure of the gate line drive signal of shift register output.

With reference to Figure 28, when same power supplies voltage Von puts on clock generator 720 and shift register 170, gate line drive signal V[Gout (1) ' from first order output] variation that is shown as the output voltage of the inverter 808 (or drop-down driving transistors M6 and M7) according to the first order changes, and from the gate line drive signal V[Gout (2) ' of second level output] variation that is shown as according to the output voltage of partial inverter 808 (or drop-down driving transistors M6 and M7) changes.

When same power supplies voltage Von put on clock generator 720 and shift register 170, the maximal voltage level of clock signal was substantially the same in the high level of supply voltage Von.

When same power supplies voltage Von put on clock generator 720 in the liquid crystal display with large display screen size and shift register 170, image displaying quality can increase along with the capacitive load owing to gate line and worsen.

As shown in figure 28, gate line drive signal V[Gout (1) '] pulse width greater than 1H (pulse width of clock signal).Usually, the minimum value of gray-scale voltage is about 0 volt, gate line drive signal V[Gout (n)] the effective impulse width preferably be less than or equal to 1H.Especially, in order to alleviate the deterioration of image displaying quality, when from the voltage level of the output voltage of inverter 808 output when low level fades to high level, the voltage level of gate line drive signal needs fade to low level from high level apace, and gate line drive signal V[Gout (n)] the effective impulse width preferably be less than or equal to 1H.

Because the operating speed of inverter 808 (or pull-down transistor M6 and M7) is slow, so gate line drive signal V[Gout (1) '] pulse width greater than 1H.Shown in the part A 1 ' and A2 ' of Figure 28, owing to have slow gradient or slowly rise to high level from low level from the output voltage of inverter 808 outputs, therefore, gate line drive signal V[Gout (1) '] and V[Gout (2) '] voltage level near part A 1 ' and A2 ', slowly reduce under the low level.Therefore, gate line drive signal V[Gout (1) '] and V[Gout (2) '] the effective impulse width greater than 1H.

As V[Gout (n) '] effective impulse width during greater than 1H, the pixel that is connected to the lead-out terminal OUT of n gate line is put on the influence of the gray-scale voltage of the data line that is connected to next gate line ((n+1) gate line) that is connected with next stage.Therefore, image displaying quality can be worsened.The voltage level of the output voltage of inverter 808 need fade to high level apace from low level, makes V[Gout (n) '] the effective impulse width can be not more than 1H.Just, the gradient of the output voltage of inverter needs big.Can increase the amplitude of output voltage of inverter, the feasible output voltage gradient that can increase inverter.

Figure 29 is the power supply of the 7th exemplary embodiment according to the present invention and the block scheme of clock generator.

With reference to Figure 29, DC to DC converter 910 produces supply voltage Von, and supply voltage Von is put on clock generator 720.DC to DC converter 910 produces another supply voltage Vona, and supply voltage Vona is put on shift register 170.Supply voltage Vona has the voltage level different with supply voltage Von.Just, the supply voltage Vona that is different from supply voltage Von puts on shift register 170.

Best, the amplitude of supply voltage Vona is greater than the amplitude of supply voltage Von, so that keep the maximum output voltage of the maximum output voltage of inverter 808 greater than the inverter of Figure 28.

Figure 30 is the exemplary circuit figure that the DC to DC converter of Figure 29 is shown.Figure 30 illustrates the DC to DC converter that is used to produce greater than the supply voltage Vona of supply voltage Von.

With reference to Figure 30, DC to DC converter receives DC voltage VDD, and produces supply voltage Von (VDD+ Δ V) and supply voltage Vona (VDD+2 Δ V) by charge pump circuit.For example, charge pump circuit comprises a plurality of diode D1, D2, D3 and D4 and a plurality of capacitor C2, C3, C4 and the C5 of mutual series connection.

DC voltage VDD puts on the anode of diode D1, and Δ V puts on capacitor C2, and exports Von (VDD+ Δ V) from the negative electrode of diode D2.Von puts on the anode of diode D3, and Δ V puts on capacitor C4, and exports Vona (VDD+2 Δ V) from the negative electrode of diode D4.Therefore, Vona (＞Von) and Von can produce by charge pump circuit.In addition, Vona (＞Von) and Von can produce by voltage level offset device (shifter) circuit.Von can change, and Vona also can be independent of Von and changes.

When Vona (＞when Von) putting on shift register 170, shown in Fig. 7 and 29, inverter 808 is driven by the Vona that the drain electrode by transistor M6 puts on shift register.Thereby the output voltage of the inverter 808 that is driven by Vona increases the output voltage of the inverter that is driven by Von.In addition, the voltage level of the output voltage of inverter fades to high level apace from low level.Therefore, V[Gout (n)] the effective impulse width be essentially 1H or be not more than 1H, and image displaying quality can not worsened.

Figure 31 be illustrate when the power supply of Figure 29 and clock generator drive shift register, from the figure of the gate line drive signal of shift register output.

In Figure 28, about 25 volts Von puts on inverter 808, and the maximum output voltage of inverter 808 is about 15 volts.In Figure 31, about 45 volts Von puts on inverter 808, and the maximum output voltage of inverter 808 is about 35 volts.Therefore, about the part B1 and the B1 ' on the rise of output voltage edge of inverter, V[Gout (1)] and V[Gout (1)] the effective impulse width less than the effective impulse width among Figure 28.

Figure 32 be illustrate when the power supply of Figure 29 and 28 and clock generator drive shift register, from the figure of the gate line drive signal of shift register output.

With reference to Figure 32, V[Gout '] the gate line drive signal of expression when clock generator and shift register are driven by same power supplies voltage Von.V[Gout] expression puts on clock generator and gate line drive signal when putting on shift register greater than the Vona of Von as Von.

About the part A and the A ' of the negative edge of the output voltage of inverter, V[Gout] the effective impulse width be narrower than V[Gout '] the effective impulse width.

Though the foregoing description has been discussed the shift register of the gate line that is used to drive liquid crystal display, the present invention also can be used in the organic electroluminescent display device.

Though describe exemplary embodiment of the present invention and advantage thereof in detail, should be appreciated that under the situation that does not break away from the scope of the present invention that is defined by the following claims, can carry out various changes, replacement and change to it.

Claims

1. shift register comprises the level of a plurality of cascades, and these levels receive first clock signal and second clock signals, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and each level comprises:

The carry impact damper is used for providing carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases;

Last pull portion is used for providing first scan line driving signal corresponding to first clock signal or second clock signal to lead-out terminal;

Drop-down part is used for providing first supply voltage to lead-out terminal;

On draw driver portion, be used to respond the carry signal that provides from previous stage and pull portion in the conducting, and second scan line driving signal of response next stage and turn-off pull portion; And

The pull-down driver part is used to respond the carry signal that provides from previous stage and turn-offs drop-down part, and second scan line driving signal of response next stage and the drop-down part of conducting.

2. shift register as claimed in claim 1, wherein the carry impact damper comprises the first transistor, it is used for reception first of first drain electrode or second clock signal by the first transistor, the first source electrode with the output signal of response pull-down driver part by the first transistor outputs to next stage with carry signal, and this output signal puts on the first grid electrode of the first transistor.

3. shift register as claimed in claim 2, wherein adjacent on the position of pull portion form the first transistor so that with first or the second clock signal offer next stage on draw driver portion.

4. shift register as claimed in claim 2 is wherein gone up pull portion and is comprised transistor seconds,

The pull-down section branch comprises the 3rd transistor, and the first transistor comprises:

First grid electrode is from the second grid wiring branch of transistor seconds;

First drain electrode is from the main drain electrode wiring branch of transistor seconds; And

The first source electrode gets around pull portion and drop-down part the 3rd grid with the drop-down part that is extended to next stage.

5. shift register as claimed in claim 4, wherein the first source electrode of the first transistor is received the 3rd grid of the drop-down part of next stage by the bridging that forms between first source electrode line and the 3rd gate line.

6. liquid crystal display comprises:

Array of display cells forms on transparency carrier, and this array of display cells comprises many gate lines, many data lines and a plurality of on-off element, and on-off element is coupled in gate line and data line;

Data driving circuit is used for providing picture signal to every data line; And

Gate driver circuit comprises shift register, and this shift register comprises the level of a plurality of cascades, and these levels receive first clock signal and second clock signal, produce a plurality of gate line drive signals that are used to select gate line with order, and each level comprises:

Last pull portion is used for providing first grid polar curve drive signal corresponding to first clock signal or second clock signal to lead-out terminal;

Drop-down part is used for providing first supply voltage to lead-out terminal;

On draw driver portion, be used to respond the carry signal that provides from previous stage and pull portion in the conducting, and the second grid line drive signal of response next stage and turn-off pull portion; And

The pull-down driver part is used to respond the carry signal that provides from previous stage and turn-offs drop-down part, and the second grid line drive signal of response next stage and the drop-down part of conducting.

7. method that drives shift register, this shift register comprises the level of a plurality of cascades, these levels receive first clock signal and second clock signal, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, each grade comprises the carry impact damper that is used to provide carry signal, and this method comprises:

Provide carry signal corresponding to first clock signal or second clock signal to next stage, the second clock signal has and the first clock signal opposite phases;

Response produces first scan line driving signal corresponding to first clock signal or second clock signal from the carry signal of previous stage output; And

Response reduces from second scan line driving signal of next stage output from first voltage level when first scan line driving signal of prime output.

8. method as claimed in claim 7, wherein carry signal has second voltage level corresponding to first clock signal or second clock signal, and is independent of parasitic resistor and the capacitor parasitics that produces from sweep trace.

9. method as claimed in claim 7 also comprises: after predetermined period, respond first voltage level of first scan line driving signal and reduce from second voltage level of the carry signal of previous stage output.

10. shift register comprises the level of a plurality of cascades, and the first order receives scan start signal, and these levels receive first clock signal and second clock signals, produce a plurality of scan line driving signals that are used to select the multi-strip scanning line with order, and each level comprises:

The first carry impact damper is used for providing first carry signal corresponding to first clock signal or second clock signal to next stage, and the second clock signal has and the first clock signal opposite phases;

Last pull portion is used for providing first scan line driving signal corresponding to first clock signal or second clock signal to first lead-out terminal;

Drop-down part is used for providing first supply voltage to first lead-out terminal;

On draw driver portion, be used to respond from second carry signal of the first carry impact damper output of previous stage and pull portion in the conducting, and second scan line driving signal of response next stage and turn-off pull portion;

The pull-down driver part is used to respond first carry signal that provides from the first carry impact damper of previous stage and turn-offs drop-down part, and second scan line driving signal of response next stage and the drop-down part of conducting; And

The second carry impact damper is used to reduce by first voltage level of second carry signal, exports first carry signal to put on pull portion from the first carry impact damper of previous stage.

11. shift register as claimed in claim 10, wherein the first carry impact damper comprises the first transistor, it is used for reception first of first drain electrode or second clock signal by the first transistor, the first source electrode with the output signal of response pull-down driver part by the first transistor outputs to next stage with carry signal, and this output signal puts on the first grid electrode of the first transistor.

12. shift register as claimed in claim 10, wherein the second carry impact damper comprises transistor seconds, and transistor seconds comprises:

Second drain electrode, be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion;

Second gate electrode is coupled in drop-down part; And

The second source electrode is used to receive first supply voltage.

13. shift register as claimed in claim 10, wherein the second carry impact damper comprises:

Transistor seconds, its second drain electrode be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion, its second gate electrode is coupled in drop-down part, and its second source electrode is coupled in the 3rd transistorized the 3rd drain electrode; And

The 3rd transistor, its 3rd drain electrode and the 3rd gate electrode coupled in common are in the second source electrode, and its 3rd source electrode is used to receive first supply voltage.

14. shift register as claimed in claim 10, wherein the second carry impact damper comprises:

Transistor seconds, its second drain electrode be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion, its second gate electrode is coupled in drop-down part, and its second source electrode is used to receive first supply voltage; And

The 3rd transistor, its 3rd drain electrode is coupled in second gate electrode of transistor seconds, and its 3rd gate electrode is coupled in second drain electrode of transistor seconds, and its 3rd source electrode is used to receive first supply voltage.

15. shift register as claimed in claim 10, wherein the second carry impact damper comprises:

Transistor seconds, its second drain electrode be coupled in previous stage the first carry impact damper second lead-out terminal and on draw the input terminal of driver portion, its second gate electrode is coupled in drop-down part, and its second source electrode is coupled in the 3rd transistorized the 3rd drain electrode;

The 3rd transistor, its 3rd drain electrode and the 3rd gate electrode coupled in common are in the second source electrode of transistor seconds, and its 3rd source electrode is used to receive first supply voltage; And

The 4th transistor, its 4th drain electrode is coupled in second gate electrode of transistor seconds, and its 4th gate electrode is coupled in second drain electrode of transistor seconds, and its 4th source electrode is used to receive first supply voltage.

16. a liquid crystal display comprises:

Array of display cells is formed on the transparency carrier, and this array of display cells comprises many gate lines, many data lines and a plurality of on-off element, and on-off element is coupled in gate line and data line;

Gate driver circuit, comprise shift register, this shift register comprises the level of a plurality of cascades, the first order receives scan start signal, these levels receive first clock signal and second clock signal, produce a plurality of gate line drive signals that are used to select many gate lines with order, each level comprises:

Last pull portion is used for providing first grid polar curve drive signal corresponding to first clock signal or second clock signal to first lead-out terminal;

On draw driver portion, be used to respond from second carry signal of the first carry impact damper output of previous stage and pull portion in the conducting, and the second grid line drive signal of response next stage and turn-off pull portion;

The pull-down driver part is used to respond first carry signal that provides from the first carry impact damper of previous stage and turn-offs drop-down part, and the second grid line drive signal of response next stage and the drop-down part of conducting; And

The second carry impact damper is used to reduce by first voltage level of second carry signal, exports first carry signal from the first carry impact damper of previous stage and puts on pull portion.