CN101567160B - GIP type liquid crystal display panel and detecting method thereof - Google Patents
GIP type liquid crystal display panel and detecting method thereof Download PDFInfo
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- CN101567160B CN101567160B CN 200910052224 CN200910052224A CN101567160B CN 101567160 B CN101567160 B CN 101567160B CN 200910052224 CN200910052224 CN 200910052224 CN 200910052224 A CN200910052224 A CN 200910052224A CN 101567160 B CN101567160 B CN 101567160B
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- shift register
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10128—Display
- H05K2201/10136—Liquid Crystal display [LCD]
Abstract
The invention relates to a GIP type liquid crystal display panel and a detecting method thereof. The liquid crystal display panel is integrated with a grid driver; the grid driver comprises a plurality of cascaded displacement registers; each displacement register comprises a setting input terminal, a clock signal input terminal, a level input terminal, a carry output terminal and a grid wire output terminal; wherein the first displacement register is provided with a setting input terminal lead, a clock signal input terminal lead and a level input terminal lead; each displacement register is provided a grid wire output terminal lead; the grid wire output terminal lead is connected with a TFT switch; the grid of the TFT switch is connected with a drive testing point CP; and a source electrode is connected with an output testing point TP. The GIP type liquid crystal display panel and the detecting method thereof check and test the GIP drive unit in an array engineering, thus avoiding a GIP drive unit with defects from entering a box forming engineering.
Description
Technical field
The present invention relates to a kind of display panels and detection method thereof, particularly relate to a kind of GIP type display panels and detection method thereof with screen inner grid driver.
Background technology
In the flat pannel display field, liquid crystal indicator is used in the terminal presentation facility of various sizes widely because it has in light weight, characteristics such as volume is little, thin thickness.As shown in Figure 1, in general, a display panels comprises formations such as drives module 11, backlight module 12, time polaroid 13, TFT (thin film transistor (TFT)) infrabasal plate 14, CF (color filter) upper substrate 16 and last polaroid 17, filling liquid crystal molecular layer 15 in two substrates 14 and 16 up and down, this liquid crystal layer externally deflects under the driving of electric field, also change thereupon of its yawing moment of difference along with external electrical field shows thereby present different GTGs.
For traditional liquid crystal display, its driving circuit as shown in Figure 2, it is made up of gate drivers 21 and source electrode driver group 22.Wherein gate drivers 21 is used for the gate driving line of gating horizontal direction, source electrode driver 22 is used for corresponding gray scale voltage is write the source drive line of vertical direction, thereby the deflection of liquid crystal molecule is changed to realize showing the function of different GTGs thereupon.In the LCD of reality, gate drivers 21 and source electrode driver 22 all are to be connected with liquid crystal panel 25 respectively with 24 via COF (chip on film) 23.In order further to save cost, especially save COF, a kind of gate drivers directly is produced on technology on the liquid crystal panel, promptly GIP (gate in plane) technology produces thereupon.
For the GIP technology, the framework of its gate drivers is varied, it generally speaking is the shift register that a plurality of cascades are set on the substrate of liquid crystal panel, the gating that comes the controlling level gate line by shift register with close, with replace in traditional liquid crystal panel gate driving IC be connected used COF.
Can save cost though adopt the GIP framework, but existing GIP technology all be the array engineering with become the box engineering after can show just whether inspection good with the driver element of judging GIP, if driver element goes wrong in the array engineering, that could be checked after also can only waiting until into the box engineering, cause the unnecessary waste on the means of production.
Summary of the invention
Technical matters to be solved by this invention provides a kind of display panels and detection method thereof with screen inner grid driver, just can in advance the GIP driver element be checked and test in the array engineering.
The present invention solves the problems of the technologies described above the technical scheme that adopts to provide a kind of display panels with screen inner grid driver, be integrated with gate drivers on the described liquid crystal panel, described gate drivers comprises the shift register of a plurality of cascades, and each shift register comprises set input, clock signal input terminal, level input end, carry output terminal and gate line output terminal; The set input of shift register carry output terminal at the corresponding levels and next shift register links to each other, clock signal input terminal links to each other with positive and negative clock signal respectively by parity rows, the set input of first order shift register links to each other with outside original levels signal, and drives shift register output gate line drive signals at different levels under the effect of this level signal successively; Wherein, described first order shift register is provided with set input lead-in wire, clock signal input terminal lead-in wire and level input end lead-in wire, every grade of shift register is provided with gate line output terminal lead-in wire, described gate line output terminal lead-in wire links to each other with the TFT switch, the grid of described TFT switch links to each other with driving test point CP, and source electrode links to each other with output test point TP.
In the display panels of above-mentioned band screen inner grid driver, be in series with the TFT protection switch before the described TFT switch, the grid of described TFT protection switch directly links to each other with drain electrode.
The present invention may further comprise the steps for solving the problems of the technologies described above the display panels detection method that a kind of above-mentioned band screen inner grid driver also is provided:
A) aaset bit input end, clock signal input terminal and level input end lead-in wire apply asserts signal, clock signal and level signal respectively;
B) drive test point CP input triggering level signal, opening the TFT switch of shift registers at different levels;
C) detect outputs level signals at output test point TP;
D) corresponding each asserts signal is if output test point TP the gate line drive signal of continuous whole occurs then judges that gate drivers is normal, if drive signal occurs intermittently then can judge the gate drivers defectiveness.
The present invention contrasts prior art following beneficial effect: the display panels and the detection method thereof of band screen inner grid driver provided by the invention, in the array engineering, just can in advance the GIP driver element be checked and test, improved in original GIP processing procedure can only the array engineering with become the box engineering after the phenomenon that could check the GIP driver element, the GIP driver element of having avoided defective originally having occurred in the array engineering enters into the box engineering, thereby has saved the means of production.
Description of drawings
Fig. 1 is the structural representation of liquid crystal indicator in the prior art.
Fig. 2 is that liquid crystal indicator drives synoptic diagram in the prior art.
Fig. 3 is a kind of GIP type display panels configuration diagram of the present invention.
Fig. 4 is the testing fixture synoptic diagram of corresponding diagram 3.
Fig. 5 is the GIP driver element work schedule synoptic diagram just often of corresponding diagram 4.
Fig. 6 is the work schedule synoptic diagram 1 of the GIP driver element of corresponding diagram 4 when unusual.
Fig. 7 is the work schedule synoptic diagram 2 of the GIP driver element of corresponding diagram 4 when unusual.
Fig. 8 is an another kind of GIP type display panels configuration diagram of the present invention.
Fig. 9 is the testing fixture synoptic diagram of corresponding diagram 8.
Figure 10 is the GIP driver element work schedule synoptic diagram just often of corresponding diagram 9.
Figure 11 is the work schedule synoptic diagram 1 of the GIP driver element of corresponding diagram 9 when unusual.
Figure 12 is the work schedule synoptic diagram 2 of the GIP driver element of corresponding diagram 9 when unusual.
Among the figure:
11 driving circuits, 12 backlights
13 times polaroid 14 infrabasal plates
15 liquid crystal molecules, 16 upper substrates
Polaroid 21 gate drivers on 17
22 source electrode drivers, 23,24 COF
25 liquid crystal panels
Embodiment
The invention will be further described below in conjunction with accompanying drawing and exemplary embodiments.
Fig. 3 is a kind of GIP type display panels configuration diagram of the present invention.
Please refer to Fig. 3, screen inner grid driver of the present invention comprises the shift register SR (i) of a plurality of cascades, wherein i=1 ... n, n are natural number.Wherein SR (1)～SR (n-1) is the shift register that drives corresponding gate line, and SR (n) is as the dummy register.For each shift register SR (i), its input end comprises level signal end VGH and VGL, and asserts signal end SET and clock signal terminal CKVO/CVKE, output terminal comprise gate line output terminal GOUT, carry output terminal COUT and reset terminal RESET.
Concrete principle of work is described as follows: the SET termination of each shift register is received from the signal of the shift register COUT end of the upper level beginning clock signal as shift register at the corresponding levels, and the RESET termination is received the signal from the GOUT end of the shift register of next stage.For first shift register, its SET termination is received outside STV signal signal to start with.The VGH end of each shift register is connected with external drive voltage to receive driving voltage, and VGL is connected to receive the accurate position of low-voltage with the accurate position of outside low-voltage.The CKVO/CVKE termination is received external timing signal, and both phase places are opposite, and respectively in order to the adjacent gate driving line of driven, such as the gate driving line of CKVO in order to driving odd number code, and CKVE is in order to drive the gate driving line of even number code.Receive the STV signal to start with during signal when the SET termination, the output terminal GOUT of each shift register is corresponding to the high level of corresponding clock signal, thus the output of exporting corresponding gate line; The RESET end is then exported the drive signal of next stage.
Please continue with reference to Fig. 4, the present invention is at the input port of array base palte one side from first shift register, comprise that VGH, VGL, SET and CKVO/CVKE end is provided with lead-in wire and test point (Test pad) STV, VGL, CKVO, CKVE and VGH respectively, and TFT switch Ni and Ti (i=1 are set at output port GOUT (i) end of each shift register of the opposite side of substrate ... n-1) and output lead and test point CP and TP.Wherein switch Ni is as protection switch, be connected on described TFT switch Ti before, the grid of described TFT protection switch Ni directly links to each other with drain electrode.Certainly, the present invention also can directly test gate line output terminal lead-in wire, but does the complicacy that can increase design like this, increases cost.Because there is not the TFT switch, just need test lead be set to the output terminal of each row, counter plate, its grid are generally all at row up to a hundred even thousands of, and therefore switch not being set is a very complex engineering.
Adopt above-mentioned testing fixture, can detect the GIP unit easily, concrete steps are as follows:
A) aaset bit input end SET, clock signal input terminal CKVO/CVKE and level input end VGH, VGL lead-in wire applies asserts signal, clock signal and level signal respectively, see also Fig. 5, wherein, clock signal phase on the CKVO/CVKE end is opposite, and VGH holds input high level, VGL end input low level (figure does not show), the concrete numerical value of its voltage is different in each concrete condition, in general, VGH should be about 30V, and VGL is about-7V;
B) drive test point CP input triggering level signal, opening the TFT switch of shift registers at different levels;
C) detect outputs level signals at output test point TP;
D) corresponding each asserts signal is if the gate line drive signal of continuous whole appears in output test point TP
Judge that then gate drivers is normal, if drive signal occurs intermittently then can judge the gate drivers defectiveness.
Specifically, if the whole operate as normal of GIP driver element, shift registers at different levels are exported the gate line drive signal successively, and then the waveform from the output of TP test point should be the gate line drive signal of continuous whole, as shown in Figure 5.If there be i driver element unusual, then interrupting can appear in drive signal, and its typical abnormal work sequential shows that synoptic diagram as shown in Figure 6.If broken string appears in the shift register of cascade, have only the previous section shift register can operate as normal so, the work schedule synoptic diagram when its typical GIP driver element is unusual is as shown in Figure 7.If there are several driver elements unusual in the GIP device, then perhaps can be inconsistent with Fig. 6 or Fig. 7 from the waveform of its TP test point output, may occur repeatedly interrupting, need the concrete condition concrete analysis, but must not normal complete output waveform, therefore still can judge that defective appears in the GIP drive unit from the waveform of TP test point output.
Fig. 8 is an another kind of GIP type display panels configuration diagram of the present invention, and Fig. 9 is the testing fixture synoptic diagram of corresponding diagram 8.
Please refer to Fig. 8 and Fig. 9, each shift register SR (i) of the present invention, its input end comprises clock signal input terminal CK1, level input end FR and GV, set input SET, output terminal comprise gate line output terminal GOUT, carry output terminal COUT, reset terminal RESET and clock signal output terminal CK2.
Concrete principle of work is described as follows: the SET termination of each shift register is received from the signal of the shift register COUT end of the upper level beginning clock signal as shift register at the corresponding levels, the RESET termination is received the signal from the GOUT end of the shift register of next stage, and the CK1 termination is received the output from the CK2 end of upper level shift register.For first shift register, its SET termination is received outside STV signal signal to start with.The GV end of each shift register is connected with the external power source low-voltage to receive the accurate position of low-voltage.The CK1 termination is received external timing signal, and adjacent shift register receives different clock signals, and such as the shift register reception CKV signal of odd number code, and the shift register of even number code receives the CKVB signal.Receive the STV signal to start with during signal when the SET termination, the output terminal GOUT of each shift register is corresponding to the high level of corresponding clock signal, thus the output of exporting corresponding gate line; The RESET end is then exported the drive signal of next stage.
Please continue with reference to Fig. 9, the present invention is at the input port of array base palte one side from first shift register, comprise that GV, SET and CK1 end is provided with lead-in wire and test point (Test pad) VGL, STV, CKV, CKVB respectively, and TFT switch Ni and Ti (i=1 are set at output port GOUT (i) end of each shift register of the opposite side of substrate ... n-1) and output lead and test point CP and TP.Wherein switch Ni is as protection switch, connects the samely, and the INT end frame reset terminal of first SR receives the signal of the carry output terminal of last SR, does not therefore need terminal lead.
Concrete testing procedure is identical, and Figure 10 is the GIP driver element output waveform of continuous whole just often, the output waveform when Figure 11 and Figure 12 are common GIP driver element defectiveness.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (3)
1. the display panels with screen inner grid driver is integrated with gate drivers on the described liquid crystal panel, and described gate drivers comprises:
The shift register of a plurality of cascades, each shift register comprise set input, clock signal input terminal, level input end, carry output terminal and gate line output terminal;
The set input of shift register carry output terminal at the corresponding levels and next shift register links to each other, clock signal input terminal links to each other with positive and negative clock signal respectively by parity rows, the set input of first order shift register links to each other with outside original levels signal, and drives shift register output gate line drive signals at different levels under the effect of this level signal successively;
It is characterized in that, described first order shift register is provided with set input lead-in wire, clock signal input terminal lead-in wire and level input end lead-in wire, every grade of shift register is provided with gate line output terminal lead-in wire, described gate line output terminal lead-in wire links to each other with the TFT switch, the grid of described TFT switch links to each other with driving test point CP, and source electrode links to each other with output test point TP.
2. the display panels of band screen inner grid driver according to claim 1 is characterized in that be in series with the TFT protection switch before the described TFT switch, the grid of described TFT protection switch directly links to each other with drain electrode.
3. the detection method of the display panels of a band screen inner grid driver as claimed in claim 1 is characterized in that described method comprises the steps:
A) aaset bit input end, clock signal input terminal and level input end lead-in wire apply asserts signal, clock signal and level signal respectively;
B) drive test point CP input triggering level signal, opening the TFT switch of shift registers at different levels;
C) detect outputs level signals at output test point TP;
D) corresponding each asserts signal is if output test point TP the gate line drive signal of continuous whole occurs then judges that gate drivers is normal, if drive signal occurs intermittently then can judge the gate drivers defectiveness.
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| CN 200910052224 CN101567160B (en) | 2009-05-31 | 2009-05-31 | GIP type liquid crystal display panel and detecting method thereof |
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| CN 200910052224 CN101567160B (en) | 2009-05-31 | 2009-05-31 | GIP type liquid crystal display panel and detecting method thereof |
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| CN101567160A CN101567160A (en) | 2009-10-28 |
| CN101567160B true CN101567160B (en) | 2011-02-09 |
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| TWI476742B (en) * | 2010-12-06 | 2015-03-11 | Au Optronics Corp | Multiplex driving circuit |
| CN103280177B (en) * | 2012-12-05 | 2016-05-18 | 上海中航光电子有限公司 | Gate drivers and detection method thereof |
| CN103927956B (en) * | 2013-12-24 | 2017-02-08 | 上海中航光电子有限公司 | Drive circuit of display panel, display panel and display device |
| CN104505045B (en) * | 2014-12-29 | 2017-04-12 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, gate drive circuit and fault detection method of gate drive circuit |
| CN104535620B (en) * | 2015-01-16 | 2017-05-24 | 友达光电(厦门)有限公司 | Display panel and crack detection method thereof |
| CN104575385B (en) * | 2015-01-17 | 2017-09-19 | 昆山工研院新型平板显示技术中心有限公司 | Organic light-emitting display device array base palte and detection method |
| CN105355163B (en) * | 2015-12-22 | 2019-01-04 | 昆山国显光电有限公司 | GIP signal deteching circuit, GIP signal detecting method and panel display apparatus |
| CN105590607B (en) * | 2016-03-10 | 2018-09-14 | 京东方科技集团股份有限公司 | Gate driving circuit and its detection method, array substrate, display device |
| CN106019672A (en) * | 2016-07-26 | 2016-10-12 | 武汉华星光电技术有限公司 | Making method for thin film transistor array substrate |
| CN106782246B (en) * | 2017-01-05 | 2020-07-31 | 昆山国显光电有限公司 | GIP signal test circuit, GIP signal test method and display device |
| CN107068033B (en) * | 2017-01-25 | 2020-12-08 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit, test method and display device |
| CN108154833A (en) * | 2018-01-03 | 2018-06-12 | 京东方科技集团股份有限公司 | The output detection circuit and its method of a kind of gate driving circuit, display device |
| CN111816107B (en) | 2019-04-11 | 2021-12-28 | 合肥京东方卓印科技有限公司 | Shifting register unit, grid driving circuit and method thereof and display device |
| CN110428760A (en) * | 2019-06-27 | 2019-11-08 | 重庆惠科金渝光电科技有限公司 | A kind of display panel test method, display panel and display device |
| CN111123591A (en) * | 2019-12-26 | 2020-05-08 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
| CN111599297B (en) * | 2020-06-19 | 2023-12-15 | 京东方科技集团股份有限公司 | Test circuit, test method and display device |
| CN112992024B (en) * | 2021-02-08 | 2022-10-14 | 昆山龙腾光电股份有限公司 | Display device and detection method thereof |
| CN112992094B (en) * | 2021-02-23 | 2022-09-09 | 福建华佳彩有限公司 | GIP circuit driving method and display device |
| CN114863872A (en) * | 2022-05-27 | 2022-08-05 | 武汉华星光电半导体显示技术有限公司 | Display module and display device |
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