KR101335678B1 - Level Shifter using oxide TFTs and Scan Driving Circuit having the Level Shifter - Google Patents

Abstract

Since the level shifter and the scan driving circuit according to the present invention are composed of only a single oxide thin film transistor and can be embedded in a display panel, the display driving apparatus can be miniaturized and manufacturing costs can be reduced. In addition, the level shifter and the scan driving circuit according to the present invention can overcome the limitation of the unitary structure because the pull-up transistors are connected in a latch structure and can be pulled, and the oxide thin film transistor is turned off in the standby state, thereby consuming unnecessary power. Can be reduced.

Description

Level shifter using oxide TFTs and Scan Driving Circuit having the Level Shifter}

The present invention relates to a level shifter using an oxide thin film transistor and a scan driving circuit including the same, and more particularly, a level shifter configured to be embedded in a display panel using an oxide thin film transistor, and to have low power consumption and full swing. The present invention relates to a scan driving circuit including the same.

The present invention is derived from a study conducted as part of the IT source technology development project of the Ministry of Knowledge Economy [Task Management Number: 2006-S-079-04, Task name: Smart window using a transparent electronic device].

A level shifter is a circuit for converting an input signal having a predetermined voltage level into an output signal having a voltage level different from that of the input signal. A level shifter is located between circuits having different magnitudes of signal voltage, and thus is transmitted between circuits. It is mainly used to convert the size of.

In particular, a low voltage of about 5V is required for the digital circuit inside the display driving apparatus, but a high voltage of about 10 to 30V is required for the scan driving circuit for driving the display panel according to the characteristics of the display panel. Essentially included.

FIG. 1A is a diagram illustrating a conventional level shifter, and FIG. 1B is a diagram illustrating an operation waveform of the level shifter illustrated in FIG. 1A.

Referring to FIG. 1A, a conventional level shifter 100 includes first and second N-type transistors N1 and N2 and first and second P-type transistors P1 and P2.

When the non-inverting input signal V _IN becomes a high level, the first N-type transistor N1 is turned on so that the inverted output signal V _OUTB is discharged to the ground voltage VSS. Accordingly, the second P-type transistor ( P2) is turned on. At this time, since the second N-type transistor N2 is turned off by the low level inverting input signal V _INB , the voltage of the non-inverting output signal V _OUT is raised to the power supply voltage VDDH to thereby generate the second N-type transistor N2. 1 P-type transistor P1 is turned off. On the contrary, when the inverting input signal V _INB becomes high, the second N-type transistor N2 and the first P-type transistor P1 are turned on, and the first N-type transistor N1 and the second P-type transistor are turned on. P2 is turned off.

In an ideal operation of the level shifter 100 illustrated in FIG. 1A, when the first and second P-type transistors P1 and P2 are turned on, the first and second N-type transistors N1 and N2 are turned off, respectively. Voltage levels can be changed quickly and reliably without significant power consumption.

However, when the current driving capabilities of the first and second N-type transistors N1 and N2 and the first and second P-type transistors P1 and P2 are similar, the first N-type transistor N1 is turned on from the turned off state. When the second P-type transistor P2 is weakly turned on when it is changed to or when the second N-type transistor N2 is turned on by being turned off, the first P-type transistor P1 may be weakly turned on by this. As a result, a short circuit current is generated between the power supply voltage VDDH and the ground voltage VSS, thereby increasing power consumption.

In order to solve this problem, there is a method of increasing the discharge rate of the output terminal by increasing the size of the first, second N-type transistors (N1, N2), but this method increases the circuit area as the size of the transistor increases. There is this.

On the other hand, in recent years, in order to miniaturize a display driving apparatus, development of a level shifter which can be incorporated in a display panel is required.

However, in order to embed the level shifter in the display panel, the elements used in the level shifter must be made of the same or compatible material as the elements used in the backplane of the display panel.

Currently, amorphous silicon (a-Si: H) thin film transistors and low temperature poly-silicon thin film transistors are mainly used for the backplane of display panels. In the case of amorphous silicon thin film transistor, the P-type device is not suitable for making a driving circuit due to its low mobility, and the N-type device is used. In the case of low-temperature polysilicon thin film transistor, the current driving capability is excellent in the N-type device, but it is insensitive to noise. The P-type element of a simple manufacturing process is used.

In the case of an oxide thin film transistor (Oxide Thin Flim Transistor), which is expected to replace these thin film transistors, development using an N-type thin film transistor having excellent current driving capability is becoming mainstream.

With this trend, research is being conducted to implement a level shifter used in a display driving device as a single structure using only an N-type oxide thin film transistor.

However, in the case of the single-level level shifter using the N-type transistor, it is easy to pull down the output signal to the ground voltage VSS, but it is difficult to pull up the output signal to the power supply voltage VDDH. In addition, the single-type structure using the P-type transistor is easy to pull up to the power supply voltage (VDDH), but there is a problem that it is difficult to pull down the output signal to the ground voltage (VSS).

In order to solve this problem, a level shifter using bootstrapping has been proposed.

FIG. 2A illustrates a conventional level shifter using bootstrapping, and FIG. 2B illustrates an operation waveform of the level shifter illustrated in FIG. 2A.

If Figures 2a and FIG 2b, the boot in the conventional level shifter 200 using the strapping when the voltage of the input signal (V _IN) changes from the low level to the high level input signal (V _IN), the first oxide film by The transistor N1 is turned on so that the output signal V _OUT is pulled down to the ground voltage VSS. At this time, the third oxide thin film transistor N3 is turned on to charge the voltage of VDDH-V _TH3 to the capacitor C1 connected to the first node A.

Conversely input signal (V _IN) voltage in this case changes from the high level to the low level, the voltage of the first oxide thin film transistor a first node (A) As the (N1) is turned off by the input signal (V _IN) about 2VDDH of Increased to -V _TH3 . At this time, the bootstrapping effect is caused by the coupling of the capacitor C1, and as a result, the output signal V _OUT is pulled up to the power supply voltage VDDH.

In the level shifter 200 using such bootstrapping, the oxide thin film transistor should not flow current in the standby state in which the gate-source voltage V _GS is 0V in an ideal case.

However, since the oxide thin film transistor having a negative threshold voltage does not operate as an enhanced mode device but as a depletion mode device, the gate-source voltage V _GS is 0V. There is a problem of consuming power even in the standby state.

An object of the present invention is to implement a level shifter that can be embedded in a display panel using an oxide thin film transistor and has a low power consumption and a full swing, and a scan driving circuit including the same.

In order to achieve the above object, a level shifter according to the present invention includes: a pull-down part including a plurality of N-type oxide thin film transistors for pulling down an output signal to a ground voltage according to a non-inverting input signal; And a pull-up part including a plurality of N-type oxide thin film transistors configured to pull up an output signal to a power supply voltage according to an inverted input signal, wherein the plurality of N-type oxide thin film transistors constituting the pull-up part are connected in a latch structure to receive the output signal. Characterized in that the pull-up to the power supply voltage.

The pull-down part includes first and second oxide thin film transistors that pull down voltages of the first and second nodes to ground voltages according to the first and second non-inverting input signals input to the gates, and the first and second inputs to the gates. The semiconductor device may further include third and fourth oxide thin film transistors which pull down voltages of the third and fourth nodes to ground voltages according to the non-inverting input signal.

The pull-up unit may include a fifth oxide thin film transistor having an inverted input signal input to a gate, and a gate connected to a source of the fifth oxide thin film transistor to pull up a voltage of the second node to a power supply voltage according to the inverted input signal. And a seventh oxide thin film transistor connected to the sixth oxide thin film transistor in a latch structure to pull up the voltage of the first node to a power supply voltage according to the voltage of the second node. The pull-up unit may include: an eighth oxide thin film transistor configured to have a gate connected to the source of the sixth oxide thin film transistor to increase a current driving capability of the sixth oxide thin film transistor, and a gate of the seventh oxide thin film transistor. And a ninth oxide thin film transistor connected to increase a current driving capability of the seventh oxide thin film transistor.

When the first and second non-inverting input signals are high level and the inverting input signal is low level, the first to fourth oxide thin film transistors included in the pull-down part by the first and second non-inverting input signals All of them are turned on so that the output signal is pulled down to the ground voltage, and the fifth to ninth oxide thin film transistors included in the pull-up part are all turned off by the inverting input signal to the first to fourth nodes. No current flows. On the contrary, when the first and second non-inverting input signals are low level and the inverting input signal is high level, the first to fourth oxides included in the pull-down part by the first and second non-inverting input signals. All of the thin film transistors are turned off so that no current flows from the first to fourth nodes toward the ground voltage, and the fifth to ninth oxide thin film transistors included in the pull-up part are all turned on by the inverting input signal. The signal is pulled up to the supply voltage.

The low level VSSL of the first and second non-inverting input signals and the inverting input signal may be lower than the low level VSS of the output signal.

In order to achieve the above object, a scan driving circuit according to the present invention includes an input unit for outputting a high level or low level non-inverting input signal and an inverting input signal to a level shifter according to an output signal of a front end; A level shifter for outputting a low level or high level output signal according to the non-inverting input signal and the inverting input signal; And a buffer unit for stabilizing and outputting an output signal output from the level shifter, wherein the input unit, the level shifter, and the buffer unit are configured of a plurality of N-type oxide thin film transistors.

The input unit may include first and second oxide thin film transistors respectively transmitting low and high level voltages to a first node according to a first clock signal input to a gate and an output signal of the previous stage, and respectively input to a gate. Third and fourth oxide thin film transistors that transfer low and high level voltages to the second node according to the voltage of the first node and the first clock signal, and the first and second nodes according to the second clock signal. And fifth and sixth oxide thin film transistors configured to output voltages of the inverted input signal and the non-inverted input signal, respectively.

The level shifter may include first and second capacitors connected to the fifth and sixth oxide thin film transistors, a seventh and eighth oxide thin film transistors to which the non-inverting input signal and the inverting input signal are respectively input to a gate, and a gate to the gate. A ninth oxide thin film transistor configured to drop a voltage of a fifth node connected to a drain to a low level according to an input third clock signal, and a gate connected to a source of the eighth oxide thin film transistor so that the fifth oxide thin film transistor is connected to the source of the eighth oxide thin film transistor; A tenth oxide thin film transistor for raising a voltage of a five node to a high level, an eleventh oxide thin film transistor for lowering a voltage of a sixth node connected to a drain to a low level according to a fourth clock signal input to a gate, 10 is connected to the oxide thin film transistor in a latch structure to lower the voltage of the sixth node according to the voltage of the fifth node. And a twelfth oxide thin film transistor to rise to a level.

The buffer unit may include a thirteenth and fourteenth oxide thin film transistors configured to transfer low-level and high-level voltages to a seventh node, respectively, in response to a third clock signal input to a gate and a voltage of the fifth node. And a fifteenth and sixteenth oxide thin film transistors configured to transfer low-level and high-level voltages to an eighth node according to the third clock signal and the voltage of the seventh node.

Here, the first clock signal is a signal having a phase opposite to the output signal of the previous stage, and periodically becomes a high level and a low level, and the second clock signal is the inverted input signal and the non-inverted input signal A signal for transferring to the level shifter or cutting off the connection between the input unit and the level shifter. The third clock signal is an output signal of the level shifter after the output signal of the front end is changed from a high level to a low level. The fourth clock signal is a signal for generating positive feedback when the output signal of the level shifter is raised to a high level.

The level shifter outputs a low level output signal to the buffer unit according to the third clock signal of a high level until the output signal of the front end is changed from a high level to a low level, and the output signal of the front end is a high level. After the change from the low level to the low level shifter, the level shifter outputs a high level output signal to the buffer unit according to the third clock signal having a low level.

Since the level shifter and the scan driving circuit according to the present invention are composed of only a single oxide thin film transistor and can be embedded in a display panel, the display driving apparatus can be miniaturized and manufacturing costs can be reduced.

In addition, the level shifter and the scan driving circuit according to the present invention can overcome the limitation of the unitary structure because the pull-up transistors are connected in a latch structure to allow full swing.

In addition, since the oxide thin film transistor included in the level shifter and the scan driving circuit according to the present invention is surely turned off in the standby state, unnecessary power consumption can be reduced.

FIG. 1A is a diagram illustrating a conventional level shifter, and FIG. 1B is a diagram illustrating an operation waveform of the level shifter illustrated in FIG. 1A.
FIG. 2A illustrates a conventional level shifter using bootstrapping, and FIG. 2B illustrates an operation waveform of the level shifter illustrated in FIG. 2A.
3A is a diagram illustrating a level shifter according to a first embodiment of the present invention, and FIG. 3B is a diagram illustrating an operation waveform of the level shifter illustrated in FIG. 3A.
4A to 4F are diagrams illustrating a level shifter according to a second embodiment of the present invention.
FIG. 5A is a diagram illustrating a general scan driving circuit, and FIG. 5B is a diagram showing an operation waveform of the scan driving circuit shown in FIG. 5A.
6A is a diagram illustrating a scan driving circuit including a level shifter according to the present invention, and FIG. 6B is a diagram illustrating an operation waveform of the scan driving circuit illustrated in FIG. 6A.
FIG. 7 illustrates that the scan driving circuit illustrated in FIG. 6A is connected to each line of the display panel.

Before describing the present invention, the basic concept of the present invention will be briefly described as follows.

First, in order to implement a level shifter that can be embedded in a display panel, a level shifter having a single structure is implemented using only an oxide thin film transistor.

Next, in order to overcome the limitation of the single structure, the present invention implements a level shifter capable of full swing by connecting pull-up transistors in a latch structure.

Finally, the present invention implements a level shifter that can reduce unnecessary power consumption by ensuring that the oxide thin film transistor is turned off in a standby state (pull down state) in which the output is low.

Such structural features will be more clearly understood through the following examples.

(Embodiment 1)

3A is a diagram illustrating a level shifter according to a first embodiment of the present invention, and FIG. 3B is a diagram illustrating an operation waveform of the level shifter illustrated in FIG. 3A.

Referring to FIG. 3A, the level shifter 300 according to an embodiment of the present invention may output an output signal V _OUT according to a first non-inverting input signal V _IN and a second non-inverting input signal V _INS . A pull-down unit 300A that pulls down to the ground voltage VSS, and _pulls up the output signal V _OUT to the power supply voltage VDDH according to the inverting input signal V _INB . And a pull-up part 300B.

Referring to FIG. 3B, the first and second non-inverting input signals V _IN and V _INS and the inverting input signal V _INB have a voltage value of VDD at a high level and a voltage value of VSSL at a low level. Has The output signal V _OUT has a voltage value of VDDH higher than VDD at a high level, and has a voltage value of VSS higher than VSSL at a low level.

The first non-inverting input signal (V _IN) is the second non-inverted after having a phase opposite to the inverted input signal (V _INB), the inverting input signal (V _INB) is changed from the low level to the high level The input signal V _INS is changed from high level to low level. Here, the second non-inverting input signal V _INS serves to pull up the output signal V _OUT to the power supply voltage VDDH during a pull-up operation, which will be described in detail below.

The pull-down unit 300A includes first to fourth oxide thin film transistors N1 to N4 having a source connected to the ground voltage VSS to perform a pull-down operation, and the pull-up unit 300B has a drain supply voltage. And fifth to ninth oxide thin film transistors N5 to N9 connected to the VDDH to perform a pull-up operation.

It is preferable that the first to ninth oxide thin film transistors N1 to N9 are N-type oxide thin film transistors.

The first and second oxide thin film transistors N1 and N2 may ground voltages of the first and second nodes A and B according to the first and second non-inverting input signals V _IN and V _INS input to the gate. The third and fourth oxide thin film transistors N3 and N4 are also pulled down to VSS, and the third and fourth nodes C, according to the first and second non-inverting input signals V _IN and V _INS , which are also input to the gate. Pull down the voltage of D) to ground voltage (VSS).

The pull-down unit 300A and the pull-up unit 300B are connected to each other through the first to fourth nodes A to D, and an output signal V _OUT is output from the first node A.

The fifth oxide thin film transistor N5 outputs the inverted input signal V _INB input to the gate to the gate of the sixth oxide thin film transistor N6.

The sixth oxide thin film transistor N6 _{pulls up} a voltage of the second node B connected to a source to a power supply voltage VDDH according to the inverted input signal V _INB input to a gate, and the second node. The voltage of (B) is input to the gate of the eighth oxide thin film transistor N8. The eighth oxide thin film transistor N8 pulls up the voltage of the fourth node D connected to the source to the power supply voltage VDDH according to the voltage of the second node B input to the gate.

The voltage of the fourth node D pulled up to the power supply voltage VDDH is input to the gate of the seventh oxide thin film transistor N7, and the seventh oxide thin film transistor N7 is input to the gate. According to the voltage of the node (D) pulls up the voltage of the first node (A) connected to the source to the power supply voltage (VDDH).

The voltage of the first node A is input to the gate of the ninth oxide thin film transistor N9, and the ninth oxide thin film transistor N9 is input according to the voltage of the first node A input to the gate. The voltage of the third node C connected to the source is pulled up to the power supply voltage VDDH.

That is, the sixth oxide thin film transistor N6 and the seventh oxide thin film transistor N7 are connected in a latch structure, and to increase the current driving capability of the sixth and seventh oxide thin film transistors N6 and N7, respectively. The eighth oxide thin film transistor N8 is connected to the sixth oxide thin film transistor N6, and the ninth oxide thin film transistor N9 is connected to the seventh oxide thin film transistor N7.

By the latch structure, the output signal V _OUT is smoothly pulled up to the power supply voltage VDDH during the pull-up operation, thereby allowing the pull swing to be described later.

Looking at the operation of the level shifter 300 having such a structure in detail as follows.

First, a process of pulling down the output signal V _OUT to the ground voltage VSS will be described.

When the first non-inverting input signal V _IN and the second non-inverting input signal V _INS become low level to high level, all of the first to fourth oxide thin film transistors N1 to N4 are turned on. The voltages of the first to fourth nodes A to D become the ground voltage VSS, and accordingly, the output signal V _OUT is pulled down to the ground voltage VSS.

At this time, since all of the fifth to ninth oxide thin film transistors N5 to N9 are turned off, no current flows from the power supply voltage VDDH toward the first to fourth nodes A to D, thereby consuming unnecessary power. Can be reduced.

Next, a process of pulling up the output signal V _OUT to the power supply voltage VDDH will be described.

When the inverting input signal V _INB goes from a low level to a high level, the fifth oxide thin film transistor N5 is turned on, and accordingly, a threshold voltage of the fifth oxide thin film transistor N5 is applied at a power supply voltage VDDH. (V _TH) voltage (VDDH-V _TH) obtained by subtracting the said sixth is caught in the gate of the oxide thin film transistor (N6) of claim 6 wherein the oxide thin film transistor (N6) is also turned on.

When the sixth oxide thin film transistor N6 is turned on, the eighth oxide thin film transistor N8 is also turned on.

In this case, the second non-inverting input signal V _INS is changed from a high level to a low level, thereby turning off the second and fourth oxide thin film transistors N2 and N4.

When the second and fourth oxide thin film transistors N2 and N4 are turned off, the turned-off second and fourth oxide thin film transistors N2 and N4 flow out of the second and fourth nodes B and D. The voltage of the second and fourth nodes B and D is increased to the power supply voltage VDDH.

The seventh oxide thin film transistor N7 is turned on by the voltage of the fourth node D raised to the power supply voltage VDDH, so that the output signal V _OUT is pulled up to the power supply voltage VDDH. The ninth oxide thin film transistor N9 is turned on.

At this time, the sixth and eighth oxide thin film transistors N6 and N8 are continuously turned on by the latch structure until the output signal V _OUT is fully pulled up to the power supply voltage VDDH, thereby enabling full swing. do.

In addition, since the first to fourth oxide thin film transistors N1 to N4 are reliably turned off by the first and second non-inverting input signals V _IN and V _INB having a low level VSSL. Since no current flows from the first to fourth nodes A to D toward the ground voltage VSS, unnecessary power consumption may be reduced.

As described above, the level shifter 300 according to the present invention is composed of only the oxide thin film transistors N1 to N9 so that the level shifter 300 may be embedded in the display panel, thereby miniaturizing the display driving apparatus and reducing the manufacturing cost.

In addition, the conventional single-level level shifter has a problem in that pull-swing is difficult due to a poor pull-up operation. The advantage is that full swings are possible.

In addition, the conventional single-level level shifter has a problem in that unnecessary power consumption occurs in the standby state, but the oxide thin film transistors included in the level shifter 300 according to the present invention are certainly turned off in the standby state, and thus standby In this state, unnecessary power consumption can be reduced.

(Second Embodiment)

4A to 4F are diagrams illustrating a level shifter according to a second embodiment of the present invention.

First, as illustrated in FIG. 4A, a buffer unit 300C including tenth and eleventh oxide thin film transistors N10 and N11 may be connected to an output terminal of a level shifter to stabilize an output signal. As shown in FIG. 4B, the level shifter shown in FIG. 4A may be configured to perform a pull up / pull down operation on one non-inverting input signal V _IN .

Next, as illustrated in FIG. 4C, the latch structure may be simplified by omitting the fourth and eighth oxide thin film transistors N4 and N8 from the level shifter shown in FIG. 4A. In this case, as shown in FIG. 4D, the level shifter illustrated in FIG. 4C may be configured to perform a pull up / pull down operation on one non-inverting input signal V _IN .

Next, as shown in FIG. 4E, the latch structure may be simplified by omitting the third and ninth oxide thin film transistors N3 and N9 from the level shifter shown in FIG. 4C. In this case, as shown in FIG. 4F, the level shifter illustrated in FIG. 4E may be configured to perform a pull-up / pull-down operation on one non-inverting input signal V _IN .

The level shifter illustrated in FIGS. 4B, 4D, and 4F outputs an output signal V _OUT having a phase opposite to that of the input signal V _IN , and thus may be used as an inverter for inverting and outputting the input signal.

However, in the case of FIGS. 4C to 4F, the structure is simplified, but the current driving capability may be slightly lower than that of the level shifter illustrated in FIG. 4A.

(Third Embodiment)

The level shifter according to the present invention may be applied to a scan driving circuit, and the scan driving circuit will be briefly described as follows to help understanding of the present invention.

FIG. 5A is a diagram illustrating a general scan driving circuit, and FIG. 5B is a diagram showing an operation waveform of the scan driving circuit shown in FIG. 5A.

5A and 5B, the scan driving circuits SC ₁ to SC _N may include a shift register 510, a mask 530, and a level shifter 550 including a multiplexer 511 and a D-flip-flop 513. And a buffer 570, respectively, and sequentially apply a scan signal to each line of the display panel.

When a scan signal output from the scan driving circuits SC ₁ to SC _N is applied to each line, an image is displayed according to the data signal input from the data driving circuit in the pixels connected to each line.

However, the scan drive circuits SC ₁ to SC _N having such a structure have a problem that it is difficult to integrate them into the display panel because both the N-type transistor and the P-type transistor are used in the level shifter 550 (see FIG. 1A). have.

To this end, in the present invention, a scan driving circuit is implemented by using a level shifter composed of only an oxide thin film transistor, which will be described in more detail as follows.

6A is a diagram illustrating a scan driving circuit including a level shifter according to the present invention, and FIG. 6B is a diagram illustrating an operation waveform of the scan driving circuit illustrated in FIG. 6A.

Referring to FIG. 6A, the scan driving circuit 600 according to the present invention includes an input unit 600A for outputting a non-inverting input signal and an inverting input signal to the level shifter 600B according to the output signal OUT _{N -1 at the} front end. ), A level shifter 600B for outputting a low level or high level output signal according to the non-inverting input signal and the inverting input signal output from the input unit 600A, and a level shifter 600B output from the level shifter 600B. And a buffer unit 600C for stabilizing and outputting the output signal.

The input unit 600A includes first to sixth oxide thin film transistors N1 to N6, and the level shifter 600B includes first and second capacitors C1 and C2 and seventh to twelfth oxide thin film transistors ( N7 to N12, and the buffer unit 600C includes thirteenth to sixteenth oxide thin film transistors N13 to N16.

The first to sixteenth oxide thin film transistors N1 to N16 may be N-type oxide thin film transistors.

The first and second oxide thin film transistors N1 and N2 have a low level VSS and a high level VDDH according to a first clock signal IN1 input to a gate and an output signal OUT _{N -1} of the previous stage, respectively. ) Is transferred to the first node A, respectively.

Similarly, the third and fourth oxide thin film transistors N3 and N4 have a low level VSS and a high level according to the voltage of the first node A and the first clock signal IN1 input to the gate. The voltage of VDDH is transferred to the second node B, respectively.

The fifth and sixth oxide thin film transistors N5 and N6 respectively convert the voltages of the first and second nodes A and B to the third and fourth nodes C and D according to the second clock signal IN2. Output

Here, the voltage of the third node C is output as an inverting input signal to the level shifter 600B, and the voltage of the fourth node D is output as a non-inverting input signal to the level shifter 600B. do.

This structure is the same as the structure in which the inverted input signal for the pull-up operation and the non-inverted input signal for the pull-down operation are input to the level shifter 300 shown in FIG. 3A. Therefore, in the following description, the output signal rises to the high level VDDH and falls to the low level VSS is interpreted in the same sense as the output signal pulled up to the power supply voltage VDDH and pulled down to the ground voltage VSS. Can be.

The first and second capacitors C1 and C2 are connected to the fifth and sixth oxide thin film transistors N5 and N6, respectively, and the fourth node is provided at a gate of the seventh and eighth oxide thin film transistors N7 and N8. The voltage of (D) and the voltage of the third node C are respectively input.

The ninth oxide thin film transistor N9 lowers the voltage of the fifth node E connected to the drain to a low level VSS according to the third clock signal IN3 input to the gate, and the tenth oxide thin film The transistor N10 has a gate connected to the source of the eighth oxide thin film transistor N8 to raise the voltage of the fifth node E to a high level VDDH according to the voltage of the third node C. .

The eleventh oxide thin film transistor N11 drops the voltage of the sixth node F connected to the drain to a low level VSS according to the fourth clock signal IN4 input to the gate. N12 is connected to the tenth oxide thin film transistor N10 in a latch structure to increase the voltage of the sixth node F to a high level VDDH according to the voltage of the fifth node E. FIG. Here, the voltage of the fifth node E is output to the buffer unit 600C.

The thirteenth and fourteenth oxide thin film transistors N13 and N14 have a low level VSS and a high level VDDH according to voltages of the third clock signal IN3 and the fifth node E, which are respectively input to a gate. Voltage is transferred to the seventh node G, respectively.

Similarly, the fifteenth and sixteenth oxide thin film transistors N15 and N16 have a low level VSS and a high voltage according to the voltages of the third clock signal IN3 and the seventh node G respectively input to a gate. The voltage of the level VDDH is transferred to the eighth node H, respectively. Here, the voltage of the eighth node H is output from the buffer unit 600C.

The operation of the scan driving circuit 600 having such a structure will be described in more detail with reference to FIG. 6B as follows.

For convenience of explanation, the waveform of the signal illustrated in FIG. 6B will be briefly described as follows.

The first to fourth clock signals IN1 to IN4 have a voltage value of VDD at a high level and a voltage value of VSSL at a low level. The output signal OUT _{N -1} and the output signal V _{OUT of the previous} stage have a voltage value of VDDH higher than VDD at a high level, and a voltage value of VSS higher than VSSL at a low level.

The first clock signal (IN1) is said first clock if having the opposite phase to each other and the output signal (OUT _{N -1)} of the front end, is held at the low level output signal (OUT _{N -1)} of the front end The signal IN1 periodically goes to a high level and a low level.

The second clock signal IN2 is a signal that goes from a high level to a low level at the same time as the output signal OUT _{N -1} of the previous stage. When the second clock signal IN2 is at a high level, the inversion is performed. An input signal and the non-inverting input signal are transmitted to the level shifter 600B, and the connection between the input unit 600A and the level shifter 600B is cut off when the second clock signal IN2 is at a low level. .

The third clock signal IN3 is a signal from the high level to the low level after the output signal OUT _{N -1} of the front end is changed to the low level. The third clock signal IN3 is connected to the front end of the front end by the third clock signal IN3. After the output signal OUT _{N -1} is completely changed to the low level, the output signal of the level shifter 600B is raised to the high level so that the stable high level output signal OUT _N is passed through the buffer unit 600C. Is output.

The fourth clock signal IN4 is a signal from the high level to the low level before the output signal OUT _{N -1 of the} previous stage is changed to the low level. The fourth clock signal IN4 corresponds to the level by the fourth clock signal IN4. Positive feedback is generated when the output signal of the shifter 600B rises to a high level. In more detail, when the eleventh oxide thin film transistor N11 is turned off by the fourth clock signal IN4 and the voltage of the sixth node F rises to a high level, the tenth oxide thin film Transistor N10 is turned on. At this time, the current flowing through the tenth oxide thin film transistor N10 generates positive feedback when the third clock signal IN3 becomes low level, and the output of the level shifter 600B is generated by the positive feedback. The signal rises to high level.

First, the operation in the first section S1 at which the output signal OUT _{N -1 at} the front end is at a high level will be described.

When the output signal OUT _{N -1} of the previous stage having the high level is input to the gate of the second oxide thin film transistor N2, the second oxide thin film transistor N2 is turned on and the voltage of the first node A is turned on. This becomes VDDH. At this time, the first and fourth oxide thin film transistors N1 and N4 are reliably turned off by the first clock signal IN1 having the low level VSSL.

When the voltage of the first node A becomes VDDH, the third oxide thin film transistor N3 is turned on so that the voltage of the second node B becomes VSS.

In this state, when the fifth and sixth oxide thin film transistors N5 and N6 are turned on by the second clock signal IN2, the voltage of the third node C becomes VDDH and the fourth node D. ) Is set to VSS so that the seventh oxide thin film transistor N7 is turned off and the eighth oxide thin film transistor N8 is turned on.

When the eighth oxide thin film transistor N8 flows through the current and the tenth oxide thin film transistor N10 is turned on, the voltage of the fifth node E becomes VDDH, and thus the twelfth oxide thin film transistor N12. ) Is also turned on.

In this case, the ninth oxide thin film transistor N9 is turned on by the third clock signal IN3 having a high level. Accordingly, the ninth oxide thin film transistor N9 is turned on from the tenth oxide thin film transistor N10. As a current flows through the furnace, the voltage of the fifth node E is lowered from VDDH to VSS. Similarly, the eleventh oxide thin film transistor N11 is also turned on by the fourth clock signal IN4 having a high level so that a current flows from the twelfth oxide thin film transistor N12 to the eleventh oxide thin film transistor N11. Accordingly, the voltage of the sixth node F is also lowered from VDDH to VSS.

When the voltage of the fifth node E becomes VSS, the fourteenth oxide thin film transistor N14 is turned off to lower the voltage of the seventh node G to VSS. N16 is also turned off so that the output signal OUT _N becomes VSS.

Secondly, the operation in the second section S2 when the output signal OUT _{N -1 at} the front end goes from the high level to the low level will be described.

First, the eleventh oxide thin film transistor N11 is turned off by the fourth clock signal IN4 having a low level, and the voltage of the sixth node F is increased to VDDH.

In this case, since the ninth oxide thin film transistor N9 is turned on, the voltage of the fifth node E maintains VSS. Accordingly, the 14th and 16th oxide thin film transistors N14 and N16 are turned off. Thus, the output signal OUT _N maintains VSS as it is.

Next, the fifth and sixth oxide thin film transistors N5 and N6 are turned off by the second clock signal IN2 having a low level, thereby connecting the input unit 600A and the level shifter 600B. Is blocked.

Thirdly, the operation in the third section S3 after the output signal OUT _{N -1} of the previous stage is changed from the high level to the low level will be described.

First, the ninth oxide thin film transistor N9 is turned off by the third clock signal IN3 having a low level, so that the voltage of the fifth node E becomes VDDH.

When the voltage of the fifth node E becomes VDDH, the fourteenth oxide thin film transistor N14 is turned on to raise the voltage of the seventh node G to VDDH. N16) is also turned on so that the output signal OUT _N becomes VDDH.

At this time, since the thirteenth and fifteenth oxide thin film transistors N13 and N15 connected to the ground voltage VSS are reliably turned off by the third clock signal IN3 having a low level VSSL, the ground voltage VSS. No current flows to the) side, so the output signal of VDDH is stably output. The output signal OUT _N maintains VDDH until all of the second, third, and fourth clock signals IN2, IN3, and IN4 become high levels.

In summary, until the output signal OUT _{N -1} of the previous stage is changed from the high level to the low level, the level shifter 600B may have a low level according to the third clock signal IN3 having a high level. The output signal of VSS is output to the buffer unit 600C, and accordingly, the output signal OUT _N of the low level VSS is output from the buffer unit 600C.

After the output signal OUT _{N -1} of the previous stage is changed to the low level, the level shifter 600B receives the output signal of the high level VDDH according to the third clock signal IN3 of the low level. The output signal OUT _N of the high level VDDH is output from the buffer unit 600C.

That is, the scan driving circuit 600 according to the present invention may sequentially apply the scan signal to the pixels of each line through the above operation.

In addition, although the conventional scan driver circuit has a problem in that unnecessary power consumption occurs in a standby state, the scan driver circuit 600 according to the present invention has a low level when the output signal OUT _{N -1} of the previous stage is at a low level. The connection between the input unit 600A and the level shifter 600B is interrupted by the second clock signal IN2, thereby reducing power consumption in the standby state.

In addition, the scan driving circuit 600 according to the present invention is composed of only the oxide thin film transistors (N1 ~ N16) and can be embedded in the display panel, thereby miniaturizing the display driving device and reducing the manufacturing cost, The connected buffer unit 600C has an advantage of keeping the output signal stable.

FIG. 7 illustrates that the scan driving circuit illustrated in FIG. 6A is connected to each line of the display panel.

Referring to FIG. 7, each scan driving circuit 600 receives an output signal of a previous stage and sequentially applies a scan signal to the pixels of each line by four clock signals IN1 to IN4. It can be seen that it has a simple wiring structure as compared with (see FIG. 5A).

The preferred embodiments of the present invention have been described above. It is to be understood, however, that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and alternative arrangements included within the spirit and scope of the appended claims. Of course.

Claims (10)

A pull-down part including a plurality of N-type oxide thin film transistors which pull down an output signal to a ground voltage according to a non-inverting input signal; And
A pull-up part including a plurality of N-type oxide thin film transistors configured to pull up the output signal to a power supply voltage according to an inverting input signal,
And a plurality of N-type oxide thin film transistors constituting the pull-up unit are connected in a latch structure to pull up the output signal to the power supply voltage.
The method of claim 1, wherein the pull-down unit,
A first and second oxide thin film transistors configured to pull down voltages of the first and second nodes to ground voltages according to the first and second non-inverting input signals input to the gate;
And an output signal pulled down to the ground voltage from the first node is output.
The method of claim 2, wherein the pull-down portion,
And a third and fourth oxide thin film transistor configured to pull down the voltages of the third and fourth nodes to the ground voltage according to the first and second non-inverting input signals input to the gate.
The method of claim 3,
The first non-inverting input signal has a phase opposite to that of the inverting input signal,
And the second non-inverting input signal is changed from a high level to a low level after the inverting input signal is changed from a low level to a high level.
The method of claim 3, wherein the pull-up unit,
A fifth oxide thin film transistor having an inverting input signal input to the gate;
A sixth oxide thin film transistor connected to a source of the fifth oxide thin film transistor to pull up a voltage of the second node to a power supply voltage according to the inversion input signal;
A seventh oxide thin film transistor connected to the sixth oxide thin film transistor in a latch structure to pull up the voltage of the first node to a power supply voltage according to the voltage of the second node;
And an output signal pulled up from the first node to a power supply voltage is output.
The method of claim 5, wherein the pull-up unit,
An eighth oxide thin film transistor having a gate connected to a source of the sixth oxide thin film transistor to increase a current driving capability of the sixth oxide thin film transistor;
And a ninth oxide thin film transistor having a gate connected to a source of the seventh oxide thin film transistor to increase a current driving capability of the seventh oxide thin film transistor.
The method according to claim 6,
And a source of the eighth oxide thin film transistor is connected to a gate of the seventh oxide thin film transistor, and a source of the ninth oxide thin film transistor is connected to a gate of the sixth oxide thin film transistor.
8. The method of claim 7,
When the first and second non-inverting input signals are high level and the inverting input signal is low level,
The first to fourth oxide thin film transistors included in the pull-down part are turned on by the first and second non-inverting input signals, and the output signal is pulled down to the ground voltage, and the pull-up part is turned on by the inverting input signal. And the fifth to ninth oxide thin film transistors are all turned off so that no current flows from the power supply voltage toward the first to fourth nodes.
The method of claim 8,
When the first and second non-inverting input signals are at a low level and the inverting input signals are at a high level,
All of the first to fourth oxide thin film transistors included in the pull-down part are turned off by the first and second non-inverting input signals so that no current flows from the first to fourth nodes toward the ground voltage, and the inverting input is performed. And the fifth to ninth oxide thin film transistors included in the pull-up part are turned on by the signal, so that the output signal is pulled up to a power supply voltage.
The method of claim 9,
And the low level (VSSL) of the first and second non-inverting input signals and the inverting input signal is lower than the low level (VSS) of the output signal.

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