KR100378556B1 - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

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Publication number
KR100378556B1
KR100378556B1 KR19990015047A KR19990015047A KR100378556B1 KR 100378556 B1 KR100378556 B1 KR 100378556B1 KR 19990015047 A KR19990015047 A KR 19990015047A KR 19990015047 A KR19990015047 A KR 19990015047A KR 100378556 B1 KR100378556 B1 KR 100378556B1
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South Korea
Prior art keywords
signal
display
liquid crystal
crystal display
block
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KR19990015047A
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Korean (ko)
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KR20000028564A (en
Inventor
장홍용
미와히로까즈
오우라미찌야
무라까미히로시
다까하라가즈히로
Original Assignee
후지쯔 디스플레이 테크놀로지스 코포레이션
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Priority to JP98-306151 priority Critical
Priority to JP98-305890 priority
Priority to JP10305890A priority patent/JP2000131670A/en
Priority to JP30615198A priority patent/JP4357613B2/en
Priority to JP01343199A priority patent/JP4557325B2/en
Priority to JP99-13431 priority
Application filed by 후지쯔 디스플레이 테크놀로지스 코포레이션 filed Critical 후지쯔 디스플레이 테크놀로지스 코포레이션
Publication of KR20000028564A publication Critical patent/KR20000028564A/en
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Publication of KR100378556B1 publication Critical patent/KR100378556B1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3685Details of drivers for data electrodes
    • G09G3/3688Details of drivers for data electrodes suitable for active matrices only

Abstract

The liquid crystal display device includes one of a display unit divided into blocks, a gate driver driving one scan line disposed in the display unit one by one, and one scan line driven by the gate driver positioned in one of blocks sequentially selected according to a block control signal. And a data driver for supplying a display signal to the pixel through a common signal line.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

The present invention relates to a liquid crystal display device composed of a liquid crystal display device and in particular a drive circuit formed on a glass substrate.

The liquid crystal display is compact in comparison with a display device having a cathode-ray tube (CRT), has a light weight and low power consumption, and is widely used as a display device such as a portable computer. In general, a liquid crystal display device has a structure in which two transparent substrates sandwich a liquid crystal. In the opposite electrode, the color filter and the alignment film are provided on one of two opposite surfaces of each transparent substrate, and the thin film transistors (TFTs), the pixel electrode and the alignment film are provided on the other opposite surface. Polar plates are each provided on the side of the transparent substrate opposite to each opposite side. The two polar plates are arranged such that their opposite axes are orthogonal to each other. In this arrangement, light can pass through the polarizing plate without an applied electric field and is shielded by an applied electric field. This is called the always-white mode. The always-black mode is taken when the polar axes of the two polar plates are parallel to each other. Thereafter, the transparent substrate having a TFT and the pixel electrode formed thereon are called a TFT substrate, and the other transparent substrate having the opposite electrode formed thereon is called an opposing substrate.

In recent years, polysilicon TFTs have been interesting because the liquid crystal display portion and the peripheral circuit portion can be formed integrally. The electromagnetic field effect mobility of the polysilicon TFT is approximately tens of cm 2 / Vs to 200 cm 2 / Vs so that it is 1/10 to 1/4 of the single crystal silicon MOSFET. Therefore, it is difficult to form high-speed circuits that operate at tens of MHz using polysilicon TFTs in liquid crystal displays. Moreover, it is also difficult to construct complicated circuits in liquid crystal display devices using polysilicon TFTs because of the limitations in the relatively large design scheme (generally 3-5 μm) applied to the glass substrates used in the liquid crystal display devices.

For this reason, the conventional liquid crystal display device using the polysilicon TFT uses a divided dot-sequential driving method for displaying an image on the display portion. The control circuit is provided outside the display section and used to divide the display data from the data driver into several parts to reduce the frequency of the display data. This is because a data driver composed of polysilicon TFTs does not operate at tens of MHz. The display data is written to the data signal line to which the analog switch is connected and then supplied to the on-line polysilicon TFT through the on-state analog switch. Therefore, the liquid crystal layer on the pixel electrode is operated to display an image.

In addition, the conventional liquid crystal display device has another disadvantage that an analog switch having a relatively wide channel width is required to complete writing data into pixels in a short time. Therefore, it is necessary to provide a large area on the glass substrate to form an analog switch.

Moreover, the conventional liquid crystal display reduces the frequency of the display signal by dividing the display data into a plurality of parts using an externally provided control circuit. Therefore, it is necessary to divide the R, G and B signals, which are one channel signal, into a plurality of channels based on the number of divisions. For example, if the display data is divided into 16 portions, each R, G, B is divided into 16 portions, so that the display data is divided into a total of 48 channels. In addition, a liquid crystal display device using a polysilicon transistor should have a function of converting a display signal in digital form into an analog signal that substantially drives the liquid crystal display, and also needs to have a specific IC chip for controlling the polysilicon TFT. This raises the price. Moreover, control circuits provided outside the display consume a certain amount of power and are not suitable for digitized interfaces.

The polysilicon TFT may be formed by a low temperature process (process temperature of 600 ° C. or less). When the polysilicon TFT thus produced is applied to the liquid crystal display device, display failure may occur. Examples of display failures include scan lines, warp streaking, ghost marks, and inequality between horizontal marks and vertical marks. Display failures result from cyclic performance fluctuations of polysilicon TFTs at low temperatures, performance deviations of analog switch TFTs, and delays in signal time due to buffer circuits and shift circuits, which are circuits forming data drivers.

The periodic performance variation of the low temperature polysilicon TFT is due to the instability coefficient of the aximmer laser oscillator. The energy error ΔE (= Emax-Emin), where Emax represents the maximum energy value of the axamer layer and Emin represents the minimum energy value of the axamer laser, is always present between the pulses of the aximmer laser, and the frequency of the laser pulse. Is in the range of 50 to 300 Hz, the energy error is at least 10% of Emax. On the other hand, the projection energy within the range in which the crystallization of the polysilicon TFT is guaranteed is approximately equal to ± 3-5% of the maximum projection energy Eop. As described above, the maximum and minimum energy values Emax and Emin of the aximmer laser are located outside the projection energy range of the laser pulse within the range in which the crystallization of the polysilicon TFT is guaranteed. Therefore, the polysilicon TFT at low temperature has a dispersibility of performance.

The crystallization of the low temperature polysilicon TFT also has dispersibility. This is because the crystallization state of the polysilicon varies at the interface portions where the laser beams overlap each other when scanning the glass substrate. Therefore, the performance of the polysilicon TFT such as the field effect mobility or the threshold voltage is varied.

The delay of the signal due to the shift register of the driving circuit is caused by the arrangement of the data driver operating at high frequency in the divided point sequential driving method and the arrangement in which the shift register has many steps.

It is a general object of the present invention to provide a liquid crystal display device in which the above disadvantages are eliminated.

A more specific object of the present invention is to provide a liquid crystal display device of improved display quality.

The above object of the present invention is to provide a liquid crystal display device comprising: a display unit divided into blocks; a gate driver for driving one scanning line arranged in the display unit one by one; A data driver is provided in one of blocks sequentially selected according to the block control signal and supplies a display signal through a common signal line to a pixel connected to one of the scan lines driven by the gate driver.

1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a plan view of a liquid crystal display panel used in the panel shown in FIG. 1. FIG.

3 is an operation timing chart of the liquid crystal display shown in FIG. 1;

FIG. 4 is an equivalent circuit diagram of the liquid crystal display shown in FIG. 1.

FIG. 5 is a diagram showing a liquid crystal display device based on the structure shown in FIG. 1 according to the first embodiment of the present invention; FIG.

6 is an operation timing chart of the liquid crystal display shown in FIG. 5;

7 is a circuit diagram of a gate driver used in the structure shown in FIG.

8 is a circuit diagram of a shift register circuit and a buffer circuit used in the structure shown in FIG.

9 is a circuit diagram of a D flip-flop.

10 is a circuit diagram of an inverter in a buffer circuit.

FIG. 11 is a plan view of the liquid crystal display shown in FIG. 5; FIG.

12 is an enlarged view of a TAB-IC device.

13 is a plan view of a mounting arrangement of a liquid crystal display device;

Fig. 14 is another plan view of the mounting arrangement of the liquid crystal display device;

Fig. 15 is still another installation layout plan of the liquid crystal display device.

16 is a block diagram of a liquid crystal display according to a second embodiment of the present invention.

Fig. 17 is a circuit diagram of an analog switch and a cell used in the second embodiment of the present invention.

18 is an enlarged layout plan view of an analog switch.

Fig. 19 is a connection diagram made between the display unit and the analog switch located in the left half of the common signal line.

20 is a connection diagram made between the display unit and the analog switch located on the right half of the common signal line.

21 is an operation timing chart of the liquid crystal display shown in FIG. 16;

22 is an installation layout plan view of an apparatus according to a second embodiment of the present invention.

FIG. 23 is a sectional view of the structure shown in FIG. 22; FIG.

24 is another installation arrangement plan view of the apparatus according to the second embodiment of the present invention.

25 is yet another installation layout plan of the apparatus according to the second embodiment of the present invention.

FIG. 26 is a schematic diagram showing a wiring pattern of a block control line formed on the panel shown in FIG. 1; FIG.

27 is a diagram showing a resistance value of a block control line of a conventional liquid crystal display device.

Fig. 28 is a plan view of an arrangement pattern of block control lines used in the third embodiment of the present invention.

Fig. 29 shows the resistance value of the block control line used in the third embodiment of the present invention.

30 is a schematic diagram of wiring patterns of block control lines used in the liquid crystal display panel of the liquid crystal display device according to the fourth embodiment of the present invention.

Fig. 31 is a diagram showing a resistance value of a block control line used in the fourth embodiment of the present invention.

32 is a plan view of a connection between an analog switch and a block control line of one block according to variations of the third and fourth embodiments of the present invention;

33 is a schematic cross-sectional view of a block control line structure.

34 is a circuit diagram of a basic structure of a liquid crystal display device.

35 shows waveforms of a display signal and a scan signal;

36 shows another waveform of a display signal and a scanning signal;

Fig. 37 is a correlation diagram between a pixel TFT and a drain current flowing in the gate voltage.

38 is a waveform diagram showing a relationship between an initial potential of a signal line portion and a standing time;

39 illustrates the basic structure of a liquid crystal display according to a fifth embodiment of the present invention.

40 is a circuit diagram of a structure of a liquid crystal display according to a fifth embodiment of the present invention.

Fig. 41 is a circuit diagram of an n-channel MOS reset circuit.

42 is a circuit diagram of a CMOS type reset circuit.

Fig. 43 is a circuit diagram of a driving IC device having a pre-made reset circuit.

44 is a diagram showing the detailed structure of a liquid crystal display according to a fifth embodiment of the present invention.

45 is an operation timing chart of the liquid crystal display shown in FIG. 44;

46 is another operation timing chart of the liquid crystal display shown in FIG. 44;

Fig. 47 is a waveform diagram showing variation in polarity of reset potential.

48 is a waveform diagram showing a polarity variation of a display signal;

Fig. 49 is a waveform diagram showing a polarity variation of a display signal having a reset potential satisfying a given condition.

50A and 50B show polarities of reset potentials in a liquid crystal display device in which field inversion is used, respectively.

Fig. 51 is an operation timing chart of a liquid crystal display using relay inversion.

52A and 52B show polarities of reset potentials in a liquid crystal display device in which H / V line inversion is used, respectively.

53 is an operation timing chart of a liquid crystal display using H / V line inversion.

FIG. 54 is a view showing a point sequential driving type liquid crystal display device according to a fifth embodiment of the present invention. FIG.

Fig. 55 is a diagram showing another dot sequential drive type liquid crystal display device.

Fig. 56 is a view showing the line sequential drive type liquid crystal display device.

Other objects, features and advantages of the present invention will be understood from the following detailed description with reference to the accompanying drawings.

A first embodiment of the present invention will be described below.

1 is a block diagram of a liquid crystal display according to a first embodiment of the present invention. As shown in Fig. 1, the liquid crystal display device 510 includes a line sequential driver IC chip 512, common signal lines D1 to Dn, an analog switch 514 formed of TFTs, block control lines BL1 to BLn, and a gate driver circuit 516. And a liquid crystal display 518. The liquid crystal display 518 is divided into n blocks B1 to Bn, and the scan line 520 and the signal line 522 are arranged in a matrix form on each block. Cell 524 is provided at each intersection where scan line 520 and signal line 522 cross each other. Each cell 524 is composed of a pixel TFT 526, a liquid crystal layer 528, and a storage capacitor 530. The gate electrode of the p-channel pixel TFT 526 is connected to the scan line 520, and its drain electrode is connected to the signal line 522. The source electrode of the TFT 526 is connected to the liquid crystal layer 528 and the storage capacitor 530.

Each block B1 to Bn has n analog switches 514. The common signal lines D1 to Dn are connected to the signal lines 522 of the display unit 518 through the analog switches 514 of blocks B1 to Bn.

The line sequential driver IC chip 512 includes first to fifth portions. The first part receives the serial digital signal from an IC chip (not shown) externally connected to the IC or device 512. The second part converts the serial digital signal into a parallel digital signal. The third part is a D / A converter for converting parallel digital signals into analog signals. The fourth part generates the liquid crystal display signal D (including information on level adjustment, gradation generation and polarity inversion). The fifth part outputs the display signal D.

The IC driver 512 applies the display signal D in the time division form to the common signal lines D1 to Dn in block units. The analog switch 514 is operated in units of blocks by applying the block control signal BL to one of the block control lines BL1 to BLn.

When driving the liquid crystal display 510, the gate scan signal G is applied from the gate driver circuit 516 to the scan line 520. The TFT is turned on because the gate scan signal G is input to the pixel TFT 526. The signal line 522 is supplied with a display signal D which is sent to the common signal lines D1 to Dn through the analog switch 514 turned on by the block control signal BL. The display signal D passes through the conductive pixel TFT 526.

2 is a plan view of the display unit 518. The display unit 518 is an area in which a plurality of pixels for image display are arranged in a matrix form. As shown in FIG. 2, a signal (data bus) line 522, a scan (gate bus) line 520, a pixel electrode 530, and a TFT 526 are provided to the display unit 518. The signal line 522 and the scan line 520 are disposed at right angles to each other and electrically separated from each other through an isolation film formed between each other. The rectangular region defined by one signal line 522 and one scanning line 520 is a pixel region in which one TFT 524 and one pixel electrode 530 are disposed. The TFT 524 is formed of a polysilicon film 525 selectively formed on an insulating film on the scan line 520 and a protrusion (gate) of the scan line 520. In each pixel, the source of the TFT 524 is connected to the pixel electrode 530 through a contact hole (not shown), and the drain of the TFT 524 is connected to the corresponding signal line 522 through the contact hole.

3 is a timing chart of the block control signal BL applied to the display signal D, the gate scan signal G, and the blocks B1 to Bn of the liquid crystal display 510.

As shown in parts a to f of FIG. 3, the gate driver circuit 516 converts the gate scan signal G to a high level and applies the high level gate scan signal G to the display unit 518. The block control signal BL maintained at the high level for one block control period Tb is applied to the analog switch 514. At this time, the display signal D is applied to the block B1 through the common signal lines D1 to Dn during the block control period Tb. It is assumed that the block control period Tb and the time constant Ts of the signal line 522 are larger than Ts.

The block control signal BL, which is high during the period Tb after the display signal D is applied to the block B1, is applied to the analog switch 514 of the block B2. At this time, the display signal D is applied to the block B2 through the common signal lines D1 to Dn for the period Tb. The above operation is repeated so that the display signal D is finally applied to the block Bn. Then, the blanking period Tbk comes. When the block control period Tb elapses after the blanking period Tbk starts, the gate signal G applied to the display unit 518 is switched to the low level. One horizontal scanning period Th ends when the blanking period Tbk ends. Then, the display signal D is applied to blocks B1 to Bn starting from block B1, so that the next scanning operation is performed.

In Fig. 3, Ton and Toff represent the rise and fall times of the gate scan signal G, respectively. The blanking period Tbk is sufficiently longer than the block control period Tb and satisfies the condition Tbk> Tb + Ton + Toff.

The block control signal BL can be applied to the analog switch 514 so that all analog switches 514 of blocks B1 to Bn are turned on simultaneously for the horizontal scanning period Th.

As described above, blocks B1 to Bn are selected sequentially and operated sequentially. The data write time Tb per block in the liquid crystal display 510 implementing the block sequential driving operation is equal to (Th − Tbk) / n. Therefore, the smaller the number n of blocks in the liquid crystal display 510 is, the longer the data writing time Tb can be determined. Since the data write time Tb per block is longer, the data write time Tb is less affected by the change during the rise time Ton and the fall time Toff of the gate scan signal G because of the dispersion of the characteristics of the pixel TFT 526. Therefore, the data writing time Tb can be sufficiently secured for each block, and the occurrence of display failures such as laser scanning lines or distortion lines can be prevented.

The dispersion of the characteristics of the pixel TFT is due to the fact that the maximum and minimum energy of the aximmer laser is located outside the range of the aximmer laser pulse projection energy in which crystallization of the p-channel polysilicon TFT is sealed.

4 illustrates an equivalent circuit 546 of the liquid crystal display 510. According to FIG. 4, the output resistor R IC and the capacitance C IC correspond to the line sequential driver IC chip 512. The resistor R L and the capacitance C L correspond to the common signal lines D1 to Dn. Capacitance C L , n-channel transistor 532 and p-channel transistor 534 correspond to one analog switch 514. Resistor R SL and capacitance C SL correspond to one signal line 522. The n-channel transistor 536 corresponds to one pixel TFT 526 and the capacitance C LC corresponds to the liquid crystal layer 528. Capacitance C S corresponds to accumulation capacitance 530.

FIG. 5 shows a liquid crystal display 540 based on the structure shown in FIG. 1 according to the first embodiment of the present invention. The device 540 shown in FIG. 1 is an SXGA liquid crystal display device integrated into a peripheral circuit and using a low temperature polysilicon TFT. In FIG. 5, the same parts as those shown in FIG. 1 are given the same reference numerals.

The liquid crystal display device 540 includes a line sequential driver IC chip 512, common signal lines D1 to D384, a CMOS type TFT analog switch 514, block control lines BL1 to BL10, a gate driver circuit 516, a display portion 518, The shift register circuit 542 and the buffer circuit 544 are included. The shift register circuit 542 and the buffer circuit 544 form a circuit for generating the block signal BL. The start pulse SP and the clock signals CL and / CL are supplied to the shift register circuit 542. The operating frequency of the shift register circuit 542 is, for example, 0.5 MHz.

The display unit 518 is divided into ten blocks B1 to B10, and each block has 1204 scanning lines 520 and 3840 signal lines (= 1280 x RGB) 522. Each cell 524 is composed of a pixel TFT 526, a liquid crystal layer 528, and a storage capacitor 530. The gate of the pixel TFT 526 formed of the p-channel polysilicon TFT is connected with the corresponding scan line 520 and its drain is connected with the signal line 522. The source of the pixel TFT 526 is connected to the liquid crystal layer 528 and the storage capacitor 530.

Each block B1 through B10 has 384 analog switches 514. The common signal lines D1 to D384 can be connected to the signal line 522 through the analog switch 514 provided at each block B1 to B10.

The line sequential driver IC chip 512 includes the first to fifth portions. In addition, the line sequential driver IC chip 512 has an input port having a function of selecting a 6 bit input or an 8 bit input and an output port having 384 output terminals having a buffer amplifying buffer. Therefore, the device 512 has the capability to handle a block width of up to 384 bits. In addition, the device 512 is designed such that the maximum output resistance is approximately 5 kΩ or less to enable driving of a display block having a wide data named operationally long common signal line. Therefore, the device 512 can improve the time constant Ts of the signal line 522 disposed on the display unit 518.

The line sequential driver IC chip 512 applies the display signal D generated therein to the analog switch 514 via the common signal lines D1 to D384. Shift register 542 has ten stages. The combination of the shift register 542 and the buffer circuit 544 generates the block control signal BL, which is transmitted to the block control lines BL1 to BL10 to turn on the analog switch 514.

When the liquid crystal display 540 is driven, the gate scan signal G is applied from the gate driver circuit 516 to the scan line 520. The gate scan signal G is applied to the gate of the pixel TFT 526. The display signal D transmitted to the common signal lines D1 to D384 is applied to the signal line 522 through the analog switch 514 turned on by the block control signal BL. The display signal D is then applied to the pixel TFT 526 to form an image.

Each analog switch 514 may be formed only of n channel transistors or p channel transistors. The pixel TFT 526 can be formed only of n-channel transistors or p-channel transistors.

6 is a timing chart of the display signal D, the gate scan signal G, and the block control signal BL applied to the blocks B1 to B10. According to FIG. 6, the high level gate scan signal G is applied from the gate driver circuit 516 to the display portion 518. Then, the block control signal BL, which is maintained at the high level only for the period Tb (2.0 ms), is applied to the analog switch 514 of the block B1. Then, the analog switch 514 is turned on. At this time, the display signal D is applied to the block B1 through the common signal lines D1 to D384 only for the period Tb so that data is written into the corresponding cell 520.

Then the high level block signal BL, which is high level only for the period Tb, is applied to the analog switch 514 of block B2. Therefore, analog switch 514 of block B2 is turned on. At this time, the display signal D is applied to the block B2 through the common signal lines D1 to D384 only for the period Tb and written to the corresponding cell 520.

The above operation is performed repeatedly so that the display signal D is applied to the block B10 and written to the corresponding cell 520. Then comes the blanking period Tbk, for example 5.0 ms.

When the period Tb elapses after the blanking period Tbk starts, the gate scan signal G is switched to the low level. One horizontal scanning period Th ends when the blanking period Tbk ends. The length of one horizontal scanning period Th is, for example, 25 ms (= 2.0 ms x 10 blocks + 5.0 ms). The display signal D is then applied to blocks B1 to B10 starting from block B1 while the next scan line is driven. In FIG. 6, Ton and Toff represent the rise and fall times of the gate scan signal G, respectively.

As described above, the liquid crystal display 540 is operated in a block sequential driving manner. The display portion 18 is divided into ten blocks and the data write time Tb per block can be set longer than that in the divided point sequential driving scheme. Therefore, the data write time Tb is less affected by the variation during the rise time Ton and the fall time Toff of the gate scan signal G because of the dispersion of the characteristics of the pixel TFT 526. Therefore, the data writing time Tb can be sufficiently secured for each block, and the occurrence of display failures such as laser scanning lines or distortion lines can be prevented.

Furthermore, since the data write time Tb per block can be set longer than that in the divided point sequential driving scheme, the frequencies of the display signal D and the block control signal BL can be drastically reduced. Therefore, the performance of the pixel TFT 526 need not be as high as that of the conventional device. As a result, the production amount and production margin of the liquid crystal display 540 can be significantly improved.

The shift register 542 has ten stages that are not as many as the stages of the shift register circuit used in the liquid crystal display of the divided point sequential driving method. And the operating frequency of the shift register circuit 42 is lower than that of the conventional apparatus. Therefore, it is possible to prevent the occurrence of display failure due to the propagation delay of the signal.

Furthermore, the liquid crystal display 540 includes a line sequential driver IC chip 512 that converts the digital signal into a corresponding analog signal and transfers the resulting display signal D in a time division format to the block. Therefore, there is no need to provide an IC chip and related external control circuits specifically designed for controlling conventional liquid crystal display devices using polysilicon TFTs. Therefore, the production cost of the liquid crystal display 540 can be reduced and power consumption can be reduced.

If the linear sequential driver IC chip 512 is a standardized driver IC chip capable of processing both a polysilicon panel and an amorphous silicon panel, it is possible to further reduce the production cost, precision and performance of the liquid crystal display.

As a result of analyzing the time constant portion of the corresponding circuit 546 shown in FIG. 4, the inventors make the block control period Tb larger than the time constant Ts (CSL x RSL) of the signal line 522 in the display portion 518. It has been found that without it is impossible to reduce the performance difference between individual pixel TFTs that occur during the crystallization process using a laser. In addition, it is generally required that the number of bits processed in one block be greater than the number of blocks. Moreover, it is required that the number of bits in one block be larger than the root of the horizontal pixels of the display portion 518. When the above requirement is applied to an SXGA panel, the number of bits in one block is greater than 3840 1/2 (about 62). The block control period Tb can be obtained from the following condition. The minimum block control period Tmin is 1/62 of approximately 25 ms of horizontal period, that is, about 0.4 ms. Therefore, in the liquid crystal display device 540, the block control period Tb is set to 2 ms, and the display portion 518 is divided into 10 blocks (384 bits per block). The block control period (data writing period) Tb 2 ms is 12.5 times the data writing period Tb (about 160 ms) of the known 16-split point sequential driver system.

In order to implement data writing to the last block B10 in the same manner as writing data to another block, the blanking period Tbk needs to be at least longer than the block control period Tb. It is recommended to satisfy the condition Tbk> Tb + Ton + Toff. With this in mind, the blanking period Tbk is set to 5 ms in the present invention.

The number of blocks and the block control period Tb can be chosen randomly as long as the concept of the present invention is satisfied. For example, the horizontal scanning period Th may be set to 25 Hz, but may vary in consideration of the frame frequency. For example, when the frame frequency is 60 Hz, the horizontal scanning period Th is approximately 16 Hz. As described above, the maximum number of blocks and the maximum block period can be selected in consideration of the performance of the TFT.

Table 1 shows an example of the number of blocks and the block width according to various display formats.

Display format The number of pixels in the horizontal direction The number of pixels in the vertical direction Horizontal / vertical ratio Horizontal Period Th Block width (bits) Number of blocks VGA 1800 (600xRGB) 480 5: 4 ~ 35 yen 300600 63 SVGA 2400 (800xRGB) 600 4: 3 ~ 28 yen 200300400600 12864 XGA 3072 (1024xRGB) 768 4: 3 To 22 yen 256512 126 SXGA 3840 (1280 x RGB) 1024 5: 4 ~ 16 yen 384768 105 UXGA 4800 (1600xRGB) 1200 4: 3 ~ 14 yen 200300400600 2416128 QXGA 6144 (2048 x RGB) 1536 4: 3 To 11 yen 2565121024 24126 HD1 3840 (1280 x RGB) 720 16: 9 ~ 23 yen 384768 105 HD2 5760 (1920 x RGB) 1080 16: 9 ~ 15 yen 240384480960 2415126 The values are calculated under the conditions of 30 frames / second and 60 fields / second.

As shown in Table 1, the number of pixels in the horizontal direction in each display format is a regular multiple of each block (bit) width, which is 200, 240, 256, 300 or 384 bits. The number of blocks in each display format set to an even number to extend the block width is desirable. Furthermore, since the number of blocks is selected in each display format, it is preferable that the block write time is longer than 1 ms to ensure the block write time.

7 is a circuit diagram of the gate driver circuit 516 used in the liquid crystal display 540.

As shown in FIG. 7, the gate driver circuit 516 includes a bidirectional switch unit 550, a shift register unit 552, a multiplexer unit 554, and an output buffer unit 556.

The bidirectional switch unit 550 includes transistors 558, 560, 562, 564. The shift register unit 552 includes transistors 566, 568, 570, 572, 574, 578, 580, inverters 582, 583, and a NAND circuit 584. The multiplexer portion 554 includes a 4-bit multiplexer formed of four NAND circuits 586, 588, 590, 592. One end of the NAND circuits 586, 588, 590, 592 is connected to the NAND circuit through an inverter 583. The output buffer unit 556 includes inverters 594, 596, 598, 100, 102, 104, 106, 108, 110, 112, 114, and 116. Inverters 594, 100, 106, and 112 are connected to NAND circuits 586, 588, 590, 592 of the multiplexer unit 554. Inverters 598, 104, 110, and 116 are connected to the display unit 518.

The gate driver circuit 516 uses a 4-bit multiplexer portion 554. Therefore, the number of shift registers (256) may be one quarter of those used in the prior art (1024). Therefore, yield and power consumption can be improved.

8 is a circuit diagram of the buffer circuit 544 used in the shift register section 542 and the liquid crystal display device 540. As shown in Fig. 8, the shift register section 542 is composed of ten D-type flip-flops (D-FF) 120, 121, ..., 129, and the buffer circuit 544 has an inverter 130, 131, ... , 153). The flip-flop 120 and the buffers 130, 131,..., 135 form a circuit for generating a block control signal BL associated with the block B1 of the display unit 518. Flip-flops 120, 121, ..., 129 have the same structure.

FIG. 9 is a circuit diagram of the D flip-flop 120 shown in FIG. 8. 10 is a circuit diagram of inverters 130, 131,..., 135 of buffer circuit 544 associated with block B1.

As shown in FIG. 9, the flip-flop 120 includes transistors 154, 155,..., 163. As shown in FIG. 10, inverters 130, 131, ..., 135 are composed of transistor pairs 170, 171, 172, 173, ..., 180, 181. The start pulse SP is applied to the gates of transistors 155 and 156 of flip-flop 120 as shown in FIG. The output signal of the flip-flop 120 is applied to the gates of the transistors 170 and 171 forming the buffer circuit 544. The block control signal BL includes a complementary signal which is output through the N output terminal 183 and the P output terminal 182 of the buffer circuit 544 as shown in FIG. 10, and also includes the block B1 of the display unit 518. Is applied to the analog switch 514.

11 is a plan view of the liquid crystal display 540. As shown in FIG. 11, the liquid crystal display 540 includes a printed circuit board 200, a common board 202, a connector 204, a TAB-IC device 206, a control circuit 208, and a data driver 210. Two 256-bit gate drivers 212 and a display region 214. Gate driver 212 is disposed opposite device 540.

The TAB-IC device 206 is an IC chip having the function of the line sequential driver IC 512 as shown in FIG. The data driver 210 includes a shift register circuit 542, a buffer circuit 544, and an analog switch 514. The gate driver 212 and the display area 214 correspond to the gate driver circuit 516 and the display unit 518, respectively.

The control circuit 208 is formed on the printed circuit board 200. The control circuit 208 includes a gate array, a line memory, a timing circuit and controls portions of the liquid crystal display 540. The printed circuit board 200 is flush with the display area 214. Therefore, the liquid crystal display 540 can be made thin.

12 is an enlarged view of the TAB-IC device 206. As shown in FIG. 12, the TAB-IC device 206 includes an input terminal portion 216, an output terminal portion 218, a driver IC chip 220, and a through terminal portion 222. The through terminal portion 222 is directly connected to the gate driver 222 and other related portions in FIG. 11.

The driver IC chip 220 is installed on the TAB-IC device 206 but can be installed in a chip on glass (COG) mounting format or TCP, so that the chip 220 is directly installed on the common substrate 202. To simplify the terminal crimping step, the TAB-IC device 206 has a through line in addition to common signal lines such as control lines and clock signal lines on its gate side and data side. The through line is connected to the printed circuit board 200. Therefore, it is not necessary to provide a component such as a flexible printed circuit board to the liquid crystal display 540 in order to separately provide lines corresponding to the common line.

The digital signal applied to the line sequential driver IC device 512 has an analog signal output by the device 512 having an input amplitude of 2.5V to 3.8V and an output amplitude of 7.5V to 16V. Because the device 512 has a large dynamic range of analog output signals, the device 512 can be applied not only to TN-type liquid crystals but also to low-voltage liquid crystals, vertically aligned liquid crystals, or IPS (in-plane switching) panel liquid crystals.

13, 14, and 15 show another installation arrangement of the liquid crystal display 540 as the components shown in FIG. 11 given the same reference numerals.

The liquid crystal display 540 of FIG. 13 uses a facing driving type system in which the data driver 220 is divided into two parts, an upper part and a lower part. Therefore, the upper area on the TFT substrate 396 for accommodating the peripheral circuit can be reduced. The printed circuit board 200 is located on the left side of the apparatus in FIG.

14 and 15 show an arrangement in which two TAB-IC devices 206 are used, respectively. This arrangement is effective for a liquid crystal display device of a relatively small size. By using two TAB-IC devices 206, each device 206 does not require as high performance as needed when only one device 206 is used. Furthermore, the load on the common signal line can be reduced. In particular, it is useful to use two or more line sequential driver IC devices 412 to form large high precision panels such as USGA panels with 1600 x 1200 pixels and QXGA with 2048 x 1536 pixels. Therefore, the number of bits in each block can be increased to extend the data write time, and the time constant of the common signal line can be reduced. In addition, reduction of the panel can be realized.

Table 2 shows the data applied to the data driver 210 in the arrangement in FIGS. 13, 26, 27.

Top (left) data driver Bottom (Right) Data Driver A Odd line data Even Line Data B Odd Pixel RGB Data Even Pixel RGB Data C Data across blocks The data at the end of the block D Random group 1 Random group 2

Each line sequential driver IC device 512 can use an arrangement in which each group is connected to a common signal line. In other words, the upper (left) common signal line need not be connected to the lower (right) common signal line. Analog switches formed from p-channel polysilicon TFTs can be replaced by electronic circuits with switching functions such as operational amplifiers.

By the way, if the liquid crystal display device using the low temperature p-channel polysilicon TFT can be modified to reduce the panel size by narrowing the pixel pitch, the liquid crystal display device can be produced with low production cost and high productivity. . However, low temperature p-channel polysilicon TFTs have a large design rule. This hinders the reduction of the pixel pitch. In addition, if the pixel pitch becomes narrow, it may be difficult to arrange the peripheral circuit in the peripheral region on the substrate.

With the above in mind, the liquid crystal display device 340 described below uses a 2-bit analog switch 314 each having a single common input terminal and operates in a block sequential driving format. This structure can narrow the pixel pitch.

16 is a block diagram of the liquid crystal display 340 according to the second embodiment of the present invention. In particular, the device shown in FIG. 16 is a 1.8 inch reflective projection liquid crystal device integrated with a peripheral circuit.

As shown in FIG. 16, the liquid crystal display 340 includes a line sequential driver IC device 312, an analog switch 314, gate drivers 316 and 317, a display unit 318, a common electrode 336 and 338, and an antistatic unit 342. ).

The gate driver 316 located on the left side includes a level shifter 320, a 256 bit shift register 324, a 4 bit multiplexer 328, and a buffer 332. The gate driver 317 located on the right side includes a level shifter 322, a 256 bit shift register 326, a 4 bit multiplexer 330, and a buffer 334.

The display unit 318 has 1024 scan lines and 1280 signal lines. The display portion 318 is divided into four blocks B1 to B4.

The apparatus of FIG. 16 has 1280 analog switches 314, each of which is an n-channel MOS TFT. The 1280 analog switches 314 are arranged in four groups with 320 analog switches 314 each. The four groups of analog switches 314 correspond to blocks B1 through B4, respectively.

320 analog switches 314 corresponding to the block B1 are connected to odd-numbered signal lines of the signal lines # 1 to # 640 disposed in the left half region of the display portion 318, respectively. 320 analog switches 314 corresponding to block B2 are connected to odd-numbered signal lines of signal lines # 641 to # 1280, which are disposed in the right half region of the display portion 318, respectively. 320 analog switches 314 corresponding to block B3 are connected to the even-numbered signal lines of signal lines # 1 to # 6400, respectively. 320 analog switches 314 corresponding to block B4 are connected to the even-numbered signal lines of the signal lines # 641 to # 1280, respectively. The block control lines BL1 to BL4 are connected to the analog switch 314.

The analog switch 314 is controlled by the block control signal BL transferred from the externally provided block control signal generation circuit (not shown) to the block control lines BL1 to BL4. Each analog switch 314 may be a p-channel MOS TFT. The block signal generation circuit may include a four-stage shift register circuit and a buffer circuit that may be provided in the liquid crystal display 340.

The line sequential driver IC device 312 having a 320-bit structure is connected to the common signal lines D1 to D320 through a signal line disposed at an end of the device 340 and extending vertically from the common signal line. The line sequential driver IC device 312 has an output resistance RIC of 10 kΩ or less in order to reduce the rise and fall times of the display signal D when writing data. The common signal lines D1 to D320 are connected to the analog switch 314.

17 is a circuit diagram of one cell 310 and an analog switch 314 provided in the display unit 318. An analog switch 314 consisting of transistor 302 and sampling capacitance 304 is connected to signal line # 1 301 associated with block B1. The cell 310 and the antistatic part 342 are connected to the signal line 301. The gate of the transistor 302 is supplied with the block control signal BL transmitted to the block control line BL1. The display signal D transmitted to the common signal line D1 when the transistor 302 is turned on is applied to the cell 310 through the transistor 302. The cell 310 includes a double gate TFT 306 formed of a low temperature p-channel TFT, a liquid crystal layer 308 and an accumulation capacitance 309. When the gate scan signal G is applied from the scan line 303 to two gate terminals of the gate TFT 306, the TFT 306 is turned on and the display signal D is applied from the signal line 301 to the cell 310. .

18 shows an arrangement of analog switches 314 using the 4 μm design rule. As shown in FIG. 18, two adjacent analog switches 314 are paired. The input terminals of the two analog switches 314 are connected to a single common signal line. The output terminals of the two analog switches 314 are connected to corresponding odd and even signal lines, respectively. Two analog switches 314 are connected to the block control lines BL1 and BL3 or BL2 and BL4. One of the two analog switches 314 connected with odd or even signal lines is selected by two block control lines. The display data D is then applied to the display portion 318 via the selected analog switch 314.

As described above, two analog switches 314 are paired in pairs, each sharing one display signal input terminal, and each having an output terminal connected to the signal line of the display portion 318. Therefore, the two analog switches 314 can be arranged at a narrow pitch of 28 mu m. Furthermore, since the number of input signal lines connected to the two analog switches 314 can be halved, the input signal lines arranged at different layer levels cross each other at a reduced number of intersections. Therefore, the signal delay caused by parasitic capacitance of the analog switch 314 can be reduced and productivity can be improved.

19 shows a connection between the analog switch 314 and the common signal line 320, which is disposed on the left half of the display unit 318 and is 640 bits. 20 shows a connection between the analog switch 314 and the common signal line 320, which is disposed on the right half of the display unit 318 and is 640 bits. 21 is a timing chart of the block control signals BL applied to the display signals D, the gate scan signals G1 and G2, and the blocks B1 to B4 applied to the liquid crystal display 340. FIG.

As shown in portions (a) to (g) of FIG. 21, the high level gate scan signal G1 is applied from the gate driver circuit 316 to the first gate of the display portion 318. Then the block control signal BL, which remains at the high level only for a period Tb (e.g. 2.5 ms), is applied to the analog switch 314 of the block B1 with the switches on. Then the display signal D transmitted to the common signal lines D1 to D320 only for the period Tb is connected to the odd signal line associated with the block B1 of the signal lines # 1 to # 640 disposed on the left half of the display portion 318 through the analog switch 314. Is applied to the cell 310.

Then the block control signal BL, which remains at the high level only for the period Tb, is applied to the analog switch 314 of block B2 so that the switches are turned on. Then, the display signal D transmitted to the common signal lines D1 to D320 only for the period Tb is connected to the odd signal line associated with the block B1 of the signal lines # 641 to # 1280 disposed on the right half of the display portion 318 via the analog switch 314. It is applied to the cell 310 to be connected.

Then the block control signal BL, which remains at the high level only for the period Tb, is applied to the analog switch 314 of block B3 so that the switches are turned on. Then the display signal D transmitted to the common signal lines D1 to D320 only for the period Tb is connected to the even signal line associated with the block B1 of the signal lines # 1 to # 640 disposed on the left half of the display portion 318 through the analog switch 314. Is applied to the cell 310.

Then the block control signal BL, which remains at the high level only for the period Tb, is applied to the analog switch 314 of block B4 so that the switches are turned on. Then, the display signal D transmitted to the common signal lines D1 to D320 only for the period Tb is connected to the even signal line associated with the block B1 of the signal lines # 641 to # 1280 disposed on the right half of the display portion 318 through the analog switch 314. Is applied to the cell 310.

In this method, data is written into the cells of blocks B1 to B4.

Operation then enters the blanking period Tbk, which can be 6.0 ms. After the blanking period Tbk starts, when the time is equal to or longer than 2.5 ms, the gate scan signal G is switched to the low level. When the blanking period Tbk ends, the horizontal scanning period Th ends. The length of the horizontal scanning period Th is 16 ms, for example.

The high level gate scan signal G2 is then applied from the gate driver circuit 316 to the second gate of the display portion 318 and the display signal D is applied in the same manner as described above. The rise and fall times Ton and Toff of the gate scan signal are shorter than 1.5 ms.

In the general line sequential driving method, the number of all bits of the driver IC device is equal to the number of pixels arranged in the horizontal direction. Therefore, the output terminals of the driver IC device are arranged at the same pitch as that of the pixels arranged in the horizontal direction. It is very difficult to realize a narrow pixel pitch equal to 20 to 30 mu m because of the pitch phase limitation in the arrangement of the output terminals of the driver IC device.

In contrast, in the liquid crystal display device 340, a single number of line sequential drive IC devices 312 selects a combination of the common signal line and the block control lines BL1 to BL4 in a time division manner, and applies the display signal D to the display unit 318. Is configured to. Therefore, the space for installing the IC driver 312 can be reduced to the reciprocal of the number of blocks. Therefore, the pixel pitch of the display unit 318 can be reduced. Furthermore, as shown in FIGS. 16 and 17, the data driver circuit can be simplified, so that the liquid crystal display 340 can be produced with low reliability and improved reliability.

The block control period Tb is not limited to the above-mentioned length and can be selected as long as the concept of the present invention is satisfied.

22 and 23 are plan and cross-sectional views of the substantial structure of the liquid crystal display 340, respectively. As shown in FIG. 22, the liquid crystal display 340 includes level shifters 320 and 22, gate drivers 316 and 317, common electrodes 336 and 338, antistatic parts 342, TAB-IC device 370, and connectors ( 372, a printed circuit board 374, a sealing part 376, a common substrate 378, and a display area 380. As shown in FIG. 23, the cross-section of the liquid crystal display 340 includes a display area 380, a terminal 388, an opposing light shield 382, an indium tin oxide (ITO) film 384, and a reflective electrode 386. And a terminal 388, a peripheral circuit portion 390, a TFT side light blocking film 392, a short circuit ring 394 and a TFT substrate 396.

The TAB-IC device 370 is an IC chip corresponding to the line sequential driver IC device in FIG. The display area 380 corresponds to the display unit 318 in FIG. 16. All lead lines extending from panels such as gate drivers 316 and 317 and common electrodes 336 and 338 are provided on TAB-IC device 370. An input terminal of the TAB-IC device 370 is connected to the printed circuit board 374.

24 is a cross-sectional view of the liquid crystal display device 340 using the COG installation method. As shown in Fig. 24, an IC chip 404, which is a line sequential driver IC device, is directly attached to the TFT substrate 396 in the form of a crimp. Therefore, the projection panel of the device 340 can be miniaturized.

FIG. 25 is an outer sectional view of the printed circuit board 374 in FIG. 22. As shown in FIG. 25, there are a TAB tape 400, an IC chip 404, a fixing screw 406, an electronic component 408, and a heat sink 410 on the outer circumference of the printed circuit board 374. TAB tape 400 is bent so that its input terminal is attached to printed circuit board 374 in a crimp manner. The printed circuit board 374 and the TFT substrate 396 are fixed to the radiator 410.

A third embodiment of the present invention, which has been improved in the first embodiment of the present invention, will now be described.

The above-mentioned liquid crystal display device according to the first and second embodiments of the present invention has the block control lines BL1 to BL8 having n = 8. As shown in Fig. 26, all the block control lines BL1 to BL8 of the other blocks have the same width but different lengths. Therefore, the resistance values of the block control lines B1 to BL8 from the start point to the end point differ significantly from block to block. It is assumed that block control lines B1 to BL8 are arranged in a rectangular area having a length L and a width W0, and the rectangular areas are divided into eight areas corresponding to the first blocks B1 to eighth block B8, respectively.

Table 3 is data obtained by calculating the resistance values of the block control lines BL1 to BL8 having a constant width in each divided area from the start point to the end point.

First area Second area Third area Fourth area Fifth area Area 6 Area 7 8th zone Resistance 1st block 16.7 127.5 2nd block 16.7 16.7 382.6 3rd block 16.7 16.7 16.7 637.7 4th block 16.7 16.7 16.7 16.7 892.8 5th block 16.7 16.7 16.7 16.7 16.7 1147.9 6th block 16.7 16.7 16.7 16.7 16.7 16.7 1403.0 7th block 16.7 16.7 16.7 16.7 16.7 16.7 16.7 1658.1 8th block 16.7 16.7 16.7 16.7 16.7 16.7 16.7 16.7 1913.2

In the simulation, the width W0 of the rectangular area where the block control lines BL1 to BL8 are arranged is 387.2 μm, and the interval between adjacent block control lines is 8 μm. The first block control line BL1 receives the block control signals BL, that is, BC1 and / BC1. Similarly, the second to eighth block control lines 16 are supplied with the block control signals BC2 and / BC2 and BC8 and / BC8. In Table 3, units of numerical values other than the resistance value are microns (µm).

27 is a diagram illustrating resistance values of the first to eighth block control lines. As shown in Table 3 and Fig. 27, the block control lines in the different blocks have significantly different resistance values. The block control line has a load corresponding to the sum of the gate capacitance values of the 384 analog switches 514 of one block. The capacitance value of one analog switch 514 is about 1 kW and the load per block is about 384 kW. Therefore, the signal transmitted through the relatively long block control lines BL1 to BL8 is cut off. This causes display failure.

Moreover, the liquid crystal display device according to the first and second embodiments of the present invention has an arrangement requiring an analog switch 514 having a relatively wide channel width to complete writing data into pixels for a short time. Therefore, a large area must be provided on the glass substrate to form the analog switch 514.

Moreover, the display failure can be due to the elements introduced during the fabrication process of the polysilicon TFT and the elements related to the driving of the TFT.

In the following description, for the sake of simplicity, it is assumed that the number of pixels of the panel arranged along the horizontal direction is 800 x 3 (R, G, B) and the number of pixels of the panel arranged along the vertical direction is 600.

As shown in FIG. 28, the block control lines 567 in each divided area corresponding to the blocks B1 to B8 have different widths. In particular, the sixteen block control lines 567 are arranged in the first block control line arrangement area of the rectangular area (width W0 and length L) corresponding to the block B1. Fourteen block control lines are arranged in a second area corresponding to block B2, and twelve block control lines are arranged in a third area corresponding to block B3. As described above, the closer the position of the block is to the right side of the rectangular area, the smaller the number of block control lines having the expanded width.

In general, the expressions described below according to a third embodiment of the invention are satisfied:

w = (Wo-(n-1) S) / n

Here, Wo represents the width of each divided area, w represents the width of the block control line, n represents the number of block control lines, and S represents the interval between adjacent block control lines.

In the third embodiment of the present invention, adjacent areas are connected by lines having a relatively narrow width. The line is extremely short compared to the total length of the block control line 567 (about 1/200). Therefore, the narrow wire does not increase the resistance of the block control wire. The line inserted between the adjacent regions may be formed in a taper shape in which the line width gradually decreases.

Table 4 shows examples of the widths of the block control lines and the respective resistance values in the first to eighth divided regions. In Table 4, the first block control line 567 is supplied with the block control line signals BC1 and / BC1. Similarly, the second to eighth block control lines 567 are supplied with the block control line signals BC2 and / BC2 to BC8 and / BC8. In Table 4, units of numerical values other than the resistance value are microns (µm). The width of the block control line is calculated under the condition that the width W0 of the rectangular area in which the block control line 567 is arranged is approximately 380 µm and the interval between adjacent block control lines is 8 µm.

First area Second area Third area Fourth area Fifth area Area 6 Area 7 8th zone Resistance 1st block 16.8 63.4 2nd block 16.8 20.3 168.3 3rd block 16.8 20.3 25 253.5 4th block 16.8 20.3 25 31.6 320.9 5th block 16.8 20.3 25 31.6 41.5 372.2 6th block 16.8 20.3 25 31.6 41.5 58 409.0 7th block 16.8 20.3 25 31.6 41.5 58 91 432.4 8th block 16.8 20.3 25 31.6 41.5 58 91 190 443.6

29 is a diagram illustrating resistance values of the first to eighth block control lines. As shown in Table 4 and FIG. 29, the difference between the minimum resistance value (resistance value of the first block control line) and the maximum resistance value (resistance value of the eighth block control line) is 400 kΩ or less. Therefore, according to the third embodiment of the present invention, the difference between the resistance values of the other blocks can be reduced as compared with the prior art (see Fig. 27). Furthermore, according to the third embodiment of the present invention, since the maximum resistance value is considerably reduced, the shaping of the waveform of the block control signal can be suppressed, so that an improved display quality can be obtained.

Now, a fourth embodiment of the present invention will be described.

30 is a schematic diagram showing a wiring pattern of a block control line formed on a liquid crystal display panel according to a fourth embodiment of the present invention. In FIG. 30, the same parts as described in the previous drawings are given the same reference numerals, and detailed description thereof will be omitted.

The wiring pattern of the block control line shown in Fig. 30 is arbitrarily selected so that the resistance values of the lines 567 measured from the start point to the end point are almost equal to each other. In particular, the width of the block control line 567 in the first through eighth blocks is selected as shown in Table 5 to achieve almost the same resistance value. In Table 5, the unit of the numerical value other than the resistance value is microns, and the interval between adjacent block control lines is 8 m.

First area Second area Third area Fourth area Fifth area Area 6 Area 7 8th zone Resistance 1st block 8 266.3 2nd block 12 10 301.8 3rd block 12 16 20 328.4 4th block 18 20 22 26 344.4 5th block 20 24 24 28 38 362.9 6th block 24 25 31 32 38 50 363.5 7th block 24 26 30 35 45 57 94 365.5 8th block 21 26 28 42 50 72 93 195 365.4

31 is a diagram illustrating resistance values of the first to eighth block control lines. As shown in Table 5 and FIG. 31, the difference between the minimum resistance value (resistance value of the first block control line) and the maximum resistance value (resistance value of the eighth block control line) is approximately 100 kV. It is noted that the difference obtained according to the fourth embodiment of the present invention is considerably smaller than that obtained according to the third embodiment of the present invention. Therefore, the shaping of the waveform of the control signal can be further suppressed so that a further improved display quality can be obtained.

32 is a modified view of the third and fourth embodiments of the present invention. In particular, Fig. 32 shows the connection between the block control line and the analog switch in the block.

When the block control line 567 and the analog switch 514 are connected to the ends of the blocks B1 to B8, they are associated with the analog switch 514 located at the other end of the block, such as the block control line associated with the analog switch 514 located at one end of the block. The block control line has a large difference in resistance. This may degrade the display quality.

With this in mind, as shown in Fig. 32, the block control line 537 at the center of the block is connected to the line 541 connecting the analog switch 514 at both ends of the block. Therefore, the difference between the resistance values in the same block can be reduced and the display quality can be prevented from deteriorating.

33 is a schematic cross-sectional view showing the structure of the block control line 567. The structure in FIG. 33 has a multilayer structure in which lower layer block control lines 537a and upper layer block control lines 537b are electrically connected to each other through contact holes 542a formed in the insulating film 542 inserted therebetween. . With this structure, the resistance value of the block control line 567 can be further reduced.

As described above, the third and fourth embodiments of the present invention use control signal lines having different widths in the same area or different areas to reduce the resistance difference between the control lines. The above-described advantages can be obtained by varying the intrinsic resistance value (resistance value per unit length) of the block control line and / or the layer structure (single layer structure or multilayer structure).

For example, when the block control lines BL1 to BL8 in FIG. 26 have the same width, if the block control lines BL1 to BL8 are designed to have different intrinsic resistance values, the difference value of the block control lines measured from the start point to the end point is decreased. Can be. For example, a line with a relatively short length, such as BL1, is composed of a material with a relatively high resistivity, and a line with a relatively long length, such as BL8, is composed of a material with a relatively small resistivity. Relatively short lines are formed in a single layer structure and relatively long lines are formed in a multilayer structure. In this case, advantages almost equal to those described above can be obtained.

The third and fourth embodiments of the present invention relate to improvements in block control lines connecting TAB terminals and analog switches. Alternatively, the concept of the third and fourth embodiments of the present invention can be applied to a block control line connecting an analog switch and a semiconductor chip having a COG connection on a glass substrate.

Now, a liquid crystal display according to a fifth embodiment of the present invention for improving the display quality by controlling the potential of the signal line will be described. In order to facilitate understanding of the fifth embodiment of the present invention, conventional signal line control will be described.

34 illustrates a basic structure of the liquid crystal display 610 including the signal line unit 612 and the pixel cell unit 614. The pixel cell portion 614 includes a pixel TFT 616, a liquid crystal C LC, and a storage capacitance C S.

The scan signal G is applied from the gate driver circuit (not shown in FIG. 34) to the gate of the pixel TFT 616 via the scan line. Therefore, the pixel TFT 616 is turned on. The display signal D is applied to the signal line unit 612 through the input unit 618. The display signal D passes through the pixel TFT 616 and is written into the liquid crystal C LC and the storage capacitor C S. The display is formed by the potential difference between the resulting pixel potential Vs and the potential (not shown) of the corresponding electrode. The display signal D is held until the scan signal G is supplied back to the pixel TFT 616. The period in which the display signal D is held in the pixel TFT 616 is the signal holding period. In FIG. 34, symbol R SL is the resistance of line signal portion 612, and C SL is its capacitance.

If the dc voltage is continuously applied to the liquid crystal C LC for a long time, the nature of the liquid crystal C LC is changed to deteriorate the quality. Therefore, the liquid crystal display 610 is driven by an ac voltage whose polarity is inverted with a predetermined period.

35 and 36 are waveform diagrams of the scan signal G and the display signal D applied to the pixel cell portion 614 of the liquid crystal display 610. In particular, FIG. 35 illustrates waveforms of the display signal D and the scan signal G supplied to the pixel cell unit 614 disposed above the display panel, and FIG. 36 illustrates a display supplied to the pixel cell unit 614 disposed below the display panel. The waveforms of the signal D and the scan signal G are shown.

As shown in Figs. 35 and 36, one frame is divided into first and second fields. In the first field, a display signal D having a potential within a range defined by + Vmax (eg, + 5V) and + Vmin (eg, + 2V) is supplied to each pixel cell portion 614. In the second field,- The display signal D having a potential within the range defined by Vmax (eg -5V) and -Vmin (eg -2V) is supplied. The median value of the amplitude of the display signal D is Vcom (e.g., 0V).

As shown in Fig. 35, the potential of the scanning signal G supplied to the pixel TFT 616 located on the upper part of the display panel is from -Vg (e.g. -8V) to + Vg (e.g. +) as soon as the first and second fields start. 8V). At this time, the pixel TFT 616 located in the upper panel is turned on and the display signal D is written therein.

In contrast, as shown in Fig. 36, the potential of the scan signal G supplied to the pixel TFT 616 located in the lower panel portion changes from -Vg to + Vg immediately before the first and second fields are over. At this time, the pixel TFT 616 located in the lower panel is turned on and the display signal D is written therein.

35 and 36, Vgs represents the gate source voltage of the pixel TFT 616, and Vds represents its source-drain voltage. For example, when Vmax = 5V, Vmin = 2V and Vg = 8V, the voltages Vgs and Vds of the pixel TFT 616 disposed on the upper panel are 3V and 0.5V, respectively. 36, the voltages Vgs and Vds of the pixel TFT 616 disposed on the lower panel are 13V and 10V, respectively. As described above, the voltages Vgs and Vds of the pixel TFT 616 depend on their positions.

37 is a relationship diagram between the gate voltage Vg of the pixel TFT 616 and the drain current Id. As shown in FIG. 37, the on current which is the charging current flowing when writing the display signal D to the pixel TFT 616 and the off current which is the leakage current flowing when the display signal D is held are applied to the pixel TFT 616. Each has a magnitude that depends on the voltages Vds and Vgs. That is, the magnitudes of the on and off currents flowing in the upper panel are different from the magnitudes of the on and off currents flowing in the lower panel.

38 is a waveform diagram showing the relationship between the rise time Tr required for the pixel potential to reach the potential Vs when the display signal D is applied, and the initial potential V SL0 at the potential V SL of the signal line portion 612.

As shown in Fig. 38, when the initial potential V SL0 is V1, time Tr1 is required for the pixel potential to rise to the potential Vs. It takes time Tr2 for the pixel potential to rise to the potential Vs when the initial potential V SL0 is V2. When the initial potential V SL0 is V3, time Tr3 is required for the pixel potential to rise to the potential Vs. The potentials V1, V2, V3 have the same relationship as V1>V2> V3 while the rise times Tr1, Tr2, Tr3 have a relationship such as Tr1 <Tr2 <Tr3. As described above, the time Tr required for the pixel potential to reach the potential Vs depends on the initial potential V SL0 of the signal line portion 612.

In the conventional liquid crystal display 610, the signal lines have different initial potentials V SL0 before the scan signal G is applied. Therefore, the rise time Tr required for the pixel potential to reach the predetermined potential Vs is different for each initial potential V SL0 . The writing times for writing the display signal D to the pixels are not equal to each other. Therefore, the device 610 has a uniform display image.

As described with reference to FIGS. 35 to 37, the off current flowing in the pixel TFT 616 disposed in the lower panel portion is considerably larger than the off current flowing in the pixel TFT 616 disposed in the upper panel portion. Therefore, the reduction rate of the pixel TFT 616 disposed in the upper panel portion is larger than that of the pixel TFT 616 disposed in the lower panel portion. Hence, up-to-down diagonal markings occur where the brightness is not uniform on the panel. In particular, the black display is relatively bright when black is displayed on the entire panel.

The fifth embodiment of the present invention aims to eliminate the above disadvantage and to periodically reset the relative potential of the signal line so that the rise time of the pixel potential is constant and the off current flows evenly in the pixel TFT.

39 shows a basic structure of a liquid crystal display according to a fifth embodiment of the present invention.

Referring to FIG. 39, the liquid crystal display 720 includes a display panel 724 having a signal line part 712 and a pixel cell part 714.

The signal line unit 712 includes a plurality of signal lines 746 to which the reset circuits 726 and 728 are connected. The reset circuit 726 is connected to the signal line 746 external to the display panel 724. The reset circuit 728 is connected to the signal line 746 on the display panel 724.

The reset circuits 726 and 728 are supplied with the reset signal R from a time generation circuit (not shown) during the signal sustain period at predetermined cycles. When the reset circuits 726 and 728 are turned on, the signal line 746 and the reset voltage generation source (not shown) provided from the outside of the display panel 724 are turned on, so that the potential of the signal line 746 is reset to the reset potential (reference potential) Vrs. Is set.

The reset circuits 726 and 728 serve to set the initial potential V SL0 of the signal line 746 to the same reset potential Vrs before the display signal D is written into the cell. Therefore, the rise time Tr in the pixel TFT 716 can be made even. Therefore, the writing time required for writing data to the pixel TFT 716 becomes constant and is the same. Furthermore, the reset circuits 726 and 728 serve to set the potential of the signal line 746 to the reset potential Vrs, so that the off currents flowing in the pixel TFT 716 can be the same. Therefore, the liquid crystal display 720 can execute high quality display with constant brightness. In FIG. 39, the symbol R SL represents the resistance of the signal line 746 and C SL represents its capacitance.

40 is a circuit diagram of a liquid crystal display device 730 with an analog switch according to a fifth embodiment of the present invention. In Fig. 40, the same parts as described in the previous figures are given the same reference numerals.

The liquid crystal display 730 has an analog switch 732. The analog switch control signal A is separately supplied to the analog switch 732 so that the switches are turned on. Therefore, the common signal line D1 and the pixel TFT 716 can be electrically connected. At this time, the display signal D transmitted from the driver IC device (not shown in FIG. 40) to the common signal line D1 is supplied to the pixel TFT 716 via the analog switch 732. Therefore, the pixel TFT 716 supplied with the display signal D can be selected by controlling the analog switch 732.

The reset circuits 726 are connected to common signal lines D1 to Dn, respectively. The reset circuit 728 is connected to the signal line 746. The reset circuit 726 receives the reset signal R from the timing generating circuit (not shown) during the signal holding period, and then sets the potentials of the common signal lines D1 to Dn as the reset potential Vrs. The reset circuit 728 receives the reset signal R from the timing generation circuit during the signal holding period, and then sets the potential of the signal line 746 to the reset potential Vrs.

The reset circuits 726 and 728 serve to set the initial potentials V SL0 of the common signal lines D1 to Dn with the same reset potential Vrs before the display signal D is written into the cell. Therefore, the rise time Tr in the pixel TFT 716 can be made even. Therefore, the writing time required for writing data to the pixel TFT 716 becomes constant and is the same. Furthermore, the reset circuits 726 and 728 serve to set the common signal lines D1 to Dn and the initial potential V SL0 of the signal line 746 to the reset potential Vrs, so that the off currents flowing in the pixel TFT 616 may be the same. Therefore, the liquid crystal display 720 can execute high quality display with constant brightness. In Fig. 40, the symbol R SL represents a resistance of one of the common signal lines D1 to Dn, and C SL represents its capacitance. Furthermore, symbols R L and C L represent the resistance and capacitance of signal line 746, respectively.

FIG. 41 is an image circuit diagram of the reset circuits 726 and 728, and FIG. 42 is another image circuit diagram thereof. Fig. 41 shows an n-channel MOS type reset circuit, and Fig. 42 shows a CMOS type reset circuit.

The reset circuit in FIG. 41 has a simple structure, and the reset circuit in FIG. 42 has a high driving force to reduce the reset time. The n-channel MOS transistor in FIG. 45 may be replaced with a p-channel MOS transistor. The transistor used in the image in FIG. 41 has a double gate. Likewise, a CMOS circuit may have a double gate. When the double gate transistor is used, the leakage current flowing in the pixel TFT 716 can be reduced during the signal holding period.

The reset circuit 726 may be provided in the driver IC device. 43 is a circuit of the driver IC device in which the reset circuit 726 is assembled.

The driver IC device, designated by reference numeral 722 as shown in FIG. 43, includes an internal IC circuit 734, a reset circuit 726, an operational amplifier 736, and protection elements 738, 739. The display signal D output by the internal IC circuit 734 is supplied to the display panel 724 through the operation amplifier 734. The reset signal R is supplied from the timing generation circuit to the reset circuit 726 when the potential of the signal line 746 is reset. Therefore, the intersection point between the internal IC circuit 734 and the operational amplifier 736 is set to the reset potential Vrs.

44 is a diagram showing the detailed structure of a liquid crystal display according to a fifth embodiment of the present invention. As shown in FIG. 44, the liquid crystal display device 740 includes the driver IC device 722, the block control lines BL1 to BLn, and the display panel 724. The display panel 724 is provided with a display area 725, common signal lines D1 to Dn, an analog switch 732, a gate driver circuit 742, and reset circuits 726 and 728. Since the peripheral circuit including the display area 725 and the gate driver circuit 742 is integrally formed with the display panel 724, the size of the liquid crystal display 740 may be easily reduced.

The display area 725 is divided into blocks B1 to Bn, and scanning lines 744 and signal lines 746 are disposed in each block. The pixel cell portion 714 is provided at the intersection where the scan line 744 and the signal line 746 cross each other. Each pixel cell portion 714 is composed of a pixel TFT 616, a liquid crystal C LC, and a storage capacitor Cs. The gate of the pixel TFT 616 is connected to the corresponding scan line 744 and its source is connected to the signal line 746. Furthermore, the drain of the pixel TFT 616 is connected to the corresponding liquid crystal layer and the storage capacitor Cs.

In each block B1 to Bn, n analog switches 732 are disposed. The common signal lines D1 to Dn are connected to the corresponding signal lines 746 on the display panel 724 through the analog switch 732.

In the display panel 724, the reset circuit 726 is connected to the common signal lines D1 to Dn, and the reset circuit 728 is connected to the signal line 746. The position of reset circuits 726 and 728 is not limited to those shown in FIG. For example, the reset circuit 726 is connected to the display signal output portion of the driver IC device 722 provided outside the display portion 724.

As shown in Fig. 44, the driver IC device 722 is connected to the common signal lines D1 to Dn. The driver IC device 722 receives the digital display signal from the external data driver and outputs the analog output signal D in the same manner as described above. The display signal D from the driver IC device 722 is transmitted to the display panel 724 in units of blocks through the common signal lines D1 to Dn in time division format. The driver IC device 722 may be provided in the display panel 724.

The analog switch 732 is supplied with a block control signal BL for turning on the analog switch 732 through the block control lines BL1 to BLn.

When driving the liquid crystal display device 740, the gate signal G is applied from the gate driving circuit 742 to one (first) of the scanning line 744 and to the gate of the pixel TFT 616. The signal line 746 is supplied with the display signal D transmitted to the common signal lines D1 to Dn through the analog switch 732. The display signal D is then input to the pixel TFT 616.

The potential of the common signal lines D1 to Dn is reset by the reset circuit 726 to the reference potential Vrs having a predetermined period. Furthermore, the potential of the signal line 746 is reset to the reference potential Vrs having a predetermined period by the reset circuit 728.

Operations of the liquid crystal display 740 will now be described with reference to FIGS. 44 and 45. 45 is a timing chart of the display signal D, the scan signal G, the block control signal BL and the reset signal R. FIG.

Referring to FIG. 45, the high level scan signal G is applied from the gate driver circuit 742 to the display area 725. The block control signal BL, which is kept at a high level for the next block control period Tb, is applied to the analog switch 732 of the block B1 to turn the switches on. At this time, the display signal D is applied from the driver IC device 722 to the block B1 through the common signal lines D1 to Dn.

After the display signal D is applied to the block B1, the reset signal R is supplied to the reset circuit 726 from the timing generation circuit provided outside the display panel 724. Therefore, the reset circuit 726 is operated to set the potential of the common signal lines D1 to Dn to the reset potential Vrs (e.g., Vcom).

The high level control signal BL is then applied to the analog switch 732 of block B2 during the block control period Tb. Therefore, the analog switch 732 is turned on. At this time, the display signal D from the driver IC device 722 is supplied to the block B2 through the common signal lines D1 to Dn during the block control period Tb. After the display signal D is applied to the block B2, the reset signal R is supplied to the reset circuit 726 from the timing generation circuit. Therefore, since the reset circuit 726 is operated, the potentials of the common signal lines D1 to Dn are set to the reset potential Vrs.

The above operation is repeated and the display signal D is applied to the block Bn. The potentials of the common signal lines D1 to Dn are then set to the reset potential Vrs by the reset circuit 726. Operation then enters the blanking period Tbk. When time Tb has elapsed after the blanking period Tbk has started, the scan signal G input to the display area 725 is changed to a low level. When the blanking period Tbk ends, the reset signal R is supplied from the timing generation circuit to the reset circuit 728. Therefore, since the reset circuit 728 is operated, the potential of the signal line 726 is set to the reset potential Vrs. The horizontal scanning period Th then ends. The next scanning line 744 is then driven and the display signal D is sequentially supplied to the blocks B1 to Bn.

The blanking period Tbk is sufficiently longer than the block control period Tb and satisfies the condition Tbk > Tb + Ton + Toff, where Ton and Toff represent the rise and fall times of the scan signal G, respectively.

In the liquid crystal display device 740, the block control signal BL can be applied to the analog switch 732 so that all the analog switches 732 of blocks B1 to Bn are turned on simultaneously for one horizontal scanning period Th.

As described above, the blocks B1 to Bn are sequentially selected. The data write time Tb per block in the liquid crystal display 740 which implements the above-mentioned block sequential driving operation is (Th-Tbk) / n. Same as Therefore, if the smaller number n of blocks is provided in the liquid crystal display device 740, the data subscription time Tb can be set longer. The longer the data write time Tb per block is affected by the variation during the rise time Ton and the fall time Toff of the gate scan signal G because of the dispersion characteristic of the TFT 526. Therefore, the data writing time Tb for each block can be sufficiently secured and the occurrence of display failures such as laser scanning lines or distortion lines can be prevented.

The reset circuit 726 resets the potential of the common signal lines D1 to Dn to the reset potential Vrs every time the block scanning is finished, and the reset circuit 728 resets the potential of the signal line 746 to the reset potential Vrs every time the horizontal scanning is finished. do. Therefore, the rise time of the pixel TFT 616 can be made constant, and the time for writing the display signal D can also be made constant. Moreover, since the potential of the signal line 746 is reset to the reset potential Vrs having a given period, a constant off current may flow in the pixel TFT 616 located in the upper and lower panels. Therefore, the liquid crystal display 740 can realize high quality display with a constant brightness.

The liquid crystal display 740 may be modified to have either the reset circuit 726 or the reset circuit 728. The timing at which the reset signal R is applied to the reset circuits 726 and 728 is not limited to that shown in FIG. 45 but may be set to other timings as long as the concept of the present invention is satisfied.

46 is a timing chart showing the relationship between the block control signal BL, the reset signal R, and the potential of the signal line 746. FIG. As shown in FIG. 46, the potential of the signal line 746 associated with the block B1 is Vs during the control period for the block B1. The reset signal R is supplied to the reset circuit 726 after the control period ends during the block B1. Moreover, the potential of the signal line 746 associated with the block B1 is set to Vcom, which is a reset potential (reference potential). Similarly, the reset signal R is supplied to the reset circuit 726 after the control period ends during the block B2, and the potential of the signal line 746 associated with the block B2 is set to Vcom, which is the reset potential (reference potential). In addition, the reset signal R is supplied to the reset circuit 726 after the control period ends during the block Bn and the potential of the signal line 746 is set to Vcom which is the reset potential (reference potential). The reset potential Vrs is not limited to Vcom but may be limited to other potential levels.

In the case where the reset potential Vrs is Vcom, the source potential of the pixel TFT 616 at the top and bottom of the display panel 724 is set to Vcom at a time other than the writing period for the display signal D. At this time, approximately equivalent off current flows in the pixel TFT 616 above and below the display panel 724. Therefore, since the effective voltages of the pixel TFTs 616 on the upper and lower portions of the display panel 724 are almost equal to each other, upside down diagonal display can be prevented.

As shown in FIG. 47, the polarity of the reset potential Vrs may vary depending on the polarity of the display signal D. FIG. In FIG. 47, the polarity of the display signal D is the same as that of the reset potential Vrs. For example, when the display signal D has a range between ± Vmin and ± Vmax, the reset potential Vrs is defined as Vrs = ± Vmin.

48 and 49 are waveform diagrams each showing variations in the potential of the display signal D caused when the polarity of the set potential Vrs varies. In particular, FIG. 48 shows the potential variation of the display signal D observed when Vrs = ± Vm. Figure 49 shows Vrs = ± 1/2 Vs indicates the potential variation of the display signal D observed at Vs.

As shown in Figs. 48 and 49, the reset potential Vrs is set to ± Vmin or ± 1/2. By setting it to Vs, the writing time of the display signal D can be reduced by the time required for rising from the potential Vcom. Moreover, since the common signal lines D1 to Dn and the signal line 746 are reset with a predetermined period, the difference between the rise times Tr of the display signal D due to the dispersion of the characteristics of the analog switch 732 can be greatly reduced. Besides, the reset potential Vrs is ± Vmin or ± 1/2 By setting it to Vs, a priming bias is applied to the analog switch 732. Therefore, since the increased initial charging current flows in the signal line 746 at the writing time of the display signal D, the display signal D can be written to the pixel TFT 616 at high speed. As shown in FIG. 49, Vrs = ± 1/2 When it is Vs, the rise time of the display signal D can be almost constant regardless of the level of the display signal D.

50A and 50B show the polarity of the reset potential Vrs in the liquid crystal display 740 in which the reset potential is field inverted. As shown in Fig. 50A, all signal lines 746 in the display area 725 are set to the positive reset potential + Vrs when in the positive field. As shown in Fig. 50B, all signal lines 746 in the display area 725 are set to negative reset potential -Vrs when in the negative field. 51 is a timing chart of the display signal D, the reset signal R, and the reset signal Vrs.

52A and 52B show the polarity of the reset potential Vrs in the liquid crystal display 740 in which the reset potential is dot inverted (H / V line inverted). As shown in Fig. 52A, when the positive field is reset, the reset potential Vrs1 of the even signal line 746 is positive reset potential + Vrs, and the reset potential Vrs2 of the odd signal line 746 is negative reset potential -Vrs. As shown in Fig. 52B, the reset potential -Vrs1 of the even signal line 746 is negative reset potential -Vrs when the negative field is negative, and the reset potential + Vrs2 of the odd signal line 746 is positive reset potential + Vrs. The polarities of the reset potentials Vrs1 and Vrs2 vary on a line-by-field basis.

FIG. 53 shows the reset potentials Vrs1 and Vrs2, the reset signal R, the scan signal G, and the display signal D in the liquid crystal display 740 in which the reset potentials Vrs1 and Vrs2 are inverted in the H / V line format.

The concept of the fifth embodiment in the present invention is not limited to the block sequential driving liquid crystal display 740 but may be applied to the point sequential driving liquid crystal display or the line sequential driving liquid crystal display.

54 is a sequential driving type liquid crystal display device 750 to which the concept of the fifth embodiment is applied. As shown in Fig. 54, the device 750 includes common signal lines D1 to Dn, an analog switch 732 of a p-channel polysilicon TFT, a gate driver circuit 742, a display region 725, a shift register circuit 752, and the like. A buffer circuit 754 is included. Like parts in the apparatus 710, 720, 730, 740 mentioned above in FIG. 54 give the same reference numerals.

The shift register circuit 742 and the buffer circuit 754 form a timing generation circuit for generating an analog switch signal A for controlling the analog switch 732. The shift register circuit 752 is supplied with the start pulse SP and the clock signals CL and / CL. The operating frequency of the shift register circuit 752 is, for example, 0.5 MHz.

The scan line 744 and the signal line 746 are arranged in a matrix form in the display area 725. The pixel TFT 714 is provided at the intersection where the scanning line 744 and the signal line 746 intersect each other.

The analog switch control signal A is applied to the analog switch 732 by a combination of the shift register circuit 752 and the buffer circuit 754.

When driving the liquid crystal display device 750, the gate signal G is applied from the gate driver circuit 742 to one of the scanning lines 744 (first) and applied to the gate of the pixel TFT 616. The display signal D transmitted to the common signal lines D1 to Dn is supplied to the signal line 746 through the analog switch 732. The display signal D is then input to the pixel TFT 616 which is already on.

The potentials of the common signal lines D1 to Dn are reset by the reset circuit 726 to the reference potential Vrs (for example, Vcom) having a predetermined period. Furthermore, the potential of the signal line 746 is reset by the reset circuit 728 to the reference potential Vrs having a predetermined period.

The reset circuit 726 resets the potential of the common signal lines D1 to Dn to the reset potential Vrs at the end of every block scan, and the reset circuit 728 resets the potential of the signal line 746 at the end of every horizontal scan. Reset to Vrs. Therefore, the rise time of the pixel TFT 616 can be made constant, and a constant time for writing the display signal D can also be obtained. Furthermore, since the potential of the signal line 746 is reset to the reset potential Vrs having a predetermined period, a constant off current may flow in the pixel TFT 616 located in the upper and lower panels. Therefore, the liquid crystal display 750 can realize high quality display with a constant brightness.

55 illustrates a point sequential drive type liquid crystal display device 760. As shown in FIG. 55, the liquid crystal display device 760 includes a driver IC device 722, a display area 725, reset circuits 726 and 728, a gate driver circuit 742, and an operation amplifier 762. In FIG. 55, the same parts of the above-mentioned liquid crystal display devices 710, 720, 730, 740 and 750 are given the same reference numerals.

The reset circuit 726 is provided between the driver IC device 722 and the operational amplifier 762 and connected to the signal line 746.

When driving the liquid crystal display 760, the gate signal G is applied from the gate driver circuit 742 to one of the scanning lines 744 (first) and applied to the gate of the pixel TFT 616. The signal line 746 is supplied with the display signal D transmitted to the common signal lines D1 to Dn through the analog switch 732. The display signal D is then input to the pixel TFT 616 which is already on.

The reset circuit 726 is supplied with a reset signal R from a timing generating circuit (not shown in FIG. 55) having a predetermined period and resets the potential of the signal line 746 between the driver IC device 722 and the operational amplifier 762. Reset to potential Vrs (e.g., Vcom). The reset circuit 728 is supplied with the reset signal R and resets the signal line 746 to the reset potential Vrs.

The reset circuits 726 and 728 reset the potential of the signal line 746 to the reset potential Vrs. Therefore, the rise time Tr of the potential of the pixel TFT 616 becomes uniform and constant. As a result, the time for writing the display signal D can also be made constant. Moreover, since the potential of the signal line 746 is reset to the reset potential Vrs having a predetermined period, a constant off current can flow in the pixel TFT 616 located in the upper and lower panel portions. Therefore, the liquid crystal display 760 can realize high quality display with a constant brightness.

The operational amplifier 762 may be replaced with an analog switch 732.

56 shows a line sequential drive liquid crystal display 770. As shown in FIG. 56, the liquid crystal display device 770 includes a driver IC device 772, a display area 725, a reset circuit 728, and a gate side driver IC device 774. Like parts of the liquid crystal display devices 710, 720, 730, 740, 750 and 760 mentioned above in FIG. 56 are given the same reference numerals.

When driving the liquid crystal display 770, the gate signal G is applied from the gate driver circuit 774 to one of the scanning lines 744 (first) and to the gate of the pixel TFT 616. The display signal D transmitted from the driver IC device 772 to the common signal lines D1 to Dn is supplied to the signal line 746 through the analog switch 732. The display signal D is then input to the pixel TFT 616 which is already on.

The reset circuit 728 is supplied with a reset signal R from a timing generation circuit (not shown in FIG. 55) having a predetermined period and resets the potential of the signal line 746 between the driver IC device 722 and the operational amplifier 762. Reset to potential Vrs (e.g., Vcom). The reset circuit 728 is supplied with the reset signal R and resets the signal line 746 to the reset potential Vrs.

The reset circuit 728 resets the potential of the signal line 746 to the reset potential Vrs. Therefore, the rise time Tr of the potential of the pixel TFT 616 becomes uniform and constant. As a result, the time for writing the display signal D can also be made constant. Moreover, since the potential of the signal line 746 is reset to the reset potential Vrs having a predetermined period, a constant off current can flow in the pixel TFT 616 located in the upper and lower panel portions. Therefore, the liquid crystal display 760 can realize high quality display with a constant brightness.

The liquid crystal display 770 can be modified such that the reset circuit 726 is connected to the driver IC device 772 and the potential of the signal line 746 is reset to the reset potential Vrs having a predetermined period. The number of driver IC devices 772 and the number of driver IC devices 774 may be selected in consideration of the number of scanning lines 744 and signal lines 746 and the driving capability of the driver IC devices 772 and 774.

The invention is not particularly limited to the disclosed embodiments and variations and modifications may be made without departing from the scope of the invention. For example, the concepts of the above embodiments may be combined at random.

This application is based on Japanese Priority Application Nos. 10-305890, 10-306151, 11-013431 and all contents are incorporated herein.

As described above, according to the present invention, the data writing time Tb can be sufficiently secured for each block, and the display failure such as a laser scanning line or a distortion line can be caused. Furthermore, since the data writing time Tb per block can be set longer than the divided point sequential driving method, the frequency of the display signal D and the block control signal BL can be reduced, which can significantly improve the production yield and production margin of the liquid crystal display device.

In addition, it is possible to implement a high quality liquid crystal display device having a constant brightness by resetting the related potential of the signal line to make the rise time of the pixel potential constant and to equalize the off current in the pixel.

Claims (18)

  1. A display unit divided into blocks,
    A gate driver for driving scan lines arranged in the display unit one by one;
    And a data driver connected to one of the scan lines driven by the gate driver and supplying a display signal through a common signal line to a pixel located in one of blocks sequentially selected according to a block control signal. Liquid crystal display.
  2. The liquid crystal display device according to claim 1, wherein the divided regions are defined to correspond to the blocks, and each of the divided regions has a width of each block control line.
  3. A display unit having pixels arranged in a matrix form,
    A signal line and a scan line connected to the pixel,
    A data driver for supplying a display signal to the signal line;
    And a reset circuit for resetting the potential of the signal line to a predetermined potential having a given period.
  4. A display unit having pixels arranged in a matrix form,
    A signal line and a scan line connected to the pixel,
    Analog switches respectively connected to the signal lines;
    A data driver connected to an analog switch through a common signal line and supplying a display signal to the signal line through the analog switch, and
    And a reset circuit for resetting the potentials of the signal line and the common signal line to a predetermined potential having a given period.
  5. A display unit having pixels arranged in a matrix and divided into blocks;
    A signal line and a scan line connected to the pixel,
    An analog switch connected to the signal line and installed in the block,
    A data driver connected to the analog switch through a common signal line and supplying a display signal to the signal line through an analog switch installed in one of blocks sequentially selected according to a block control signal;
    And a reset circuit for resetting the potential of the signal line to a predetermined potential having a given period.
  6. The liquid crystal display of claim 1, further comprising a block control signal generator configured to generate the block control signal.
  7. 2. The method of claim 1, further comprising analog switches located within blocks and provided between the common signal lines and the pixels, wherein the analog switches located in one of the blocks selected by the block control signal are simultaneously activated. A liquid crystal display device characterized by the above-mentioned.
  8. The liquid crystal display of claim 1, wherein the data driver further comprises a display signal generator configured to generate a display signal from an applied digital signal and to apply a display signal to one of the selected blocks according to the block control signal. Display device.
  9. The formula of claim 2 wherein
    w = (Wo-(n-1) S) / n
    It satisfies the liquid crystal display device.
    (Wo denotes the width of each of the divided regions, w denotes the width of the block control signal lines, n denotes the number of block control lines, and S denotes the interval between adjacent block control lines among the block control lines. Indicates.)
  10. 3. The width of the block control line in each divided area is selected such that the block control line in each divided area has a nearly uniform resistance value measured from the start points to the end points of the block control line. Liquid crystal display.
  11. 3. The apparatus of claim 2, further comprising a signal line connecting the switch elements disposed in the same one of the blocks, wherein one of the corresponding block signal lines is connected to a central portion of the signal line connecting the switch elements. Liquid crystal display.
  12. The liquid crystal display of claim 1, wherein each block has a resistivity of each of the block control lines so that a difference in resistance values of the block control lines measured from the start points to the end points of the block control lines can be reduced.
  13. The liquid crystal display device according to claim 3 or 4, wherein the reset circuit is connected to the signal line.
  14. The liquid crystal display device according to claim 3 or 4, wherein the reset circuit is connected to an output of the driver.
  15. The liquid crystal display device according to claim 3 or 4, wherein the reset circuit includes a first reset circuit connected to the signal line and a second reset circuit connected to an output of the driver.
  16. The liquid crystal display device according to claim 4, wherein the reset circuit is connected to the common signal line.
  17. 5. The liquid crystal display device according to claim 4, wherein the reset circuit includes a first reset circuit connected to the signal line and a second reset circuit connected to one of an output part of the driver or a common signal line.
  18. delete
KR19990015047A 1998-10-27 1999-04-27 Liquid crystal display device KR100378556B1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP98-306151 1998-10-27
JP98-305890 1998-10-27
JP10305890A JP2000131670A (en) 1998-10-27 1998-10-27 Liquid crystal display device
JP30615198A JP4357613B2 (en) 1998-10-27 1998-10-27 LCD with integrated driver
JP01343199A JP4557325B2 (en) 1999-01-21 1999-01-21 Liquid crystal display
JP99-13431 1999-01-21

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KR100378556B1 true KR100378556B1 (en) 2003-03-31

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Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6670938B1 (en) * 1999-02-16 2003-12-30 Canon Kabushiki Kaisha Electronic circuit and liquid crystal display apparatus including same
US7173609B2 (en) * 2000-06-08 2007-02-06 Matsushita Electric Industrial Co., Ltd. Image display apparatus and image display method
JP3892650B2 (en) * 2000-07-25 2007-03-14 株式会社日立製作所 Liquid crystal display
JP4269542B2 (en) * 2001-06-04 2009-05-27 日本電気株式会社 Transistor operating point setting method and circuit, signal component value changing method, and active matrix liquid crystal display device
TW540020B (en) * 2001-06-06 2003-07-01 Semiconductor Energy Lab Image display device and driving method thereof
JP2003140188A (en) * 2001-11-07 2003-05-14 Hitachi Ltd Liquid crystal display device
JP2003228336A (en) * 2002-01-31 2003-08-15 Toshiba Corp Planar display device
JP2003280600A (en) * 2002-03-20 2003-10-02 Hitachi Ltd Display device, and its driving method
TW559748B (en) * 2002-10-25 2003-11-01 Toppoly Optoelectronics Corp Liquid crystal display with data line diving circuit arrangement
DE10252166A1 (en) * 2002-11-09 2004-05-19 Philips Intellectual Property & Standards Gmbh Matrix display with pixel selection arrangement of neighboring pixels being connected mutually with bordering control lines
JP4282985B2 (en) * 2002-12-27 2009-06-24 株式会社半導体エネルギー研究所 Method for manufacturing display device
KR100506090B1 (en) * 2003-02-08 2005-08-03 삼성전자주식회사 Liquid crystal display panel
TWI248600B (en) * 2003-05-08 2006-02-01 Ind Tech Res Inst Apparatus and method for supplying the video signal with time-division multiplexing
TW591594B (en) * 2003-05-19 2004-06-11 Au Optronics Corp LCD and internal sampling circuit thereof
JP3882796B2 (en) * 2003-07-22 2007-02-21 セイコーエプソン株式会社 Electro-optical device, driving method of electro-optical device, and electronic apparatus
JP4191136B2 (en) * 2004-03-15 2008-12-03 シャープ株式会社 Liquid crystal display device and driving method thereof
JP2005338421A (en) * 2004-05-27 2005-12-08 Renesas Technology Corp Liquid crystal display driving device and liquid crystal display system
TWI253049B (en) * 2004-06-24 2006-04-11 Hannstar Display Corp Display panel and driving method
KR100649249B1 (en) * 2004-06-30 2006-11-24 삼성에스디아이 주식회사 Demultiplexer, and light emitting display deviceusing the same and display panel thereof
JP2006023539A (en) * 2004-07-08 2006-01-26 Tohoku Pioneer Corp Self light emitting display panel and its driving method
JP4367386B2 (en) * 2004-10-25 2009-11-18 セイコーエプソン株式会社 Electro-optical device, driving circuit thereof, driving method, and electronic apparatus
JP2006215099A (en) * 2005-02-01 2006-08-17 Tohoku Pioneer Corp Device and method for driving light emitting display panel
JP2007017947A (en) * 2005-06-06 2007-01-25 Seiko Epson Corp Electro-optical device, method of driving the same, and electronic apparatus
JP5011788B2 (en) * 2005-06-17 2012-08-29 セイコーエプソン株式会社 Electro-optical device, driving method, and electronic apparatus
KR100726640B1 (en) * 2005-07-13 2007-06-11 엘지전자 주식회사 Plasma Display Apparatus and Driving Method of Plasma Display Panel
US20070035500A1 (en) * 2005-08-11 2007-02-15 Keisuke Takeo Data bus structure and driving method thereof
KR101152138B1 (en) * 2005-12-06 2012-06-15 삼성전자주식회사 Liquid crystal display, liquid crystal of the same and method for driving the same
KR20080008795A (en) * 2006-07-21 2008-01-24 삼성전자주식회사 Display substrate and display device having the same
KR101352344B1 (en) * 2006-09-13 2014-01-15 삼성디스플레이 주식회사 Signal transfer member and display apparatus having the same
KR101308455B1 (en) * 2007-03-07 2013-09-16 엘지디스플레이 주식회사 Liquid crystal display device
TWI374418B (en) 2007-05-15 2012-10-11 Novatek Microelectronics Corp Method and apparatus to generate control signals for display-panel driver
JP4524699B2 (en) * 2007-10-17 2010-08-18 ソニー株式会社 Display device
US9129576B2 (en) * 2008-05-06 2015-09-08 Himax Technologies Limited Gate driving waveform control
JP5713657B2 (en) * 2010-02-24 2015-05-07 キヤノン株式会社 Stereoscopic image control apparatus and control method thereof
JP5722573B2 (en) 2010-08-24 2015-05-20 株式会社ジャパンディスプレイ Display device with touch detection function
US9087492B2 (en) * 2012-04-23 2015-07-21 Au Optronics Corporation Bus-line arrangement in a gate driver
CN104218042B (en) * 2014-09-02 2017-06-09 合肥鑫晟光电科技有限公司 A kind of array base palte and preparation method thereof, display device
KR20160109905A (en) * 2015-03-13 2016-09-21 삼성전자주식회사 Gate Driver, Display driver circuit and display device comprising thereof
TWI643013B (en) * 2017-03-29 2018-12-01 友達光電股份有限公司 Display

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0668672B2 (en) * 1984-09-12 1994-08-31 ソニー株式会社 LCD display device
JPH065478B2 (en) 1984-12-28 1994-01-19 キヤノン株式会社 Active matrix circuit
JP2613370B2 (en) 1985-08-19 1997-05-28 セイコーエプソン株式会社 Color liquid crystal device
JPS6337394A (en) 1986-08-01 1988-02-18 Hitachi Ltd Matrix display device
US4890101A (en) 1987-08-24 1989-12-26 North American Philips Corporation Apparatus for addressing active displays
US4870399A (en) 1987-08-24 1989-09-26 North American Philips Corporation Apparatus for addressing active displays
JPH05210361A (en) 1992-01-31 1993-08-20 Toshiba Ave Corp Driving circuit of liquid crystal display device
JPH05328268A (en) 1992-05-27 1993-12-10 Toshiba Ave Corp Liquid crystal display device
JP3238758B2 (en) 1992-09-18 2001-12-17 富士通株式会社 Drive circuit for liquid crystal display
US5426447A (en) * 1992-11-04 1995-06-20 Yuen Foong Yu H.K. Co., Ltd. Data driving circuit for LCD display
JPH06167952A (en) 1992-12-01 1994-06-14 Hitachi Ltd Writing reset system liquid crystal panel driving circuit
US5574475A (en) 1993-10-18 1996-11-12 Crystal Semiconductor Corporation Signal driver circuit for liquid crystal displays
JP2962985B2 (en) 1993-12-22 1999-10-12 シャープ株式会社 Liquid Crystal Display
JPH07199874A (en) 1993-12-29 1995-08-04 Casio Comput Co Ltd Display driving device
US5739805A (en) 1994-12-15 1998-04-14 David Sarnoff Research Center, Inc. Matrix addressed LCD display having LCD age indication, and autocalibrated amplification driver, and a cascaded column driver with capacitor-DAC operating on split groups of data bits
JP3253481B2 (en) * 1995-03-28 2002-02-04 シャープ株式会社 Memory interface circuit
JP3230408B2 (en) 1995-04-20 2001-11-19 ソニー株式会社 Display device
KR0161918B1 (en) 1995-07-04 1999-03-20 구자홍 Data driver of liquid crystal device
JP3110980B2 (en) * 1995-07-18 2000-11-20 インターナショナル・ビジネス・マシーンズ・コーポレ−ション Driving device and method for liquid crystal display device
US6067066A (en) * 1995-10-09 2000-05-23 Sharp Kabushiki Kaisha Voltage output circuit and image display device
CN1297951C (en) * 1996-02-09 2007-01-31 精工爱普生株式会社 Signal wire precharging method, precharging circuit,chip of liquid crystal screen and liquid crystal display device
US6040812A (en) * 1996-06-19 2000-03-21 Xerox Corporation Active matrix display with integrated drive circuitry
JP2806366B2 (en) 1996-06-21 1998-09-30 日本電気株式会社 Liquid Crystal Display
JPH10143115A (en) 1996-11-11 1998-05-29 Sharp Corp Active matrix image display device
JPH10161612A (en) 1996-12-05 1998-06-19 Sony Corp Multiple image plane liquid crystal display unit
JP4011715B2 (en) 1997-03-03 2007-11-21 東芝松下ディスプレイテクノロジー株式会社 Display device
JP3300638B2 (en) * 1997-07-31 2002-07-08 株式会社東芝 Liquid crystal display

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