CN103426415A - Drive circuit of liquid crystal display panel and waveform driving approach - Google Patents
Drive circuit of liquid crystal display panel and waveform driving approach Download PDFInfo
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- CN103426415A CN103426415A CN2013103221942A CN201310322194A CN103426415A CN 103426415 A CN103426415 A CN 103426415A CN 2013103221942 A CN2013103221942 A CN 2013103221942A CN 201310322194 A CN201310322194 A CN 201310322194A CN 103426415 A CN103426415 A CN 103426415A
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Abstract
The invention provides a drive circuit of a liquid crystal display panel and a waveform driving approach. The drive circuit comprises a first signal line, a second signal line, a chip pin connector line, a first switch unit, a second switch unit, a first scanning line and second scanning line. The first signal line and the second signal line are located outside a pixel area of the liquid crystal display panel, the first switch unit and the second switch unit are connected with the chip pin connector line, a grid of the first switch unit and a grid of the second switch unit are connected to the chip pin connector line, a source of the first switch unit is connected to the first signal line, a drain of the first switch unit is connected to the first scanning line, a source of the second switch unit is connected to the second signal line, and a drain of the second switch unit is connected to the second scanning line.
Description
Technical field
The present invention relates to a kind of driving circuit and drive waveform method of display panels.
Background technology
Fig. 1 is the drives schematic diagram of existing general liquid crystal display, and liquid crystal display comprises: liquid crystal panel assembly (PANEL) 10, data driver (the Data Drive IC) 20 that is connected to liquid crystal panel assembly 10 and gate drivers (Scan Drive IC) 30, be connected to data driver 20 grayscale voltage maker (Gamma Voltage Generator) 40, provide the DC-DC power supply (DC/DC) 60 of power supply for the time schedule controller (TCON) 50 of control gate driver 30 and data driver 20 and for liquid crystal display.Liquid crystal panel assembly 10 comprise lower display panel and the upper display panel of mutual correspondence and be folded in display panel and lower display panel between liquid crystal.
Suppose that liquid crystal display has m bar data line, horizontal direction that n bar sweep trace is arranged in the vertical direction, be combined into the liquid crystal display of a m*n pixel, sweep trace intersects and limits a plurality of pixel cells with data line, and each pixel cell includes three sub-pixel unit PX.Each sub-pixel unit PX comprises a TFT switchgear, liquid crystal capacitance and memory capacitance, the TFT switchgear comprises the grid (Gate) formed together with sweep trace, the source electrode (Source) be connected with data line and the drain electrode (Drain) be connected with pixel electrode, and memory capacitance is connected to switchgear abreast.
The drives schematic diagram that above-mentioned Fig. 1 is general liquid crystal display, the existing liquid crystal display that also has a kind of known DualGate dot structure, Figure 2 shows that the schematic diagram of the liquid crystal display of existing Dual Gate dot structure, with the liquid crystal display of above-mentioned Fig. 1, compare, the liquid crystal display of Dual Gate dot structure has increased the sweep trace G of a times, public electrode wire Cs is identical with the public electrode wire quantity of above-mentioned Fig. 1, and be provided with two sub-pixel unit 1 between every two data lines S, 2, each sub-pixel unit includes a TFT switchgear 11, 21 and pixel electrode 12, 22, the grid of each TFT switchgear connects with corresponding sweep trace G.
The liquid crystal display of Dual Gate dot structure can be saved the source electrode driver of half number, but the gate drivers that need double, because the gate drivers cost is lower, so adopt the liquid crystal panel of Dual gate, than conventional architectures, reduced panel cost.
Summary of the invention
The present invention relates to a kind of driving circuit and drive waveform method of the display panels that gate drivers and/or source electrode driver can be reduced.
The invention provides a kind of driving circuit of display panels, it comprises: be positioned at outside the pixel region of display panels, and the first signal line that current potential is contrary and secondary signal line, the chip pin connecting line be connected with chip pin, all with the first switchgear and the second switch device of chip pin connecting line, and first, the second sweep trace, each switchgear includes grid, source electrode and drain electrode, the grid of the grid of described the first switchgear and second switch device all is connected to the chip pin connecting line, the source electrode of described the first switchgear is connected to the first signal line, the drain electrode of the first switchgear is connected to the first sweep trace, the source electrode of described second switch device is connected to the secondary signal line, the drain electrode of second switch device is connected to the second sweep trace.
The present invention provides again a kind of driving circuit of display panels, it comprises: be positioned at outside the pixel region of display panels, and the first signal line that current potential is contrary, secondary signal line and the 3rd signal wire, the chip pin connecting line be connected with chip pin, all with the first switchgear of chip pin connecting line, second switch device and the 3rd switchgear, and first, second, three scan line, each switchgear includes grid, source electrode and drain electrode, the grid of described the first switchgear, the grid of the grid of second switch device and the 3rd switchgear all is connected to the chip pin connecting line, the source electrode of described the first switchgear is connected to the first signal line, the drain electrode of the first switchgear is connected to the first sweep trace, the source electrode of described second switch device is connected to the secondary signal line, the drain electrode of second switch device is connected to the second sweep trace, the source electrode of described the 3rd switchgear is connected to the 3rd signal wire, the drain electrode of the 3rd switchgear is connected to three scan line.
The present invention provides again a kind of drive waveform method, when chip pin connecting line input noble potential first three/mono-in, the first signal line is noble potential too, the second and the 3rd signal wire input electronegative potential, the first switchgear is opened, thus the first sweep trace output grid opening signal; The second and the 3rd switchgear is also opened, but second and three scan line output grid shutdown signal; Within time of 1/3rd to 2/3rds of chip pin connecting line input noble potential, secondary signal line input noble potential, the first and the 3rd signal wire input electronegative potential, the second switch device is opened, thus the second sweep trace output grid opening signal; The first and the 3rd switchgear is also opened, but first and three scan line output grid shutdown signal; After chip pin connecting line input noble potential, in 1/3rd time, the 3rd signal wire is inputted noble potential, the first and second signal wires input electronegative potentials, and the 3rd switchgear is opened, thus three scan line output grid opening signal; The first and second switchgears are also opened, but the first and second sweep trace output grid shutdown signals.
The present invention provides again a kind of driving circuit of display panels, display panels comprises first substrate and the second substrate be oppositely arranged, and be folded in the liquid crystal between first substrate and second substrate, second substrate is provided with color membrane electrode, first substrate comprises: the pixel region that is positioned at display panels, and the first signal line that current potential is contrary, secondary signal line and the 3rd signal wire, crisscross sweep trace and data line, and the public electrode wire parallel with sweep trace, form memory capacitance between public electrode wire and corresponding sub-pixel unit, form liquid crystal capacitance between color membrane electrode and corresponding sub-pixel unit, described sweep trace intersects and limits some pixel cells with data line, each pixel cell comprises some sub-pixel unit, each sub-pixel unit comprises the first sub-pixel unit and the second sub-pixel unit, be provided with first in described the first sub-pixel unit, second switch device and the first pixel electrode, be provided with the 3rd in described the second sub-pixel unit, the 4th switchgear and the second pixel electrode, each switchgear is equipped with grid, source electrode and drain electrode, the grid of described the first switchgear connects the drain electrode of second switch device, the drain electrode of the 3rd switchgear is connected to the grid of described the 4th switchgear.
The present invention provides again a kind of driving circuit of display panels, display panels comprises first substrate and the second substrate be oppositely arranged, and be folded in the liquid crystal between first substrate and second substrate, second substrate is provided with color membrane electrode, first substrate comprises: the pixel region that is positioned at display panels, and the first signal line that current potential is contrary, secondary signal line and the 3rd signal wire, and crisscross sweep trace and data line, form memory capacitance between signal wire and corresponding sub-pixel unit, form liquid crystal capacitance between liquid crystal and corresponding sub-pixel unit, described sweep trace intersects and limits some pixel cells with data line, each pixel cell comprises some sub-pixel unit, each sub-pixel unit comprises the first sub-pixel unit and the second sub-pixel unit, be provided with first in described the first sub-pixel unit, second switch device and the first pixel electrode, be provided with the 3rd in described the second sub-pixel unit, the 4th switchgear and the second pixel electrode, each switchgear is equipped with grid, source electrode and drain electrode, the grid of described the first switchgear connects the drain electrode of second switch device, the drain electrode of the 3rd switchgear is connected to the grid of described the 4th switchgear.
The present invention provides again a kind of drive waveform method, within the first half section time that sweep trace is high level, the first signal line is all high level, the secondary signal line is low level, the second switch device of the first sub-pixel unit is opened, drive the first switchgear to open simultaneously, thereby be the first pixel electrode charging of the first sub-pixel unit; Within time second half section that sweep trace is high level, the secondary signal line is all high level, and the first signal line is low level, and the 3rd switchgear of the 3rd sub-pixel unit cuts out, drive the 4th switchgear to open simultaneously, thereby be the second pixel electrode charging of the second sub-pixel unit; When sweep trace is low level, first, second pixel electrode voltage is for maintaining state.
The present invention provides again a kind of driving circuit of display panels, display panels comprise first substrate and the second substrate be oppositely arranged and be folded in first substrate and second substrate between liquid crystal, second substrate is provided with color membrane electrode, this driving circuit is arranged on first substrate, and the pixel region of described driving circuit comprises outward: the chip pin connecting line be connected with chip pin, first signal line and secondary signal line, the first switchgear be connected with the chip pin connecting line respectively and second switch device, in the pixel region of this driving circuit, comprise: crisscross sweep trace, data line, and parallel with data line and be positioned at the 3rd signal wire and the 4th signal wire of data line both sides, by described adjacent two sweep traces, the 3rd signal wire, the 4th signal wire, and the 3rd a data line between signal wire and the 4th signal wire intersect and define four sub-pixel unit of first to fourth, be equipped with two switchgears and corresponding pixel electrode in each sub-pixel unit, definition is positioned at the first sub-pixel unit and is provided with the 3rd, the 4th switchgear and the first pixel electrode, definition is positioned at the second sub-pixel unit and is provided with the 5th, the 6th switchgear and the second pixel electrode, definition is positioned at the 3rd sub-pixel unit and is provided with the 7th, the 8th switch device and the 3rd pixel electrode, definition is positioned at the 4th sub-pixel unit and is provided with the 9th, the tenth switchgear and the 4th pixel electrode, the 4th switchgear of described the first sub-pixel unit is controlled by the 3rd switchgear, the 6th switchgear of described the second sub-pixel unit is controlled by the 5th switchgear, the 8th switch device of described the 3rd sub-pixel unit closes device by minion to be controlled, the tenth switchgear of described the 4th sub-pixel unit is controlled by the 9th switchgear.
The present invention provides again a kind of drive waveform method, within the first half section time that the chip pin connecting line is high level, the first signal line is also high level, the secondary signal line is low level, with first, the 3rd, the sweep trace input grid opening signal that is connected of the grid of the 5th switchgear, with second, the 5th, the sweep trace that is connected of the grid of the 9th switchgear inputs the grid shutdown signal; When the 3rd signal wire is high level in be high level at the chip pin connecting line time of front 1/4th, now the 4th signal wire is low level, the 3rd switchgear of the first sub-pixel unit is controlled the 4th switchgear and is opened, thereby is the pixel electrode charging of the first sub-pixel unit; When the 4th signal wire is high level in be high level at the chip pin connecting line time of 1/4th to 1/2nd, now the 3rd signal wire is low level, the 5th switchgear of the second sub-pixel unit is controlled the 6th switchgear and is opened, thereby is the pixel electrode charging of the second sub-pixel unit; When the 3rd signal wire is high level in be high level at the chip pin connecting line time of 1/2nd to 3/4ths, now the 4th signal wire is low level, the minion pass device of the 3rd sub-pixel unit is controlled the 8th switch device and is opened, thereby is the pixel electrode charging of the 3rd sub-pixel unit; It after the 4th signal wire is high level at the chip pin connecting line, in 1/4th time, is high level, now the 3rd signal wire is low level, the 9th switchgear of the 4th sub-pixel unit is controlled the tenth switchgear and is opened, thereby is the pixel electrode charging of the 4th sub-pixel unit.
The present invention is by increasing by one group of anti-phase signal wire, and the driving circuit of the composition such as switchgear the pixel region of display panels outside and/or in pixel region, the pulse signal that will be produced by gate drivers is divided into two or one is divided into three or one and is divided into four, form two or three or four grid impulse signals of opening successively, so gate drivers and/or source electrode driver number can be reduced, so the decrease panel cost.
The accompanying drawing explanation
Fig. 1 is the drives schematic diagram of existing general liquid crystal display;
Fig. 2 is the schematic diagram of the liquid crystal display of existing Dual Gate dot structure;
The schematic diagram of the equivalent electrical circuit that Fig. 3 is the first embodiment of the invention liquid crystal display panel drive circuit;
The waveform schematic diagram that Fig. 4 is the described driving circuit of Fig. 3;
The realistic simulation that Fig. 5 is driving circuit shown in Fig. 3 is figure as a result;
The schematic diagram of the equivalent electrical circuit that Fig. 6 is the second embodiment of the invention liquid crystal display panel drive circuit;
The waveform schematic diagram that Fig. 7 is the described driving circuit of Fig. 6;
The schematic diagram of the equivalent electrical circuit that Fig. 8 is the third embodiment of the invention liquid crystal display panel drive circuit;
The waveform schematic diagram that Fig. 9 is the described driving circuit of Fig. 8;
The realistic simulation that Figure 10 is driving circuit shown in Fig. 8 is figure as a result;
The schematic diagram of the equivalent electrical circuit that Figure 11 is the fourth embodiment of the invention liquid crystal display panel drive circuit;
The schematic diagram of the equivalent electrical circuit that Figure 12 is the fifth embodiment of the invention liquid crystal display panel drive circuit;
The partial enlarged drawing that Figure 13 is Figure 12;
The waveform schematic diagram that Figure 14 is the described driving circuit of Figure 12;
The schematic diagram of the equivalent electrical circuit that Figure 15 is the sixth embodiment of the invention liquid crystal display panel drive circuit;
The partial enlarged drawing that Figure 16 is Figure 15.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is not used in and limits the scope of the invention for the present invention is described, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
The schematic diagram of the equivalent electrical circuit that Fig. 3 is the first embodiment of the invention liquid crystal display panel drive circuit, this driving circuit comprises first, the second sweep trace 41, 42(G1-G4), be positioned at the outer one group of anti-phase first signal line CLK1 of display panels pixel region and secondary signal line CLK2, and first switchgear 31 and second switch device 32, the anti-phase meaning is that voltage is contrary, such as: if first signal line CLK1 input noble potential Vgh, the electronegative potential Vgl that secondary signal line CLK2 inputs so, the current potential that is also the current potential of first signal line CLK1 and secondary signal line CLK2 is contrary.Described first, second sweep trace 41,42 is by same chip pin connecting line 21(G12, G34) be connected to the same chip pin 20(IC pin of gate drivers (not shown)), and first signal line CLK1 is spatially all vertical with chip pin connecting line 21 with secondary signal line CLK2.
Fig. 3 has only illustrated two chip pin 20(IC pin1 and IC pin2), each chip pin 20 is by chip pin connecting line 21(G12) be connected to the first switchgear 31 and second switch device 32, the first grid G of described the first switchgear 31 is connected to chip pin connecting line 21, the first source S of the first switchgear 31 is connected to first signal line CLK1, and the first drain D of the first switchgear 31 is connected to the first sweep trace 41(G1, G3); The second grid G of described second switch device 32 also is connected to chip pin connecting line 21(G34), the second source S of second switch device 32 is connected to secondary signal line CLK2, and the second drain D of second switch device 32 is connected to the second sweep trace 42(G2, G4).
The waveform schematic diagram that Fig. 4 is driving circuit shown in Fig. 3, the input signal that G12 and G34 are gate drivers, CLK1 and CLK2 are the signal wire input signal, the output signal that G1 and G3 are the first sweep trace 41, the output signal that G3 and G4 are the second sweep trace 42, and G1, G2, G3, the G4 signal that is actual driving pixel region.
Within the first half section time of the chip pin connecting line G12 of gate drivers input grid opening signal, first signal line CLK1 inputs the grid opening signal too, secondary signal line CLK2 input grid shutdown signal, also: in the first half section time of the chip pin connecting line G12 input noble potential Vgh of gate drivers, first signal line CLK1 is noble potential Vgh too, secondary signal line CLK2 input electronegative potential Vgl.
The first switchgear 31 be connected with chip pin connecting line G12 is opened, and due to first signal line CLK1 input noble potential Vgh, therefore export to the source electrode of the first switchgear 31, is also noble potential, therefore the first sweep trace G1 output grid opening signal, i.e. noble potential Vgh; With the second switch device 32 that chip pin connecting line G12 is connected, also open, due to secondary signal line CLK2 input electronegative potential Vgl, therefore exporting to the source electrode of second switch device 32 is also electronegative potential, therefore the second sweep trace G2 output grid shutdown signal, that is: electronegative potential Vgl.
Within time second half section of the chip pin connecting line G12 of gate drivers input grid opening signal, secondary signal line CLK2 inputs the grid opening signal equally, first signal line CLK1 input grid shutdown signal, also: in time second half section of the chip pin connecting line G12 input noble potential Vgh of gate drivers, secondary signal line CLK2 input noble potential Vgh, first signal line CLK1 input electronegative potential Vgl, with the second switch device 32 that chip pin connecting line G12 is connected, open, thereby the second sweep trace G2 output grid opening signal, that is: noble potential; The first switchgear 31 be connected with chip pin connecting line G12 is also opened, but the first sweep trace G1 output grid shutdown signal, that is: electronegative potential.
Then sequentially input chip pin connecting line G34 input grid opening signal or the noble potential Vgh of gate drivers, its result is same as described above, output scanning line G3 and G4 signal successively, just repeated description not.
First embodiment of the invention is by increasing by one group of anti-phase first signal line CLK1 and secondary signal line CLK2, and the pulse signal that gate drivers is produced is divided into two, and forms two pulse signals of opening successively grid.
The realistic simulation that Fig. 5 is driving circuit shown in Fig. 3 is figure as a result, and the equivalent electrical circuit through shown in Fig. 3, can produce desirable G1 and G2 pulse signal.
By gate drivers, produce as G12 and G34 pulse signal, via signal wire CLK1, CLK2, be converted to the sweep signal as G1-G4, and the signal that G1-G4 is actual driving pixel region, the pulse signal also just gate drivers produced is divided into two, thereby can reduce the gate drivers of half, save the display panels cost.
The schematic diagram of the equivalent electrical circuit that Fig. 6 is the second embodiment of the invention liquid crystal display panel drive circuit, with above-mentioned the first embodiment, distinguish: being positioned at the outer signal wire of display panels pixel region has three: first signal line CLK1, secondary signal line CLK2 and the 3rd signal wire CLK3, the current potential difference of these three signal wires; Switchgear also has three: the first switchgear 31, second switch device 32 and the 3rd switchgear 33; Sweep trace be also three 41,42,43 by same chip pin connecting line 21(G123, G456) be connected to the same chip pin 20(IC pin of gate drivers (not shown)).
The first grid G of described the first switchgear 31 is connected to chip pin connecting line 21(G123), the first source S of the first switchgear 31 is connected to first signal line CLK1, and the first drain D of the first switchgear 31 is connected to the first sweep trace 41(G1, G4); The second grid G of described second switch device 32 also is connected to chip pin connecting line 21(G456), the second source S of second switch device 32 is connected to secondary signal line CLK2, and the second drain D of second switch device 32 is connected to the second sweep trace 42(G2, G5); The 3rd grid G of described second switch device 33 also is connected to chip pin connecting line 21(G456), the 3rd source S of the 3rd switchgear 33 is connected to the 3rd signal wire CLK3, and the 3rd drain D of the 3rd switchgear 33 is connected to three scan line 43(G3, G6).
The waveform schematic diagram that Fig. 7 is driving circuit shown in Fig. 6, within first three time of dividing of the chip pin connecting line G123 of gate drivers input grid opening signal, first signal line CLK1 inputs the grid opening signal too, secondary signal line CLK2 and secondary signal line CLK3 input grid shutdown signal, also: in the time of first three minute of the chip pin connecting line G12 input noble potential Vgh of gate drivers, first signal line CLK1 is noble potential Vgh too, secondary signal line CLK2 and secondary signal line CLK3 input electronegative potential Vgl, the first switchgear 31 be connected with chip pin connecting line G123 is opened, thereby the first sweep trace G1 output grid opening signal, that is: noble potential, the second switch device 32 and the 3rd switchgear 33 that with chip pin connecting line G123, are connected are also opened, but the second sweep trace G2 and three scan line G3 output grid shutdown signal, that is: electronegative potential.
Within 1/3rd to 2/3rds times of the chip pin connecting line G123 of gate drivers input grid opening signal, secondary signal line CLK2 inputs the grid opening signal equally, first signal line CLK1 and the 3rd signal wire CLK3 input grid shutdown signal, also: in 1/3rd to 2/3rds times of the chip pin connecting line G123 input noble potential Vgh of gate drivers, secondary signal line CLK2 input noble potential Vgh, first signal line CLK1 and the 3rd signal wire CLK3 input electronegative potential Vgl, with the second switch device 32 that chip pin connecting line G123 is connected, open, thereby the second sweep trace G2 output grid opening signal, that is: noble potential, the first switchgear 31 and the 3rd switchgear 33 that with chip pin connecting line G12, are connected are also opened, but the first sweep trace G1 and three scan line G3 output grid shutdown signal, that is: electronegative potential.
After the chip pin connecting line G123 of gate drivers input grid opening signal in 1/3rd times, the 3rd signal wire CLK3 inputs the grid opening signal equally, first signal line CLK1 and secondary signal line CLK2 input grid shutdown signal, also: in rear 1/3rd times of the chip pin connecting line G123 input noble potential Vgh of gate drivers, the 3rd signal wire CLK3 input noble potential Vgh, first signal line CLK1 and secondary signal line CLK2 input electronegative potential Vgl, the 3rd switchgear 33 be connected with chip pin connecting line G123 is opened, thereby three scan line G3 output grid opening signal, that is: noble potential, the first switchgear 31 and the second switch device 32 that with chip pin connecting line G123, are connected are also opened, but the first sweep trace G1 and the second sweep trace G2 output grid shutdown signal, that is: electronegative potential.
Then sequentially input chip pin connecting line G456 input grid opening signal or the noble potential Vgh of gate drivers, its result is same as described above, output scanning line G4, G5 and G6 signal successively, just repeated description not.
One be divided into three again by pulse that gate drivers is produced, form the pulse signal of three sweep traces of opening successively, thereby gate drivers can be reduced to 1/3rd, saved the display panels cost.
First and second embodiment is the radical difference of the signal wire outside pixel region just, but actual ultimate principle is all that gate drivers is reduced, it has common specified features and " signal wire is set outside pixel region ", therefore have unicity between first and second embodiment.
The schematic diagram of the equivalent electrical circuit that Fig. 8 is the third embodiment of the invention liquid crystal display panel drive circuit, different from above-mentioned two embodiment: the driving circuit shown in Fig. 8 is positioned at the display panels pixel region, display panels of the present invention comprise first substrate and the second substrate be oppositely arranged and be folded in first substrate and second substrate between liquid crystal, in the present embodiment, first substrate is array base palte, second substrate is color membrane substrates, and second substrate is provided with color membrane electrode.
Array base palte comprises: crisscross sweep trace Gn 30 and data line S1/S2 50 and public electrode wire CS 70(Fig. 8 parallel with sweep trace have illustrated that two data lines, n are with sweep trace and two public electrode wires) and one group of anti-phase first signal line K1 61 and secondary signal line K2 62, this first signal line K1 61 is parallel to each other with secondary signal line K2 62 and is all parallel with sweep trace 30.
Described sweep trace 30 intersects and limits some pixel cells with data line 50, each pixel cell comprises that some sub-pixel unit (are generally three sub-pixel unit, be respectively R sub-pixel unit, G sub-pixel unit and B sub-pixel unit), each sub-pixel unit comprises the first sub-pixel unit and the second sub-pixel unit, be provided with first, second switchgear 71,72 and the first pixel electrode in described the first sub-pixel unit, be provided with the 3rd, the 4th switchgear 73,74 and the second pixel electrode in described the second sub-pixel unit.
Public electrode wire 70 is by forming memory capacitance Cst between fixed voltage and corresponding sub-pixel unit, general public electrode wire 3 connects common electric voltage Vcom or ground connection or other fixed voltages, and form the first memory capacitance Cst1 between public electrode wire 70 and the first pixel electrode, form the second memory capacitance Cst2 between public electrode wire 70 and the second pixel electrode; Form liquid crystal capacitance C between color membrane electrode and corresponding sub-pixel unit
LC, general liquid crystal capacitance C
LCConnect common electric voltage Vcom or ground connection or other fixed voltages, and form the first liquid crystal capacitance C between color membrane electrode and the first pixel electrode
LC1, form the first liquid crystal capacitance C between color membrane electrode and the second pixel electrode
LC2.
The first grid of described the first switchgear 71 connects the second drain electrode of second switch device 72, the first source electrode of the first switchgear 71 connects corresponding data line 50, the first drain electrode of the first switchgear 71 connects the first pixel electrode, and form the first memory capacitance Cst1 between public electrode wire 70 and the first pixel electrode, form the first liquid crystal capacitance C between color membrane electrode and the first pixel electrode
LC1; The second grid of described second switch device 72 is connected to corresponding sweep trace 30, and the second source electrode of second switch device 72 is connected to first signal line K1 61, and the second drain electrode of second switch device 72 is connected to the first grid of described the first switchgear 71.
The 3rd grid of described the 3rd switchgear 73 is connected to the sweep trace 30 identical with the second grid of second switch device 72, the 3rd drain electrode that the 3rd source electrode of the 3rd switchgear 73 is connected to secondary signal line K2 62, the three switchgears 73 is connected to the 4th grid of described the 4th switchgear 74; The 4th grid of described the 4th switchgear 74 connects the 3rd drain electrode of the 3rd switchgear 73, the 4th source electrode of the 4th switchgear 74 connects corresponding data line 50, the 4th drain electrode of the 4th switchgear 74 connects the second pixel electrode, and form the second memory capacitance Cst2 between public electrode wire 70 and the second pixel electrode, form the second liquid crystal capacitance C between color membrane electrode and the second pixel electrode
LC2.
According to above-mentioned description, namely: the first switchgear 71 and the 4th switchgear 74 are symmetry status, and second switch device 72 and the 3rd switchgear 73 are symmetry status; And the first switchgear 71 is driven and controlled by second switch device 72, the 4th switchgear 74 is driven and is controlled by the 3rd switchgear 73.
When sweep trace Gn and first signal line K1 61 are all high level Vgh, the second switch device 72 of the first sub-pixel unit is opened, and drives the first switchgear 71 to open simultaneously, thereby is the first pixel electrode charging of the first sub-pixel unit; When sweep trace Gn and secondary signal line K2 62 are all high level Vgl, the 3rd switchgear 73 of the 3rd sub-pixel unit is opened, and drives the 4th switchgear 74 to open simultaneously, thereby is the second pixel electrode charging of the second sub-pixel unit.
The waveform schematic diagram that Fig. 9 is driving circuit shown in Fig. 8, public electrode wire CS70 is DC voltage DC, within the first half section time that sweep trace Gn is high level Vgh, first signal line K1 61 is all high level Vgh, secondary signal line K2 62 is low level Vgl, the second switch device 72 of the first sub-pixel unit is opened, and drives the first switchgear 71 to open simultaneously, thereby is the first pixel electrode charging of the first sub-pixel unit; Within time second half section that sweep trace Gn is high level Vgh, secondary signal line K2 62 is all high level Vgh, first signal line K1 61 is low level Vgl, the 3rd switchgear 73 of the 3rd sub-pixel unit is opened, drive the 4th switchgear 74 to open simultaneously, thereby be the second pixel electrode charging of the second sub-pixel unit; When sweep trace Gn is low level Vgl, upper and lower two row pixel electrode voltages are for maintaining state.
The realistic simulation that Figure 10 is driving circuit shown in Fig. 8 is figure as a result, and through the equivalent electrical circuit shown in Figure 10, pixel electrode can be charged desirable voltage.
This 3rd embodiment is by increasing by one group of anti-phase signal wire K1, K2, thereby the pulse signal that IC is inputted is divided into two, and forms two grid impulse signals of opening successively, and then the IC number of gate drivers is reduced to half quantity.
The schematic diagram of the equivalent electrical circuit that Figure 11 is the fourth embodiment of the invention liquid crystal display panel drive circuit, different from above-mentioned the 3rd embodiment: this 4th embodiment has saved public electrode wire CS, by corresponding pixel electrode and first signal line K161 or secondary signal line K2 62 formation memory capacitance Cst, thereby can increase pixel aperture ratio.
Owing to having saved public electrode wire CS, the first drain electrode of the first switchgear 71 connects the first pixel electrode, and form the second memory capacitance Cst1 between first signal line K1 61 and the first pixel electrode, form the first liquid crystal capacitance C between color membrane electrode and the first pixel electrode
LC1.
The 4th drain electrode of the 4th switchgear 74 connects the second pixel electrode, and forms the second memory capacitance Cst2 between secondary signal line K2 62 and the second pixel electrode, forms the second liquid crystal capacitance C between color membrane electrode and the second pixel electrode
LC2.
The pixel aperture ratio of this 4th embodiment is higher than conventional pixel, and due to signal wire K1 K2 be high frequency square wave voltage, so can't affect pixel voltage and picture disply.
The switchgear of above the third and fourth embodiment is exactly existing thin film transistor (TFT) TFT, and its channel layer all adopts oxide semiconductor.
First, second embodiment and the 3rd, the 4th embodiment are the signalization lines, just the signal wire of first, second embodiment is arranged on outside pixel region, three, the signal wire of the 4th embodiment is arranged in pixel region, but the purpose that first, second embodiment and the 3rd, the 4th embodiment reach is all by the negligible amounts of gate drivers, therefore there is specific common technical characterictic " signal wire " between first, second embodiment and the 3rd, the 4th embodiment, therefore there is unicity between first, second embodiment and the 3rd, the 4th embodiment.
The 3rd from the 4th embodiment, just the radical of the signal wire outside pixel region is different, but actual ultimate principle is all that gate drivers is reduced, it has common specified features and " signal wire is set outside pixel region ", therefore have unicity between first and second embodiment.
The schematic diagram of the equivalent electrical circuit that Figure 12 is the fifth embodiment of the invention liquid crystal display panel drive circuit, this the 5th embodiment is equivalent to two schemes of aforementioned four embodiment are combined, that is: the driving circuit formed by corresponding signal wire and switchgear all are set outside the pixel region of display panels and in pixel region, the driving circuit designed like this, gate drivers and source electrode driver number are reduced to half simultaneously, so the decrease panel cost.
Consult Figure 13 simultaneously, the partial enlarged drawing that Figure 13 is Figure 12, definition is positioned at the outer signal wire of pixel region and is respectively first signal line CLK1 101 and secondary signal line CLK2 102, and the signal wire that definition is positioned at pixel region is respectively the 3rd signal wire K1 401 and the 4th signal wire K2 402.
The pixel region of the driving circuit of this 5th embodiment comprises outward: the chip pin connecting line 201 be connected with the chip pin (not shown), first signal line CLK1 101 and secondary signal line CLK2 102, respectively with chip pin connecting line (Figure 12 illustrated two chip pin connecting line G12 and G34) 201 the first switchgear 301 and the second switch devices 302 that are connected.
In the pixel region of this driving circuit, comprise: crisscross sweep trace G(Figure 12 has illustrated G1-G4, wherein sweep trace G1 is 501, sweep trace G2 is 502), data line S601(Figure 12 has illustrated data line S1 and data line S2), and parallel with data line and be positioned at the 3rd signal wire K1 401 and the 4th signal wire K2 402 of data line both sides, by described adjacent two sweep trace G1/G2, the 3rd signal wire K1, the 4th signal wire K2, and the 3rd a data line S1 between signal wire K1 and the 4th signal wire K2 intersect and define four sub-pixel unit, be defined as respectively the first sub-pixel unit (1. what mark in Figure 12 and Figure 13 is), the second sub-pixel unit (2. what mark in Figure 12 and Figure 13 is), the 3rd sub-pixel unit (3. what mark in Figure 12 and Figure 13 is), and the 4th sub-pixel unit (4. what mark in Figure 12 and Figure 13 is), be equipped with two switchgears and corresponding pixel electrode in each sub-pixel unit, definition is positioned at the first sub-pixel unit and is provided with the third and fourth switchgear 303, the 304 and first pixel electrode, definition is positioned at the second sub-pixel unit and is provided with the 5th and the 6th switchgear 305, the 306 and second pixel electrode, definition is positioned at the 3rd sub-pixel unit and is provided with the 7th and the 8th switch device 307, the 308 and the 3rd pixel electrode, definition is positioned at the 4th sub-pixel unit and is provided with the 9th and the tenth switchgear 309, the 310 and the 4th pixel electrode.
The 3rd signal wire K1 and the 4th signal wire K2 are by between fixed voltage and corresponding sub-pixel unit, forming memory capacitance Cst, and color membrane electrode is by forming liquid crystal capacitance C between fixed voltage and corresponding sub-pixel unit
L C.
The annexation of this driving circuit is: the first grid of described the first switchgear 301 connects chip pin connecting line 201, the first drain electrode that the first source electrode of the first switchgear 301 connects first signal line CLK1 101, the first switchgears 301 connects sweep trace G1 501; The second grid of described second switch device 302 all is connected same chip pin connecting line 201 with the first grid of the first switchgear 301, the second source electrode of second switch device 302 connects secondary signal line CLK2 102, the second drain electrode of second switch device 302 connects sweep trace G2 502, and sweep trace G1 and sweep trace G2 are two adjacent sweep traces.
The 3rd grid of the 3rd switchgear 303 in the first sub-pixel unit connects sweep trace G1 501, and also: the 3rd grid of the 3rd switchgear 303 is connected same sweep trace with the first drain electrode of the first switchgear 301; The 3rd source electrode of the 3rd switchgear 303 connects the 4th grid of the 3rd drain electrode connection the 4th switchgear 304 of the 3rd signal wire K1 401, the three switchgears 303; The 4th grid of the 4th switchgear 304 connects the 3rd drain electrode of the 3rd switchgear, the 4th source electrode connection data line S1 601 of the 4th switchgear 304, the 4th drain electrode of the 4th switchgear 304 connects the first pixel electrode, and form the first memory capacitance Cst1 between the 3rd signal wire K1 401 and the first pixel electrode, form the first liquid crystal capacitance C between color membrane electrode and the first pixel electrode
LC2.
By above-mentioned explanation, the 4th switchgear 304 of the first sub-pixel unit is controlled by the 3rd switchgear 303.
The 5th grid of the 5th switchgear 305 in the second sub-pixel unit connects sweep trace G1 501, and also: the 5th grid of the 5th switchgear 305 all is connected same sweep trace with the first drain electrode of the 3rd grid of the 3rd switchgear 303, the first switchgear 301; The 5th source electrode of the 5th switchgear 305 connects the 5th grid of the 5th drain electrode connection the 6th switchgear 306 of the 4th signal wire K2 402, the five switchgears 305; The 6th grid of the 6th switchgear 306 connects the 5th drain electrode of the 5th switchgear 305, the 6th source electrode connection data line S1 601 of the 6th switchgear 306, the 6th drain electrode of the 6th switchgear 306 connects the second pixel electrode, and form the second memory capacitance Cst2 between secondary signal line K1 402 and the second pixel electrode, form the second liquid crystal capacitance C between color membrane electrode and the second pixel electrode
LC3.By above-mentioned explanation, the 6th switchgear 306 of the second sub-pixel unit is controlled by the 5th switchgear 305.
The 7th grid that minion in the 3rd sub-pixel unit is closed device 307 connects sweep trace G2 502, and also: the 7th grid that minion is closed device 307 all is connected same sweep trace with the second grid of second switch device 302; The 7th source electrode that minion is closed device 307 connects the 8th grid that the 3rd signal wire K1 401, the minions are closed the 7th drain electrode connection the 8th switch device 308 of device 307; The 8th grid of the 8th switch device 308 connects the 7th drain electrode that minion is closed device 307, the 8th source electrode connection data line S1601 of the 8th switch device 308, the 8th drain electrode of the 8th switch device 308 connects the 3rd pixel electrode, and form the 3rd memory capacitance Cst3 between the 3rd signal wire K1 401 and the 3rd pixel electrode, form the 3rd liquid crystal capacitance C between color membrane electrode and the 3rd pixel electrode
LC3.
By above-mentioned explanation, the 8th switch device 308 of the 3rd sub-pixel unit closes device 305 by minion to be controlled.
The 9th grid of the 9th switchgear 309 in the 4th sub-pixel unit connects sweep trace G2 502, and also: the 9th grid of the 9th switchgear 309 closes the 7th grid of device 307 with minion, the second drain electrode of second switch device 302 all is connected same sweep trace; The 9th source electrode of the 9th switchgear 309 connects the tenth grid of the 9th drain electrode connection the tenth switchgear 310 of the 4th signal wire K2 402, the nine switchgears 309; The tenth grid of the tenth switchgear 310 connects the 9th drain electrode of the 9th switchgear 309, the tenth source electrode connection data line S1 601 of the tenth switchgear 310, the tenth drain electrode of the tenth switchgear 310 connects the first pixel electrode, and form the 4th memory capacitance Cst4 between the 4th signal wire K1 402 and the 4th pixel electrode, form the 4th liquid crystal capacitance C between color membrane electrode and the 4th pixel electrode
LC4.
By above-mentioned explanation, the tenth switchgear 310 of the 4th sub-pixel unit is controlled by the 9th switchgear 309.
The waveform schematic diagram that Figure 14 is driving circuit shown in Figure 13, the pixel electrode of the pixel electrode of pixel electrode charging order the first sub-pixel unit, the pixel electrode of the second sub-pixel unit, the 3rd sub-pixel unit and the pixel electrode of the 4th sub-pixel unit.
Within the first half section time that chip pin connecting line G12 is high level Vgh, first signal line CLK1 101 is also high level Vgh, and secondary signal line CLK2 102 is low level, thus sweep trace G1 output grid line opening signal, sweep trace G2 output grid shutdown signal.
Within time of front 1/4th that the 3rd signal wire K1 401 is high level Vgh at chip pin connecting line G12, be high level Vgh, now the 4th signal wire K2 402 is low level Vgl, the 3rd switchgear 303 of the first sub-pixel unit is opened, the 3rd switchgear 303 drives control the 4th switchgear 304 to open simultaneously, thereby is the pixel electrode charging of the first sub-pixel unit; Within time of 1/4th to 1/2nd that the 4th signal wire K2 402 is high level Vgh at chip pin connecting line G12, be high level Vgh, now the 3rd signal wire K1 401 is low level Vgl, the 5th switchgear 305 of the second sub-pixel unit is opened, the 5th switchgear 306 drives control the 6th switchgear 306 to open simultaneously, thereby is the pixel electrode charging of the second sub-pixel unit; Within time of 1/2nd to 3/4ths that the 3rd signal wire K1 401 is high level Vgh at chip pin connecting line G12, be high level Vgh, now the 4th signal wire K2 402 is low level Vgl, the minion pass device 307 of the 3rd sub-pixel unit is opened, this minion pass device 307 is controlled the 8th switch device 308 simultaneously and is opened, thereby is the pixel electrode charging of the 3rd sub-pixel unit; When the 4th signal wire K2 402 chip pin connecting line G12 be high level Vgh after be high level Vgh in time of 1/4th, now the 3rd signal wire K1 401 is low level Vgl, the 9th switchgear 309 of the 4th sub-pixel unit is opened, the 9th switchgear 309 drives control the tenth switchgear 310 to open simultaneously, thereby is the pixel electrode charging of the 4th sub-pixel unit.
The schematic diagram of the equivalent electrical circuit that Figure 15 is the sixth embodiment of the invention liquid crystal display panel drive circuit, the partial enlarged drawing that Figure 16 is Figure 15, this the 6th embodiment from above-mentioned the 5th embodiment difference is: the connected mode of the 3rd signal wire K1 and the 4th signal wire K2 and switchgear is different: the 3rd, the 5th, the 7th, the 9th switchgear 303, 305, 307, 309 grid still connects corresponding sweep trace, the 3rd, the 5th, the 7th, the 9th switchgear 303, 305, 307, 309 source electrode changes connection data line S1, the 3rd, the 5th, the 7th, the 9th switchgear 303, 305, 307, 309 drain electrode changes connection the corresponding the 4th, the 6th, the 8th, the tenth switchgear 304, 306, 308, 310 source electrode, the 4th the 3rd signal wire K1 be connected with the grid of the 8th switch device 304,308, the 6th is connected the 4th signal wire K2 with the grid of the tenth switchgear 306,310, four, the source electrode of the 6th, the 8th, the tenth switchgear 304,306,308,310 changes the drain electrode that connects corresponding the 3rd, the 5th, the 7th, the 9th switchgear 303,305,307,309, and the 4th is connected corresponding pixel electrode with the drain electrode of the 8th switch device 304,308.
The waveform schematic diagram of the driving circuit of this 6th embodiment is identical with the waveform schematic diagram of above-mentioned the 5th embodiment, it is all the driving circuit formed by corresponding signal wire and switchgear all are set outside the pixel region of display panels and in pixel region, the driving circuit designed like this, gate drivers and source electrode driver number are reduced to half simultaneously, so the decrease panel cost.
Five, the 6th embodiment merges above-mentioned first, second and the 3rd, the 4th embodiment, has unicity due between first, second and the 3rd, the 4th embodiment, therefore have separately unicity between the first to the 6th embodiment.
The present invention is by increasing by one group of anti-phase signal wire, and the driving circuit of the composition such as switchgear the pixel region of display panels outside and/or in pixel region, the pulse signal that will be produced by gate drivers is divided into two or one is divided into three or one and is divided into four, form two or three or four grid impulse signals of opening successively, so gate drivers and/or source electrode driver number can be reduced, so the decrease panel cost.
Claims (13)
1. the driving circuit of a display panels, it is characterized in that: it comprises: be positioned at outside the pixel region of display panels, and the first signal line that current potential is contrary and secondary signal line, the chip pin connecting line be connected with chip pin, all with the first switchgear and the second switch device of chip pin connecting line, and first, the second sweep trace, each switchgear includes grid, source electrode and drain electrode, the grid of the grid of described the first switchgear and second switch device all is connected to the chip pin connecting line, the source electrode of described the first switchgear is connected to the first signal line, the drain electrode of the first switchgear is connected to the first sweep trace, the source electrode of described second switch device is connected to the secondary signal line, the drain electrode of second switch device is connected to the second sweep trace.
2. the drive waveform method of driving circuit according to claim 1, it is characterized in that: within the first half section time of chip pin connecting line input noble potential, the first signal line is noble potential too, secondary signal line input electronegative potential, the first switchgear is opened, thus the first sweep trace output grid opening signal; The second switch device is also opened, but the second sweep trace output grid shutdown signal; Within time second half section of chip pin connecting line input noble potential, secondary signal line input noble potential, first signal line input electronegative potential, the second switch device is opened, thus the second sweep trace output grid opening signal; The first switchgear is also opened, but the first sweep trace output grid shutdown signal.
3. the driving circuit of a display panels, it is characterized in that: it comprises: be positioned at outside the pixel region of display panels, and the first signal line that current potential is contrary, secondary signal line and the 3rd signal wire, the chip pin connecting line be connected with chip pin, all with the first switchgear of chip pin connecting line, second switch device and the 3rd switchgear, and first, second, three scan line, each switch switchgear includes grid, source electrode and drain electrode, the grid of described the first switchgear, the grid of the grid of second switch device and the 3rd switchgear all is connected to the chip pin connecting line, the source electrode of described the first switchgear is connected to the first signal line, the drain electrode of the first switchgear is connected to the first sweep trace, the source electrode of described second switch device is connected to the secondary signal line, the drain electrode of second switch device is connected to the second sweep trace, the source electrode of described the 3rd switchgear is connected to the 3rd signal wire, and the drain electrode of the 3rd switchgear is connected to three scan line.
4. the drive waveform method of driving circuit according to claim 3, it is characterized in that: when chip pin connecting line input noble potential first three/mono-in, the first signal line is noble potential too, the second and the 3rd signal wire input electronegative potential, the first switchgear is opened, thus the first sweep trace output grid opening signal; The second and the 3rd switchgear is also opened, but second and three scan line output grid shutdown signal; Within time of 1/3rd to 2/3rds of chip pin connecting line input noble potential, secondary signal line input noble potential, the first and the 3rd signal wire input electronegative potential, the second switch device is opened, thus the second sweep trace output grid opening signal; The first and the 3rd switchgear is also opened, but first and three scan line output grid shutdown signal; After chip pin connecting line input noble potential, in 1/3rd time, the 3rd signal wire is inputted noble potential, the first and second signal wires input electronegative potentials, and the 3rd switchgear is opened, thus three scan line output grid opening signal; The first and second switchgears are also opened, but the first and second sweep trace output grid shutdown signals.
5. the driving circuit of a display panels, display panels comprises first substrate and the second substrate be oppositely arranged, and be folded in the liquid crystal between first substrate and second substrate, second substrate is provided with color membrane electrode, it is characterized in that: first substrate comprises: the pixel region that is positioned at display panels, and the first signal line that current potential is contrary, secondary signal line and the 3rd signal wire, crisscross sweep trace and data line, and the public electrode wire parallel with sweep trace, form memory capacitance between public electrode wire and corresponding sub-pixel unit, form liquid crystal capacitance between color membrane electrode and corresponding sub-pixel unit, described sweep trace intersects and limits some pixel cells with data line, each pixel cell comprises some sub-pixel unit, each sub-pixel unit comprises the first sub-pixel unit and the second sub-pixel unit, be provided with first in described the first sub-pixel unit, second switch device and the first pixel electrode, be provided with the 3rd in described the second sub-pixel unit, the 4th switchgear and the second pixel electrode, each switchgear is equipped with grid, source electrode and drain electrode, the grid of described the first switchgear connects the drain electrode of second switch device, the drain electrode of the 3rd switchgear is connected to the grid of described the 4th switchgear.
6. the driving circuit of display panels according to claim 5, it is characterized in that: the source electrode of the first switchgear connects corresponding data line, and the drain electrode of the first switchgear connects the first pixel electrode; The grid of described second switch device is connected to corresponding sweep trace, and the source electrode of second switch device is connected to the first signal line, and the drain electrode of second switch device is connected to the grid of described the first switchgear; The grid of described the 3rd switchgear is connected to the sweep trace identical with the grid of second switch device, and the source electrode of the 3rd switchgear is connected to the secondary signal line; The grid of described the 4th switchgear connects the drain electrode of the 3rd switchgear, and the source electrode of the 4th switchgear connects corresponding data line, and the drain electrode of the 4th switchgear connects the second pixel electrode.
7. the driving circuit of a display panels, display panels comprises first substrate and the second substrate be oppositely arranged, and be folded in the liquid crystal between first substrate and second substrate, second substrate is provided with color membrane electrode, it is characterized in that: first substrate comprises: the pixel region that is positioned at display panels, and the first signal line that current potential is contrary, secondary signal line and the 3rd signal wire, and crisscross sweep trace and data line, form memory capacitance between signal wire and corresponding sub-pixel unit, form liquid crystal capacitance between color membrane electrode and corresponding sub-pixel unit, described sweep trace intersects and limits some pixel cells with data line, each pixel cell comprises some sub-pixel unit, each sub-pixel unit comprises the first sub-pixel unit and the second sub-pixel unit, be provided with first in described the first sub-pixel unit, second switch device and the first pixel electrode, be provided with the 3rd in described the second sub-pixel unit, the 4th switchgear and the second pixel electrode, each switchgear is equipped with grid, source electrode and drain electrode, the grid of described the first switchgear connects the drain electrode of second switch device, the drain electrode of the 3rd switchgear is connected to the grid of described the 4th switchgear.
8. the driving circuit of display panels according to claim 7, it is characterized in that: the source electrode of the first switchgear connects corresponding data line, and the drain electrode of the first switchgear connects the first pixel electrode; The grid of described second switch device is connected to corresponding sweep trace, and the source electrode of second switch device is connected to the first signal line, and the drain electrode of second switch device is connected to the grid of described the first switchgear; The grid of described the 3rd switchgear is connected to the sweep trace identical with the grid of second switch device, and the source electrode of the 3rd switchgear is connected to the secondary signal line; The grid of described the 4th switchgear connects the drain electrode of the 3rd switchgear, and the source electrode of the 4th switchgear connects corresponding data line, and the drain electrode of the 4th switchgear connects the second pixel electrode.
9. according to the drive waveform method of the described driving circuit of claim 5 to 8, it is characterized in that: within the first half section time that sweep trace is high level, the first signal line is all high level, the secondary signal line is low level, the second switch device of the first sub-pixel unit is opened, drive the first switchgear to open simultaneously, thereby be the first pixel electrode charging of the first sub-pixel unit; Within time second half section that sweep trace is high level, the secondary signal line is all high level, and the first signal line is low level, and the 3rd switchgear of the 3rd sub-pixel unit is opened, drive the 4th switchgear to open simultaneously, thereby be the second pixel electrode charging of the second sub-pixel unit; When sweep trace is low level, first, second pixel electrode voltage is for maintaining state.
10. the driving circuit of a display panels, display panels comprise first substrate and the second substrate be oppositely arranged and be folded in first substrate and second substrate between liquid crystal, second substrate is provided with color membrane electrode, it is characterized in that: this driving circuit is positioned on first substrate, and the pixel region of described driving circuit comprises outward: the chip pin connecting line be connected with chip pin, first signal line and secondary signal line, the first switchgear be connected with the chip pin connecting line respectively and second switch device, in the pixel region of this driving circuit, comprise: crisscross sweep trace, data line, and parallel with data line and be positioned at the 3rd signal wire and the 4th signal wire of data line both sides, by described adjacent two sweep traces, the 3rd signal wire, the 4th signal wire, and the 3rd a data line between signal wire and the 4th signal wire intersect and define four sub-pixel unit of first to fourth, definition is positioned at the first sub-pixel unit and is provided with the 3rd, the 4th switchgear and the first pixel electrode, definition is positioned at the second sub-pixel unit and is provided with the 5th, the 6th switchgear and the second pixel electrode, definition is positioned at the 3rd sub-pixel unit and is provided with the 7th, the 8th switch device and the 3rd pixel electrode, definition is positioned at the 4th sub-pixel unit and is provided with the 9th, the tenth switchgear and the 4th pixel electrode, the 4th switchgear of described the first sub-pixel unit is controlled by the 3rd switchgear, the 6th switchgear of described the second sub-pixel unit is controlled by the 5th switchgear, the 8th switch device of described the 3rd sub-pixel unit closes device by minion to be controlled, the tenth switchgear of described the 4th sub-pixel unit is controlled by the 9th switchgear.
11. the driving circuit of a kind of display panels according to claim 10, it is characterized in that: three, the 4th signal wire is by forming memory capacitance between the pixel electrode with corresponding, color membrane electrode forms corresponding liquid crystal capacitance with corresponding pixel electrode, each switchgear is equipped with grid, source electrode and drain electrode, the grid of described the first switchgear connects the chip pin connecting line, the source electrode of the first switchgear connects the first signal line, and the drain electrode of the first switchgear connects sweep trace; The grid of described second switch device all is connected same chip pin connecting line with the grid of the first switchgear, and the source electrode of second switch device connects the secondary signal line, and the drain electrode of second switch device connects sweep trace; The grid of the 3rd switchgear connects sweep trace; The source electrode of the 3rd switchgear connects the 3rd signal wire, and the drain electrode of the 3rd switchgear connects the grid of the 4th switchgear; The source electrode connection data line of the 4th switchgear, the drain electrode of the 4th switchgear connects the first pixel electrode; The grid of the 5th switchgear connects sweep trace, and the grid of the 5th switchgear all is connected same sweep trace with the grid of the 3rd switchgear, the drain electrode of the first switchgear, the source electrode of the 5th switchgear connects the 4th signal wire, and the drain electrode of the 5th switchgear connects the grid of the 6th switchgear; The source electrode connection data line of the 6th switchgear, the drain electrode of the 6th switchgear connects the second pixel electrode; The grid that minion is closed device connects sweep trace; The source electrode that minion is closed device connects the 3rd signal wire, and minion is closed the grid of drain electrode connection the 8th switch device of device; The source electrode connection data line of the 8th switch device, the drain electrode of the 8th switch device connects the 3rd pixel electrode; The grid of the 9th switchgear connects sweep trace, and the grid of the 9th switchgear closes the grid of device with minion, the drain electrode of second switch device all is connected same sweep trace, and the sweep trace that the grid of this sweep trace and first, the 3rd, the 5th switchgear is connected is two adjacent sweep traces; The source electrode of the 9th switchgear connects the 4th signal wire, and the drain electrode of the 9th switchgear connects the grid of the tenth switchgear; The source electrode connection data line of the tenth switchgear, the drain electrode of the tenth switchgear connects the 4th pixel electrode.
12. the driving circuit of a kind of display panels according to claim 10, it is characterized in that: three, the 4th signal wire is by forming memory capacitance between fixed voltage and corresponding sub-pixel unit, liquid crystal is by forming liquid crystal capacitance between fixed voltage and corresponding sub-pixel unit, each switchgear is equipped with grid, source electrode and drain electrode, the grid of described the first switchgear connects the chip pin connecting line, the source electrode of the first switchgear connects the first signal line, and the drain electrode of the first switchgear connects sweep trace; The grid of described second switch device all is connected same chip pin connecting line with the grid of the first switchgear, and the source electrode of second switch device connects the secondary signal line, and the drain electrode of second switch device connects sweep trace; The grid of the 3rd switchgear connects sweep trace; The source electrode connection data line of the 3rd switchgear, the drain electrode of the 3rd switchgear connects the source electrode of the 4th switchgear; The grid of the 4th switchgear connects the 3rd signal wire, and the drain electrode of the 4th switchgear connects the first pixel electrode; The grid of the 5th switchgear connects sweep trace, and the grid of the 5th switchgear all is connected same sweep trace with the grid of the 3rd switchgear, the drain electrode of the first switchgear, the source electrode connection data line of the 5th switchgear, the drain electrode of the 5th switchgear connects the source electrode of the 6th switchgear; The grid of the 6th switchgear connects the 4th signal wire, and the drain electrode of the 6th switchgear connects the second pixel electrode; The grid that minion is closed device connects sweep trace; Minion is closed the source electrode connection data line of device, and minion is closed the source electrode of drain electrode connection the 8th switch device of device; The grid of the 8th switch device connects the 3rd signal wire, and the drain electrode of the 8th switch device connects the 3rd pixel electrode; The grid of the 9th switchgear connects sweep trace, and the grid of the 9th switchgear closes the grid of device with minion, the drain electrode of second switch device all is connected same sweep trace, and the sweep trace that the grid of this sweep trace and first, the 3rd, the 5th switchgear is connected is two adjacent sweep traces; The source electrode connection data line of the 9th switchgear, the drain electrode of the 9th switchgear connects the source electrode of the tenth switchgear; The grid connection data line of the tenth switchgear, the drain electrode of the tenth switchgear connects the 4th pixel electrode.
13. the drive waveform method according to claim 10 to 12 described driving circuits, it is characterized in that: within the first half section time that the chip pin connecting line is high level, the first signal line is also high level, the secondary signal line is low level, with first, the 3rd, the sweep trace input grid opening signal that is connected of the grid of the 5th switchgear, with second, the 5th, the sweep trace that is connected of the grid of the 9th switchgear inputs the grid shutdown signal; When the 3rd signal wire is high level in be high level at the chip pin connecting line time of front 1/4th, now the 4th signal wire is low level, the 3rd switchgear of the first sub-pixel unit is controlled the 4th switchgear and is opened, thereby is the pixel electrode charging of the first sub-pixel unit; When the 4th signal wire is high level in be high level at the chip pin connecting line time of 1/4th to 1/2nd, now the 3rd signal wire is low level, the 5th switchgear of the second sub-pixel unit is controlled the 6th switchgear and is opened, thereby is the pixel electrode charging of the second sub-pixel unit; When the 3rd signal wire is high level in be high level at the chip pin connecting line time of 1/2nd to 3/4ths, now the 4th signal wire is low level, the minion pass device of the 3rd sub-pixel unit is controlled the 8th switch device and is opened, thereby is the pixel electrode charging of the 3rd sub-pixel unit; It after the 4th signal wire is high level at the chip pin connecting line, in 1/4th time, is high level, now the 3rd signal wire is low level, the 9th switchgear of the 4th sub-pixel unit is controlled the tenth switchgear and is opened, thereby is the pixel electrode charging of the 4th sub-pixel unit.
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| CN108780625A (en) * | 2016-04-25 | 2018-11-09 | 三星电子株式会社 | LED display module, display device and its control method |
| CN109599405A (en) * | 2019-01-02 | 2019-04-09 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and correlation technique |
| CN111402819A (en) * | 2020-04-26 | 2020-07-10 | 华南师范大学 | Display device driving system, method and apparatus |
| CN111435200A (en) * | 2019-01-11 | 2020-07-21 | 惠科股份有限公司 | Liquid crystal display device, liquid crystal display panel and driving method thereof |
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