CN103426415B - The driving circuit of a kind of display panels and drive waveform method - Google Patents
The driving circuit of a kind of display panels and drive waveform method Download PDFInfo
- Publication number
- CN103426415B CN103426415B CN201310322194.2A CN201310322194A CN103426415B CN 103426415 B CN103426415 B CN 103426415B CN 201310322194 A CN201310322194 A CN 201310322194A CN 103426415 B CN103426415 B CN 103426415B
- Authority
- CN
- China
- Prior art keywords
- switching arrangement
- grid
- electrode
- signal wire
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention provides driving circuit and the waveform driver circuit thereof of a kind of display panels, comprising: the first signal wire being positioned at outside the pixel region of display panels and second signal line, chip pin wire, all with the first switching arrangement and the 2nd switching arrangement of chip pin wire, and first, 2nd sweep trace, the grid of described first switching arrangement and the grid of the 2nd switching arrangement are all connected to chip pin wire, the source electrode of described first switching arrangement is connected to the first signal wire, the drain electrode of the first switching arrangement is connected to the first sweep trace, the source electrode of described 2nd switching arrangement is connected to second signal line, the drain electrode of the 2nd switching arrangement is connected to the 2nd sweep trace.
Description
Technical field
The present invention relates to the driving circuit of a kind of display panels and drive waveform method.
Background technology
Fig. 1 is the circuit drives schematic diagram of existing general liquid-crystal display, and liquid-crystal display comprises: liquid crystal panel assembly (PANEL) 10, the data-driven device (DataDriveIC) 20 being connected to liquid crystal panel assembly 10 and gate drivers (ScanDriveIC) 30, the grayscale voltage maker (GammaVoltageGenerator) 40 being connected to data-driven device 20, for the sequential control device (TCON) 50 of control gate driving mechanism 30 and data-driven device 20 and provide the DC-DC power supply (DC/DC) 60 of power supply for liquid-crystal display. The liquid crystal that liquid crystal panel assembly 10 comprises mutually corresponding lower display panel and upper display panel and is folded between display panel and lower display panel.
Assuming that liquid-crystal display has m data line, horizontal direction to have n bar sweep trace in the vertical direction, be combined into the liquid-crystal display of a m*n pixel, sweep trace and data line intersect limit multiple pixel cell, each pixel cell includes three sub-pixel unit PX. Each sub-pixel unit PX comprises a TFT switch device, liquid crystal capacitance and memory capacitance, TFT switch device comprises the source electrode (Source) that the grid (Gate) formed together with sweep trace is connected and the drain electrode (Drain) being connected with pixel electrode with data line, and memory capacitance is connected to switching arrangement parallelly.
Above-mentioned Fig. 1 is the circuit drives schematic diagram of general liquid-crystal display, the existing liquid-crystal display also having a kind of public affairs to know DualGate pixel structure, Fig. 2 show the schematic diagram of the liquid-crystal display of existing DualGate pixel structure, compared with the liquid-crystal display of above-mentioned Fig. 1, the liquid-crystal display of DualGate pixel structure adds the sweep trace G of a times, public electrode wires Cs is identical with the public electrode wires quantity of above-mentioned Fig. 1, and between every two data lines S, it is provided with two sub-pixel unit 1, 2, each sub-pixel unit includes a TFT switch device 11, 21 and pixel electrode 12, 22, the grid of each TFT switch device connects with corresponding sweep trace G.
The liquid-crystal display of DualGate pixel structure can save the source electrode driver of half number, but the gate drivers that need to double, owing to gate drivers cost is lower, so adopting the liquid crystal panel of Dualgate, than conventional architectures, reduce panel cost.
Summary of the invention
The present invention relates to the driving circuit of a kind of display panels that gate drivers and/or source electrode driver can be reduced and drive waveform method.
The present invention provides the driving circuit of a kind of display panels, comprising: be positioned at outside the pixel region of display panels, and contrary the first signal wire of current potential and second signal line, the chip pin wire being connected with chip pin, all with the first switching arrangement and the 2nd switching arrangement of chip pin wire, and first, 2nd sweep trace, each switching arrangement includes grid, source electrode and drain electrode, the grid of described first switching arrangement and the grid of the 2nd switching arrangement are all connected to chip pin wire, the source electrode of described first switching arrangement is connected to the first signal wire, the drain electrode of the first switching arrangement is connected to the first sweep trace, the source electrode of described 2nd switching arrangement is connected to second signal line, the drain electrode of the 2nd switching arrangement is connected to the 2nd sweep trace.
The present invention provides again the driving circuit of a kind of display panels, comprising: be positioned at outside the pixel region of display panels, and the first signal wire that current potential is contrary, second signal line and the 3rd signal wire, the chip pin wire being connected with chip pin, all with the first switching arrangement of chip pin wire, 2nd switching arrangement and the 3rd switching arrangement, and first, 2nd, three scan line, each switching arrangement includes grid, source electrode and drain electrode, the grid of described first switching arrangement, the grid of the 2nd switching arrangement and the grid of the 3rd switching arrangement are all connected to chip pin wire, the source electrode of described first switching arrangement is connected to the first signal wire, the drain electrode of the first switching arrangement is connected to the first sweep trace, the source electrode of described 2nd switching arrangement is connected to second signal line, the drain electrode of the 2nd switching arrangement is connected to the 2nd sweep trace, the source electrode of described 3rd switching arrangement is connected to the 3rd signal wire, the drain electrode of the 3rd switching arrangement is connected to three scan line.
The present invention provides again a kind of drive waveform method, when chip pin wire input noble potential first three/mono-in, the first signal wire noble potential too, the 2nd and the 3rd signal wire input low potential, first switching arrangement is opened, thus the first sweep trace output grid opens signal; 2nd and the 3rd switching arrangement is also opened, but the 2nd and three scan line export grid close signal; When chip pin wire input noble potential 2/1sts to three/3rd time in, second signal line input noble potential, first and the 3rd signal wire input low potential, the 2nd switching arrangement is opened, thus the 2nd sweep trace export grid open signal; First and the 3rd switching arrangement also open, but first and three scan line export grid close signal; When chip pin wire inputs in the time of after noble potential 1/3rd, the 3rd signal wire input noble potential, the first and second signal wire input low potentials, the 3rd switching arrangement is opened, thus three scan line output grid opens signal; First and second switching arrangements are also opened, but the first and second sweep traces export grid closedown signal.
The present invention provides again the driving circuit of a kind of display panels, display panels comprises the first substrate and second substrate that are oppositely arranged, and the liquid crystal being folded between first substrate and second substrate, second substrate is provided with color membrane electrode, first substrate comprises: the pixel region being positioned at display panels, and the first signal wire that current potential is contrary, second signal line and the 3rd signal wire, crisscross sweep trace and data line, and the public electrode wires parallel with sweep trace, memory capacitance is formed between public electrode wires and corresponding sub-pixel unit, liquid crystal capacitance is formed between color membrane electrode and corresponding sub-pixel unit, described sweep trace and data line intersect limit some pixel cells, each pixel cell comprises some sub-pixel unit, each sub-pixel unit comprises the first sub-pixel unit and the 2nd sub-pixel unit, it is provided with first in described first sub-pixel unit, 2nd switching arrangement and the first pixel electrode, it is provided with the 3rd in described 2nd sub-pixel unit, 4th switching arrangement and the 2nd pixel electrode, each switching arrangement is equipped with grid, source electrode and drain electrode, the grid of described first switching arrangement connects the drain electrode of the 2nd switching arrangement, the drain electrode of the 3rd switching arrangement is connected to the grid of described 4th switching arrangement.
The present invention provides again the driving circuit of a kind of display panels, display panels comprises the first substrate and second substrate that are oppositely arranged, and the liquid crystal being folded between first substrate and second substrate, second substrate is provided with color membrane electrode, first substrate comprises: the pixel region being positioned at display panels, and the first signal wire that current potential is contrary, second signal line and the 3rd signal wire, and crisscross sweep trace and data line, memory capacitance is formed between signal wire and corresponding sub-pixel unit, liquid crystal capacitance is formed between liquid crystal and corresponding sub-pixel unit, described sweep trace and data line intersect limit some pixel cells, each pixel cell comprises some sub-pixel unit, each sub-pixel unit comprises the first sub-pixel unit and the 2nd sub-pixel unit, it is provided with first in described first sub-pixel unit, 2nd switching arrangement and the first pixel electrode, it is provided with the 3rd in described 2nd sub-pixel unit, 4th switching arrangement and the 2nd pixel electrode, each switching arrangement is equipped with grid, source electrode and drain electrode, the grid of described first switching arrangement connects the drain electrode of the 2nd switching arrangement, the drain electrode of the 3rd switching arrangement is connected to the grid of described 4th switching arrangement.
The present invention provides again a kind of drive waveform method, when in the first half section time that sweep trace is high level, first signal wire is all high level, second signal line is lower level, 2nd switching arrangement of the first sub-pixel unit is opened, drive the first switching arrangement to open simultaneously, thus it is the first pixel electrode charging of the first sub-pixel unit; When in time second half section that sweep trace is high level, second signal line is all high level, and the first signal wire is lower level, and the 3rd switching arrangement of the 3rd sub-pixel unit cuts out, drive the 4th switching arrangement to open simultaneously, thus it is the 2nd pixel electrode charging of the 2nd sub-pixel unit; When sweep trace is lower level, first, second pixel electrode voltage is maintenance state.
The present invention provides again the driving circuit of a kind of display panels, display panels comprises the first substrate and second substrate that are oppositely arranged and the liquid crystal being folded between first substrate and second substrate, second substrate is provided with color membrane electrode, this driving circuit is arranged on first substrate, comprises outside the pixel region of described driving circuit: chip pin wire, the first signal wire and second signal line, the first switching arrangement being connected with chip pin wire respectively and the 2nd switching arrangement being connected with chip pin, comprise in the pixel region of this driving circuit: crisscross sweep trace, data line, and it is parallel with data line and be positioned at the 3rd signal wire and the 4th signal wire of data line both sides, by described adjacent two sweep traces, 3rd signal wire, 4th signal wire, and the 3rd a data line between signal wire and the 4th signal wire intersect define first to fourth four sub-pixel unit, two switching arrangements and corresponding pixel electrode it is equipped with in each sub-pixel unit, definition is positioned at the first sub-pixel unit and is provided with the 3rd, 4th switching arrangement and the first pixel electrode, definition is positioned at the 2nd sub-pixel unit and is provided with the 5th, 6th switching arrangement and the 2nd pixel electrode, definition is positioned at the 3rd sub-pixel unit and is provided with the 7th, 8th switching arrangement and the 3rd pixel electrode, definition is positioned at the 4th sub-pixel unit and is provided with the 9th, tenth switching arrangement and the 4th pixel electrode, 4th switching arrangement of described first sub-pixel unit is controlled by the 3rd switching arrangement, 6th switching arrangement of described 2nd sub-pixel unit is controlled by the 5th switching arrangement, 8th switching arrangement of described 3rd sub-pixel unit is controlled by the 7th switching arrangement, tenth switching arrangement of described 4th sub-pixel unit is controlled by the 9th switching arrangement.
The present invention provides again a kind of drive waveform method, when in the first half section time that chip pin wire is high level, first signal wire is also high level, second signal line is lower level, the sweep trace input grid being connected with the grid of the first, the 3rd, the 5th switching arrangement opens signal, and the sweep trace input grid being connected with the grid of the 2nd, the 5th, the 9th switching arrangement closes signal; When the 3rd signal wire is high level within the time that chip pin wire is before high level 1/4th, now the 4th signal wire is lower level, 3rd switching arrangement control the 4th switching arrangement of the first sub-pixel unit is opened, thus is the pixel electrode charging of the first sub-pixel unit; When the 4th signal wire chip pin wire be high level 1/1st to two/4th time in for high level, now the 3rd signal wire is lower level, 5th switching arrangement control the 6th switching arrangement of the 2nd sub-pixel unit is opened, thus is the pixel electrode charging of the 2nd sub-pixel unit; When the 3rd signal wire chip pin wire be high level 3/1sts to four/2nd time in for high level, now the 4th signal wire is lower level, 7th switching arrangement control the 8th switching arrangement of the 3rd sub-pixel unit is opened, thus is the pixel electrode charging of the 3rd sub-pixel unit; When the 4th signal wire is high level within the time that chip pin wire is after high level 1/4th, now the 3rd signal wire is lower level, 9th switching arrangement control the tenth switching arrangement of the 4th sub-pixel unit is opened, thus is the pixel electrode charging of the 4th sub-pixel unit.
The present invention is by outside the pixel district of display panels and/or increase the driving circuit of the composition such as one group of anti-phase signal wire and switching arrangement in pixel region, the pulse signal produced by gate drivers is divided into two or one dividing into three or is divided into four, form two or three or four grid pulsing signals opened successively, so gate drivers and/or source electrode driver number can be reduced, so significantly reduce panel cost.
Accompanying drawing explanation
Fig. 1 is the circuit drives schematic diagram of existing general liquid-crystal display;
Fig. 2 is the schematic diagram of the liquid-crystal display of existing DualGate pixel structure;
Fig. 3 is the schematic diagram of the equivalent electrical circuit of first embodiment of the invention liquid crystal display panel drive circuit;
Fig. 4 is the waveform diagram of driving circuit described in Fig. 3;
Fig. 5 is the actual simulation result figure of driving circuit shown in Fig. 3;
Fig. 6 is the schematic diagram of the equivalent electrical circuit of second embodiment of the invention liquid crystal display panel drive circuit;
Fig. 7 is the waveform diagram of driving circuit described in Fig. 6;
Fig. 8 is the schematic diagram of the equivalent electrical circuit of third embodiment of the invention liquid crystal display panel drive circuit;
Fig. 9 is the waveform diagram of driving circuit described in Fig. 8;
Figure 10 is the actual simulation result figure of driving circuit shown in Fig. 8;
Figure 11 is the schematic diagram of the equivalent electrical circuit of fourth embodiment of the invention liquid crystal display panel drive circuit;
Figure 12 is the schematic diagram of the equivalent electrical circuit of fifth embodiment of the invention liquid crystal display panel drive circuit;
Figure 13 is the partial enlargement figure of Figure 12;
Figure 14 is the waveform diagram of driving circuit described in Figure 12;
Figure 15 is the schematic diagram of the equivalent electrical circuit of sixth embodiment of the invention liquid crystal display panel drive circuit;
Figure 16 is the partial enlargement figure of Figure 15.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of the various equivalent form of values of the present invention is all fallen within the application's claims limited range by those skilled in the art.
Fig. 3 is the schematic diagram of the equivalent electrical circuit of first embodiment of the invention liquid crystal display panel drive circuit, this driving circuit comprises first, 2nd sweep trace 41, 42(G1-G4), it is positioned at the outer one group of first anti-phase signal wire CLK1 and second signal line CLK2 of display panels pixel region, and first switching arrangement 31 and the 2nd switching arrangement 32, it is anti-phase that to be meant to voltage contrary, such as: if the first signal wire CLK1 inputs noble potential Vgh, the low potential Vgl that so second signal line CLK2 inputs, also namely the current potential of the first signal wire CLK1 is contrary with the current potential of second signal line CLK2. first, second sweep trace 41,42 described is by same chip pin wire 21(G12, G34) it is connected to the same chip pin 20(ICpin of gate drivers (not shown)), and the first signal wire CLK1 is spatially all vertical with chip pin wire 21 with second signal line CLK2.
Fig. 3 only illustrates two chip pin 20(ICpin1 and ICpin2), each chip pin 20 is by chip pin wire 21(G12) it is connected to the first switching arrangement 31 and the 2nd switching arrangement 32, first grid G of described first switching arrangement 31 is connected to chip pin wire 21, first source S of the first switching arrangement 31 is connected to the first signal wire CLK1, and the first drain D of the first switching arrangement 31 is connected to first sweep trace 41(G1, G3); The second gate pole G of described 2nd switching arrangement 32 is also connected to chip pin wire 21(G34), 2nd source S of the 2nd switching arrangement 32 is connected to second signal line CLK2, and the 2nd drain D of the 2nd switching arrangement 32 is connected to the 2nd sweep trace 42(G2, G4).
Fig. 4 is the waveform diagram of driving circuit shown in Fig. 3, G12 and G34 is the input signal of gate drivers, CLK1 and CLK2 is signal wire input signal, G1 and G3 is the output signal of the first sweep trace 41, G3 and G4 is the output signal of the 2nd sweep trace 42, and G1, G2, G3, G4 are the grid signal in actual driving pixel district.
When the chip pin wire G12 of gate drivers inputs in the first half section time that grid opens signal, first signal wire CLK1 inputs grid too and opens signal, second signal line CLK2 inputs grid and closes signal, also namely: the chip pin wire G12 of gate drivers inputs in the first half section time of noble potential Vgh, first signal wire CLK1 noble potential Vgh too, second signal line CLK2 input low potential Vgl.
The first switching arrangement 31 being connected with chip pin wire G12 is opened, and owing to the first signal wire CLK1 inputs noble potential Vgh, therefore the source electrode exporting to the first switching arrangement 31 is also noble potential, therefore the first sweep trace G1 output grid opens signal, i.e. noble potential Vgh; The 2nd switching arrangement 32 being connected with chip pin wire G12 is also opened, owing to second signal line CLK2 inputs low potential Vgl, therefore the source electrode exporting to the 2nd switching arrangement 32 is also low potential, therefore the 2nd sweep trace G2 exports grid closedown signal, that is: low potential Vgl.
When the chip pin wire G12 of gate drivers inputs in time second half section that grid opens signal, second signal line CLK2 inputs grid equally and opens signal, first signal wire CLK1 inputs grid and closes signal, also namely: the chip pin wire G12 of gate drivers inputs in time second half section of noble potential Vgh, second signal line CLK2 inputs noble potential Vgh, first signal wire CLK1 inputs low potential Vgl, the 2nd switching arrangement 32 being connected with chip pin wire G12 is opened, thus the 2nd sweep trace G2 output grid opens signal, that is: noble potential;The first switching arrangement 31 being connected with chip pin wire G12 is also opened, but the first sweep trace G1 exports grid closedown signal, that is: low potential.
Then the chip pin wire G34 input grid sequentially inputting gate drivers opens signal or noble potential Vgh, and its result is same as described above, exports sweep trace G3 and G4 signal successively, with regard to not repeated description.
The pulse signal that gate drivers produces, by increasing by one group of anti-phase first signal wire CLK1 and second signal line CLK2, is divided into two by first embodiment of the invention, forms two pulse signals opening grid successively.
Fig. 5 is the actual simulation result figure of driving circuit shown in Fig. 3, through the equivalent electrical circuit shown in Fig. 3, it is possible to produce desirable G1 and G2 pulse signal.
By gate drivers produce such as G12 and G34 pulse signal, via signal wire CLK1, CLK2, be converted to such as G1-G4 sweep signal, and G1-G4 is the grid signal in actual driving pixel district, also just the pulse signal that gate drivers produces is divided into two, such that it is able to reduce the gate drivers of half, save display panels cost.
Fig. 6 is the schematic diagram of the equivalent electrical circuit of second embodiment of the invention liquid crystal display panel drive circuit, distinguishing with above-mentioned first embodiment: the signal wire being positioned at outside display panels pixel region has the three: first signal wire CLK1, second signal line CLK2 and the 3rd signal wire CLK3, the current potential of these three signal wires is different; Switching arrangement also has the three: first switching arrangement 31, the 2nd switching arrangement 32 and the 3rd switching arrangement 33; Sweep trace be also three 41,42,43 by same chip pin wire 21(G123, G456) be connected to the same chip pin 20(ICpin of gate drivers (not shown)).
First grid G of described first switching arrangement 31 is connected to chip pin wire 21(G123), first source S of the first switching arrangement 31 is connected to the first signal wire CLK1, and the first drain D of the first switching arrangement 31 is connected to first sweep trace 41(G1, G4); The second gate pole G of described 2nd switching arrangement 32 is also connected to chip pin wire 21(G456), 2nd source S of the 2nd switching arrangement 32 is connected to second signal line CLK2, and the 2nd drain D of the 2nd switching arrangement 32 is connected to the 2nd sweep trace 42(G2, G5); 3rd grid G of described 2nd switching arrangement 33 is also connected to chip pin wire 21(G456), 3rd source S of the 3rd switching arrangement 33 is connected to the 3rd signal wire CLK3, and the 3rd drain D of the 3rd switching arrangement 33 is connected to three scan line 43(G3, G6).
Fig. 7 is the waveform diagram of driving circuit shown in Fig. 6, when the chip pin wire G123 of gate drivers inputs in the time of first three point that grid opens signal, first signal wire CLK1 inputs grid too and opens signal, second signal line CLK2 and second signal line CLK3 inputs grid and closes signal, also namely: in the time of first three point that the chip pin wire G12 of gate drivers inputs noble potential Vgh, first signal wire CLK1 noble potential Vgh too, second signal line CLK2 and second signal line CLK3 inputs low potential Vgl, the first switching arrangement 31 being connected with chip pin wire G123 is opened, thus the first sweep trace G1 output grid opens signal, that is: noble potential, the 2nd switching arrangement 32 and the 3rd switching arrangement 33 that are connected with chip pin wire G123 are also opened, but the 2nd sweep trace G2 and three scan line G3 exports grid closedown signal, that is: low potential.
When the chip pin wire G123 of gate drivers inputs in 2/1sts to three/3rd times that grid opens signal, second signal line CLK2 inputs grid equally and opens signal, first signal wire CLK1 and the 3rd signal wire CLK3 inputs grid and closes signal, also namely: the chip pin wire G123 of gate drivers inputs in 2/1sts to three/3rd times of noble potential Vgh, second signal line CLK2 inputs noble potential Vgh, first signal wire CLK1 and the 3rd signal wire CLK3 inputs low potential Vgl, the 2nd switching arrangement 32 being connected with chip pin wire G123 is opened, thus the 2nd sweep trace G2 output grid opens signal, that is: noble potential, the first switching arrangement 31 and the 3rd switching arrangement 33 that are connected with chip pin wire G12 are also opened, but the first sweep trace G1 and three scan line G3 exports grid closedown signal, that is: low potential.
Open after signal in 1/3rd times when the chip pin wire G123 of gate drivers inputs grid, 3rd signal wire CLK3 inputs grid equally and opens signal, first signal wire CLK1 and second signal line CLK2 inputs grid and closes signal, also namely: the chip pin wire G123 of gate drivers inputs in rear 1/3rd times of noble potential Vgh, 3rd signal wire CLK3 inputs noble potential Vgh, first signal wire CLK1 and second signal line CLK2 inputs low potential Vgl, the 3rd switching arrangement 33 being connected with chip pin wire G123 is opened, thus three scan line G3 output grid opens signal, that is: noble potential, the first switching arrangement 31 and the 2nd switching arrangement 32 that are connected with chip pin wire G123 are also opened, but the first sweep trace G1 and the 2nd sweep trace G2 exports grid closedown signal, that is: low potential.
Then the chip pin wire G456 input grid sequentially inputting gate drivers opens signal or noble potential Vgh, and its result is same as described above, exports sweep trace G4, G5 and G6 signal successively, with regard to not repeated description.
By the pulse one dividing into three again that gate drivers is produced, form the pulse signal of three sweep traces opened successively, such that it is able to gate drivers is reduced to 1/3rd, save display panels cost.
The radical that first and second embodiment is the signal wire outside pixel region is different, but actual ultimate principle is all reduced by gate drivers, it has common specified features " putting signal wire at pixel region peripheral hardware ", therefore has unicity between first and second embodiment.
Fig. 8 is the schematic diagram of the equivalent electrical circuit of third embodiment of the invention liquid crystal display panel drive circuit, with above-mentioned two embodiments the difference is that: the driving circuit shown in Fig. 8 is positioned at display panels pixel region, display panels of the present invention comprises the first substrate and second substrate that are oppositely arranged and the liquid crystal being folded between first substrate and second substrate, in the present embodiment, first substrate is array substrate, second substrate is color membrane substrates, and second substrate is provided with color membrane electrode.
Array substrate comprises: crisscross sweep trace Gn30 illustrates two data lines, n-th with sweep trace and two public electrode wires with data line S1/S250 and public electrode wires CS70(Fig. 8 parallel with sweep trace) and one group of first anti-phase signal wire K161 and second signal line K262, this first signal wire K161 be parallel to each other with second signal line K262 and all parallel with sweep trace 30.
Described sweep trace 30 and data line 50 intersect limit some pixel cells, each pixel cell comprises some sub-pixel unit and (is generally three sub-pixel unit, it is respectively R sub-pixel unit, G sub-pixel unit and B sub-pixel unit), each sub-pixel unit comprises the first sub-pixel unit and the 2nd sub-pixel unit, it is provided with first, second switching arrangement 71,72 and first pixel electrode in described first sub-pixel unit, in described 2nd sub-pixel unit, it is provided with the 3rd, the 4th switching arrangement the 73,74 and the 2nd pixel electrode.
Public electrode wires 70 is by forming memory capacitance Cst between fixed voltage and corresponding sub-pixel unit, general public electrode wires 3 connects common electric voltage Vcom or ground connection or other fixed voltages, and form the first memory capacitance Cst1 between public electrode wires 70 and the first pixel electrode, form the 2nd memory capacitance Cst2 between public electrode wires 70 and the 2nd pixel electrode; Liquid crystal capacitance C is formed between color membrane electrode and corresponding sub-pixel unitLC, general liquid crystal capacitance CLCConnect common electric voltage Vcom or ground connection or other fixed voltages, and form the first liquid crystal capacitance C between color membrane electrode and the first pixel electrodeLC1, form the first liquid crystal capacitance C between color membrane electrode and the 2nd pixel electrodeLC2。
First grid of described first switching arrangement 71 connects the 2nd drain electrode of the 2nd switching arrangement 72, first source electrode of the first switching arrangement 71 connects corresponding data line 50, first drain electrode of the first switching arrangement 71 connects the first pixel electrode, and form the first memory capacitance Cst1 between public electrode wires 70 and the first pixel electrode, form the first liquid crystal capacitance C between color membrane electrode and the first pixel electrodeLC1; The 2nd source electrode that the second gate pole of described 2nd switching arrangement 72 is connected to corresponding sweep trace the 30, two switching arrangement 72 is connected to the first signal wire K161, and the 2nd drain electrode of the 2nd switching arrangement 72 is connected to the first grid of described first switching arrangement 71.
3rd grid of described 3rd switching arrangement 73 is connected to the sweep trace 30 extremely identical with the second gate of the 2nd switching arrangement 72,3rd source electrode of the 3rd switching arrangement 73 is connected to second signal line K262, and the 3rd drain electrode of the 3rd switching arrangement 73 is connected to the 4th grid of described 4th switching arrangement 74; 4th grid of described 4th switching arrangement 74 connects the 3rd drain electrode of the 3rd switching arrangement 73,4th source electrode of the 4th switching arrangement 74 connects corresponding data line 50,4th drain electrode of the 4th switching arrangement 74 connects the 2nd pixel electrode, and between public electrode wires 70 and the 2nd pixel electrode, form the 2nd memory capacitance Cst2, form the 2nd liquid crystal capacitance C between color membrane electrode and the 2nd pixel electrodeLC2。
According to above-mentioned description, also it is exactly: the first switching arrangement 71 and the 4th switching arrangement 74 symmetrically state, the 2nd switching arrangement 72 and the 3rd switching arrangement 73 symmetrically state; And first switching arrangement 71 by the 2nd switching arrangement 72 drived control, the 4th switching arrangement 74 is by the 3rd switching arrangement 73 drived control.
When sweep trace Gn and the first signal wire K161 is all high level Vgh, the 2nd switching arrangement 72 of the first sub-pixel unit is opened, and drives the first switching arrangement 71 to open simultaneously, thus is the first pixel electrode charging of the first sub-pixel unit; When sweep trace Gn and second signal line K262 is all high level Vgl, the 3rd switching arrangement 73 of the 3rd sub-pixel unit is opened, and drives the 4th switching arrangement 74 to open simultaneously, thus is the 2nd pixel electrode charging of the 2nd sub-pixel unit.
Fig. 9 is the waveform diagram of driving circuit shown in Fig. 8, public electrode wires CS70 is volts DS DC, when in the first half section time that sweep trace Gn is high level Vgh, first signal wire K161 is all high level Vgh, second signal line K262 is lower level Vgl, 2nd switching arrangement 72 of the first sub-pixel unit is opened, and drives the first switching arrangement 71 to open simultaneously, thus is the first pixel electrode charging of the first sub-pixel unit; When in time second half section that sweep trace Gn is high level Vgh, second signal line K262 is all high level Vgh, first signal wire K161 is lower level Vgl, 3rd switching arrangement 73 of the 3rd sub-pixel unit is opened, drive the 4th switching arrangement 74 to open simultaneously, thus it is the 2nd pixel electrode charging of the 2nd sub-pixel unit; When sweep trace Gn is lower level Vgl, upper and lower two row pixel electrode voltages are maintenance state.
Figure 10 is the actual simulation result figure of driving circuit shown in Fig. 8, and through the equivalent electrical circuit shown in Figure 10, pixel electrode can be charged desirable voltage.
This 3rd embodiment is by increasing by one group of anti-phase signal wire K1, K2, thus is divided into two by the pulse signal that IC inputs, and forms two grid pulsing signals opened successively, and then falls the IC number of gate drivers for half quantity.
Figure 11 is the schematic diagram of the equivalent electrical circuit of fourth embodiment of the invention liquid crystal display panel drive circuit, with above-mentioned 3rd embodiment the difference is that: this 4th embodiment eliminates public electrode wires CS, form memory capacitance Cst by corresponding pixel electrode and the first signal wire K161 or second signal line K262, thus pixel aperture ratio can be increased.
Owing to eliminating public electrode wires CS, first drain electrode of the first switching arrangement 71 connects the first pixel electrode, and first form the 2nd memory capacitance Cst1 between signal wire K161 and the first pixel electrode, between color membrane electrode and the first pixel electrode, form the first liquid crystal capacitance CLC1。
4th drain electrode of the 4th switching arrangement 74 connects the 2nd pixel electrode, and forms the 2nd memory capacitance Cst2 between second signal line K262 and the 2nd pixel electrode, forms the 2nd liquid crystal capacitance C between color membrane electrode and the 2nd pixel electrodeLC2。
The pixel aperture ratio of this 4th embodiment higher than conventional pixel, and due to signal wire K1 K2 be high frequency square wave voltage, so pixel voltage and picture display can't be affected.
The switching arrangement of above third and fourth embodiment is exactly existing thin film transistor TFT, and its channel layer all adopts oxide semiconductor.
First, second embodiment and the 3rd, the 4th embodiment are all arrange signal wire, just the signal wire of first, second embodiment is arranged on outside pixel region, three, the signal wire of the 4th embodiment is arranged in pixel region, but the object that first, second embodiment and the 3rd, the 4th embodiment reach is all by the comparatively small amt of gate drivers, therefore there is between first, second embodiment and the 3rd, the 4th embodiment specific common technology feature " signal wire ", therefore between first, second embodiment and the 3rd, the 4th embodiment, there is unicity.
3rd is different from the radical of the 4th embodiment just signal wire outside pixel region, but actual ultimate principle is all reduced by gate drivers, it has common specified features " putting signal wire at pixel region peripheral hardware ", therefore has unicity between first and second embodiment.
Figure 12 is the schematic diagram of the equivalent electrical circuit of fifth embodiment of the invention liquid crystal display panel drive circuit, this the 5th embodiment is equivalent to combine two schemes of aforementioned four embodiments, that is: by all arranging corresponding signal wire and the driving circuit of switching arrangement composition in and pixel region outer at the pixel region of display panels, the driving circuit of design like this, gate drivers and source electrode driver number are reduced half simultaneously, so significantly reduces panel cost.
Consult Figure 13 simultaneously, Figure 13 is the partial enlargement figure of Figure 12, the signal wire that definition is positioned at outside pixel region is respectively the first signal wire CLK1101 and second signal line CLK2102, and the signal wire that definition is positioned at pixel region is respectively the 3rd signal wire K1401 and the 4th signal wire K2402.
Comprise outside the pixel region of the driving circuit of this 5th embodiment: chip pin wire 201, the first signal wire CLK1101 being connected with chip pin (not shown) and second signal line CLK2102, respectively with chip pin wire (Figure 12 illustrates two chip pin wire G12 and G34) 201 the first switching arrangement 301 being connected and the 2nd switching arrangement 302.
Comprise in the pixel region of this driving circuit: crisscross sweep trace G(Figure 12 illustrates G1-G4, wherein sweep trace G1 is 501, sweep trace G2 is 502), data line S601(Figure 12 illustrates data line S1 and data line S2), and it is parallel with data line and be positioned at the 3rd signal wire K1401 and the 4th signal wire K2402 of data line both sides, by described adjacent two sweep trace G1/G2, 3rd signal wire K1, 4th signal wire K2, and the 3rd a data line S1 between signal wire K1 and the 4th signal wire K2 intersect and define four sub-pixel unit, it is defined as the first sub-pixel unit (in Figure 12 and Figure 13,1. mark is) respectively, 2nd sub-pixel unit (in Figure 12 and Figure 13,2. mark is), 3rd sub-pixel unit (in Figure 12 and Figure 13,3. mark is), and the 4th sub-pixel unit (in Figure 12 and Figure 13,4. mark is), two switching arrangements and corresponding pixel electrode it is equipped with in each sub-pixel unit, definition is positioned at the first sub-pixel unit and is provided with the third and fourth switching arrangement 303, 304 and first pixel electrode, definition is positioned at the 2nd sub-pixel unit and is provided with the 5th and the 6th switching arrangement 305, 306 and the 2nd pixel electrode, definition is positioned at the 3rd sub-pixel unit and is provided with the 7th and the 8th switching arrangement 307, 308 and the 3rd pixel electrode, definition is positioned at the 4th sub-pixel unit and is provided with the 9th and the tenth switching arrangement 309, 310 and the 4th pixel electrode.
3rd signal wire K1 and the 4th signal wire K2 is by forming memory capacitance Cst between fixed voltage and corresponding sub-pixel unit, color membrane electrode is by forming liquid crystal capacitance C between fixed voltage and corresponding sub-pixel unitL C。
The connection of this driving circuit is closed: the first grid of described first switching arrangement 301 connects chip pin wire 201, first source electrode of the first switching arrangement 301 connects the first signal wire CLK1101, and the first drain electrode of the first switching arrangement 301 connects sweep trace G1501; The second gate pole of described 2nd switching arrangement 302 is all connected same chip pin wire 201 with the first grid of the first switching arrangement 301,2nd source electrode of the 2nd switching arrangement 302 connects second signal line CLK2102,2nd drain electrode connection sweep trace G2502, sweep trace G1 and sweep trace G2 of the 2nd switching arrangement 302 is two adjacent sweep traces.
3rd grid of the 3rd switching arrangement 303 in the first sub-pixel unit connects sweep trace G1501, also namely: the 3rd grid of the 3rd switching arrangement 303 is connected same scan line with the first drain electrode of the first switching arrangement 301; 3rd source electrode of the 3rd switching arrangement 303 connects the 3rd signal wire K1401, and the 3rd drain electrode of the 3rd switching arrangement 303 connects the 4th grid of the 4th switching arrangement 304; 4th grid of the 4th switching arrangement 304 connects the 3rd drain electrode of the 3rd switching arrangement, 4th source electrode of the 4th switching arrangement 304 connects data line S1601,4th drain electrode of the 4th switching arrangement 304 connects the first pixel electrode, and the 3rd form the first memory capacitance Cst1 between signal wire K1401 and the first pixel electrode, between color membrane electrode and the first pixel electrode, form the first liquid crystal capacitance CLC2。
By above-mentioned explanation, the 4th switching arrangement 304 of the first sub-pixel unit is controlled by the 3rd switching arrangement 303.
5th grid of the 5th switching arrangement 305 in the 2nd sub-pixel unit connects sweep trace G1501, also namely: the 5th grid of the 5th switching arrangement 305 is all connected same scan line with the first drain electrode of the 3rd grid of the 3rd switching arrangement 303, the first switching arrangement 301; 5th source electrode of the 5th switching arrangement 305 connects the 4th signal wire K2402, and the 5th drain electrode of the 5th switching arrangement 305 connects the 5th grid of the 6th switching arrangement 306; 6th grid of the 6th switching arrangement 306 connects the 5th drain electrode of the 5th switching arrangement 305,6th source electrode of the 6th switching arrangement 306 connects data line S1601,6th drain electrode of the 6th switching arrangement 306 connects the 2nd pixel electrode, and between second signal line K1402 and the 2nd pixel electrode, form the 2nd memory capacitance Cst2, form the 2nd liquid crystal capacitance C between color membrane electrode and the 2nd pixel electrodeLC3. By above-mentioned explanation, the 6th switching arrangement 306 of the 2nd sub-pixel unit is controlled by the 5th switching arrangement 305.
7th grid of the 7th switching arrangement 307 in the 3rd sub-pixel unit connects sweep trace G2502, also namely: the 7th grid of the 7th switching arrangement 307 is extremely all connected same scan line with the second gate of the 2nd switching arrangement 302; 7th source electrode of the 7th switching arrangement 307 connects the 3rd signal wire K1401, and the 7th drain electrode of the 7th switching arrangement 307 connects the 8th grid of the 8th switching arrangement 308; 8th grid of the 8th switching arrangement 308 connects the 7th drain electrode of the 7th switching arrangement 307,8th source electrode of the 8th switching arrangement 308 connects data line S1601,8th drain electrode of the 8th switching arrangement 308 connects the 3rd pixel electrode, and the 3rd form the 3rd memory capacitance Cst3 between signal wire K1401 and the 3rd pixel electrode, between color membrane electrode and the 3rd pixel electrode, form the 3rd liquid crystal capacitance CLC3。
By above-mentioned explanation, the 8th switching arrangement 308 of the 3rd sub-pixel unit is controlled by the 7th switching arrangement 305.
9th grid of the 9th switching arrangement 309 in the 4th sub-pixel unit connects sweep trace G2502, also namely: the 9th grid of the 9th switching arrangement 309 is all connected same scan line with the 2nd drain electrode of the 7th grid of the 7th switching arrangement 307, the 2nd switching arrangement 302; 9th source electrode of the 9th switching arrangement 309 connects the 4th signal wire K2402, and the 9th drain electrode of the 9th switching arrangement 309 connects the tenth grid of the tenth switching arrangement 310; Tenth grid of the tenth switching arrangement 310 connects the 9th drain electrode of the 9th switching arrangement 309, tenth source electrode of the tenth switching arrangement 310 connects data line S1601, tenth drain electrode of the tenth switching arrangement 310 connects the first pixel electrode, and the 4th form the 4th memory capacitance Cst4 between signal wire K1402 and the 4th pixel electrode, between color membrane electrode and the 4th pixel electrode, form the 4th liquid crystal capacitance CLC4。
By above-mentioned explanation, the tenth switching arrangement 310 of the 4th sub-pixel unit is controlled by the 9th switching arrangement 309.
Figure 14 is the waveform diagram of driving circuit shown in Figure 13, the pixel electrode of pixel electrode charging order first sub-pixel unit, the pixel electrode of the 2nd sub-pixel unit, the pixel electrode of the 3rd sub-pixel unit and the pixel electrode of the 4th sub-pixel unit.
When, in the first half section time that chip pin wire G12 is high level Vgh, the first signal wire CLK1101 is also high level Vgh, and second signal line CLK2102 is lower level, thus signal opened by sweep trace G1 output grid line, and sweep trace G2 exports grid and closes signal.
When the 3rd signal wire K1401 before chip pin wire G12 is high level Vgh 1/4th time in for high level Vgh, now the 4th signal wire K2402 is lower level Vgl, 3rd switching arrangement 303 of the first sub-pixel unit is opened, the while of 3rd switching arrangement 303, drived control the 4th switching arrangement 304 is opened, thus is the pixel electrode charging of the first sub-pixel unit; When the 4th signal wire K2402 chip pin wire G12 be high level Vgh 1/1st to two/4th time in for high level Vgh, now the 3rd signal wire K1401 is lower level Vgl, 5th switching arrangement 305 of the 2nd sub-pixel unit is opened, the while of 5th switching arrangement 306, drived control the 6th switching arrangement 306 is opened, thus is the pixel electrode charging of the 2nd sub-pixel unit; When the 3rd signal wire K1401 chip pin wire G12 be high level Vgh 3/1sts to four/2nd time in for high level Vgh, now the 4th signal wire K2402 is lower level Vgl, 7th switching arrangement 307 of the 3rd sub-pixel unit is opened, 7th switching arrangement 307 is opened with control the 8th switching arrangement 308, thus is the pixel electrode charging of the 3rd sub-pixel unit; When the 4th signal wire K2402 after chip pin wire G12 is high level Vgh 1/4th time in for high level Vgh, now the 3rd signal wire K1401 is lower level Vgl, 9th switching arrangement 309 of the 4th sub-pixel unit is opened, the while of 9th switching arrangement 309, drived control the tenth switching arrangement 310 is opened, thus is the pixel electrode charging of the 4th sub-pixel unit.
Figure 15 is the schematic diagram of the equivalent electrical circuit of sixth embodiment of the invention liquid crystal display panel drive circuit, Figure 16 is the partial enlargement figure of Figure 15, this the 6th embodiment from above-mentioned 5th embodiment difference is: the mode of connection of the 3rd signal wire K1 and the 4th signal wire K2 and switching arrangement is different: the 3rd, 5th, 7th, 9th switching arrangement 303, 305, 307, the grid of 309 still connects corresponding sweep trace, 3rd, 5th, 7th, 9th switching arrangement 303, 305, 307, the source electrode of 309 changes connection data line S1, 3rd, 5th, 7th, 9th switching arrangement 303, 305, 307, the drain electrode of 309 changes connection the corresponding 4th, 6th, 8th, tenth switching arrangement 304, 306, 308, the source electrode of 310, the 3rd signal wire K1 that the grid of the 4th and the 8th switching arrangement 304,308 connects, the grid of the 6th and the tenth switching arrangement 306,310 connects the 4th signal wire K2, four, the source electrode of the 6th, the 8th, the tenth switching arrangement 304,306,308,310 changes the drain electrode connecting corresponding 3rd, the 5th, the 7th, the 9th switching arrangement 303,305,307,309, and the drain electrode of the 4th and the 8th switching arrangement 304,308 connects corresponding pixel electrode.
The waveform diagram of the driving circuit of this 6th embodiment is identical with the waveform diagram of above-mentioned 5th embodiment, it is all by all arranging corresponding signal wire and the driving circuit of switching arrangement composition in and pixel region outer at the pixel region of display panels, the driving circuit of design like this, gate drivers and source electrode driver number are reduced half simultaneously, so significantly reduces panel cost.
Five, above-mentioned first, second and the 3rd, the 4th embodiment are merged by the 6th embodiment, owing to having unicity between first, second and the 3rd, the 4th embodiment, therefore having unicity separately between the first to the 6th embodiment.
The present invention is by outside the pixel district of display panels and/or increase the driving circuit of the composition such as one group of anti-phase signal wire and switching arrangement in pixel region, the pulse signal produced by gate drivers is divided into two or one dividing into three or is divided into four, form two or three or four grid pulsing signals opened successively, so gate drivers and/or source electrode driver number can be reduced, so significantly reduce panel cost.
Claims (3)
1. the driving circuit of a display panels, display panels comprises the first substrate and second substrate that are oppositely arranged and the liquid crystal being folded between first substrate and second substrate, second substrate is provided with color membrane electrode, it is characterized in that: this driving circuit is positioned on first substrate, comprise outside the pixel region of described driving circuit: the chip pin wire that the first signal wire, second signal line are connected with chip pin, the first switching arrangement being connected with chip pin wire respectively and the 2nd switching arrangement, comprise in the pixel region of this driving circuit: crisscross sweep trace, data line, and it is parallel with data line and be positioned at the 3rd signal wire and the 4th signal wire of data line both sides, by adjacent two sweep traces, 3rd signal wire, 4th signal wire, and the 3rd a data line between signal wire and the 4th signal wire intersect define first to fourth four sub-pixel unit, definition is positioned at the first sub-pixel unit and is provided with the 3rd, 4th switching arrangement and the first pixel electrode, definition is positioned at the 2nd sub-pixel unit and is provided with the 5th switching arrangement, 6th switching arrangement and the 2nd pixel electrode, definition is positioned at the 3rd sub-pixel unit and is provided with the 7th switching arrangement, 8th switching arrangement and the 3rd pixel electrode, definition is positioned at the 4th sub-pixel unit and is provided with the 9th switching arrangement, tenth switching arrangement and the 4th pixel electrode, 4th switching arrangement of described first sub-pixel unit is controlled by the 3rd switching arrangement, 6th switching arrangement of described 2nd sub-pixel unit is controlled by the 5th switching arrangement, 8th switching arrangement of described 3rd sub-pixel unit is controlled by the 7th switching arrangement, tenth switching arrangement of described 4th sub-pixel unit is controlled by the 9th switching arrangement, 3rd signal wire, the 4th forms memory capacitance between signal wire and corresponding pixel electrode, color membrane electrode forms corresponding liquid crystal capacitance to corresponding pixel electrode, each switching arrangement is equipped with grid, source electrode and drain electrode, the grid of described first switching arrangement connects chip pin wire, the source electrode of the first switching arrangement connects the first signal wire, and the drain electrode of the first switching arrangement connects sweep trace, the described grid of the 2nd switching arrangement is all connected same chip pin wire with the grid of the first switching arrangement, and the source electrode of the 2nd switching arrangement connects second signal line, and the drain electrode of the 2nd switching arrangement connects sweep trace, the grid of the 3rd switching arrangement connects sweep trace, the source electrode of the 3rd switching arrangement connects the 3rd signal wire, and the drain electrode of the 3rd switching arrangement connects the grid of the 4th switching arrangement, the source electrode of the 4th switching arrangement connects data line, and the drain electrode of the 4th switching arrangement connects the first pixel electrode, the grid of the 5th switching arrangement connects sweep trace, and the 5th the grid of switching arrangement be all connected same scan line with the grid of the 3rd switching arrangement, the drain electrode of the first switching arrangement, the source electrode of the 5th switching arrangement connects the 4th signal wire, and the drain electrode of the 5th switching arrangement connects the grid of the 6th switching arrangement, the source electrode of the 6th switching arrangement connects data line, and the drain electrode of the 6th switching arrangement connects the 2nd pixel electrode, the grid of the 7th switching arrangement connects sweep trace, the source electrode of the 7th switching arrangement connects the 3rd signal wire, and the drain electrode of the 7th switching arrangement connects the grid of the 8th switching arrangement, the source electrode of the 8th switching arrangement connects data line, and the drain electrode of the 8th switching arrangement connects the 3rd pixel electrode,The grid of the 9th switching arrangement connects sweep trace, and the 9th the grid of switching arrangement be all connected same scan line with the grid of the 7th switching arrangement, the drain electrode of the 2nd switching arrangement, the sweep trace that the grid of the sweep trace that the drain electrode of the grid of the 9th switching arrangement, the grid of the 7th switching arrangement, the 2nd switching arrangement all connects and the 5th switching arrangement, the grid of the 3rd switching arrangement, the drain electrode of the first switching arrangement all connect is two articles of adjacent sweep traces; The source electrode of the 9th switching arrangement connects the 4th signal wire, and the drain electrode of the 9th switching arrangement connects the grid of the tenth switching arrangement; The source electrode of the tenth switching arrangement connects data line, and the drain electrode of the tenth switching arrangement connects the 4th pixel electrode.
2. the driving circuit of a display panels, display panels comprises the first substrate and second substrate that are oppositely arranged and the liquid crystal being folded between first substrate and second substrate, second substrate is provided with color membrane electrode, it is characterized in that: this driving circuit is positioned on first substrate, comprise outside the pixel region of described driving circuit: the chip pin wire that the first signal wire, second signal line are connected with chip pin, the first switching arrangement being connected with chip pin wire respectively and the 2nd switching arrangement, comprise in the pixel region of this driving circuit: crisscross sweep trace, data line, and it is parallel with data line and be positioned at the 3rd signal wire and the 4th signal wire of data line both sides, by adjacent two sweep traces, 3rd signal wire, 4th signal wire, and the 3rd a data line between signal wire and the 4th signal wire intersect define first to fourth four sub-pixel unit, definition is positioned at the first sub-pixel unit and is provided with the 3rd, 4th switching arrangement and the first pixel electrode, definition is positioned at the 2nd sub-pixel unit and is provided with the 5th switching arrangement, 6th switching arrangement and the 2nd pixel electrode, definition is positioned at the 3rd sub-pixel unit and is provided with the 7th switching arrangement, 8th switching arrangement and the 3rd pixel electrode, definition is positioned at the 4th sub-pixel unit and is provided with the 9th switching arrangement, tenth switching arrangement and the 4th pixel electrode, 4th switching arrangement of described first sub-pixel unit is controlled by the 3rd switching arrangement, 6th switching arrangement of described 2nd sub-pixel unit is controlled by the 5th switching arrangement, 8th switching arrangement of described 3rd sub-pixel unit is controlled by the 7th switching arrangement, tenth switching arrangement of described 4th sub-pixel unit is controlled by the 9th switching arrangement, 3rd signal wire, the 4th forms memory capacitance between signal wire and corresponding pixel electrode, color membrane electrode forms corresponding liquid crystal capacitance to corresponding pixel electrode, each switching arrangement is equipped with grid, source electrode and drain electrode, the grid of described first switching arrangement connects chip pin wire, the source electrode of the first switching arrangement connects the first signal wire, and the drain electrode of the first switching arrangement connects sweep trace, the described grid of the 2nd switching arrangement is all connected same chip pin wire with the grid of the first switching arrangement, and the source electrode of the 2nd switching arrangement connects second signal line, and the drain electrode of the 2nd switching arrangement connects sweep trace, the grid of the 3rd switching arrangement connects sweep trace, the source electrode of the 3rd switching arrangement connects data line, and the drain electrode of the 3rd switching arrangement connects the source electrode of the 4th switching arrangement, the grid of the 4th switching arrangement connects the 3rd signal wire, and the drain electrode of the 4th switching arrangement connects the first pixel electrode, the grid of the 5th switching arrangement connects sweep trace, and the 5th the grid of switching arrangement be all connected same scan line with the grid of the 3rd switching arrangement, the drain electrode of the first switching arrangement, the source electrode of the 5th switching arrangement connects data line, and the drain electrode of the 5th switching arrangement connects the source electrode of the 6th switching arrangement, the grid of the 6th switching arrangement connects the 4th signal wire, and the drain electrode of the 6th switching arrangement connects the 2nd pixel electrode, the grid of the 7th switching arrangement connects sweep trace, the source electrode of the 7th switching arrangement connects data line, and the drain electrode of the 7th switching arrangement connects the source electrode of the 8th switching arrangement, the grid of the 8th switching arrangement connects the 3rd signal wire, and the drain electrode of the 8th switching arrangement connects the 3rd pixel electrode, the grid of the 9th switching arrangement connects sweep trace, and the 9th the grid of switching arrangement be all connected same scan line with the grid of the 7th switching arrangement, the drain electrode of the 2nd switching arrangement, the sweep trace that the grid of the sweep trace that the drain electrode of the grid of the 9th switching arrangement, the grid of the 7th switching arrangement, the 2nd switching arrangement all connects and the 5th switching arrangement, the grid of the 3rd switching arrangement, the drain electrode of the first switching arrangement all connect is two articles of adjacent sweep traces, the source electrode of the 9th switching arrangement connects data line, and the drain electrode of the 9th switching arrangement connects the source electrode of the tenth switching arrangement, the grid of the tenth switching arrangement connects data line, and the drain electrode of the tenth switching arrangement connects the 4th pixel electrode.
3. the drive waveform method of driving circuit according to claim 1 or 2, it is characterized in that: when in the first half section time that chip pin wire is high level, first signal wire is also high level, second signal line is lower level, the sweep trace input grid being all connected with the grid of the 5th switching arrangement, the grid of the 3rd switching arrangement, the drain electrode of the first switching arrangement opens signal, and the sweep trace input grid being all connected with the drain electrode of the grid of the grid of the 9th switching arrangement, the 7th switching arrangement, the 2nd switching arrangement closes signal;When the 3rd signal wire is high level within the time that chip pin wire is before high level 1/4th, now the 4th signal wire is lower level, 3rd switching arrangement control the 4th switching arrangement of the first sub-pixel unit is opened, thus is the pixel electrode charging of the first sub-pixel unit; When the 4th signal wire chip pin wire be high level 1/1st to two/4th time in for high level, now the 3rd signal wire is lower level, 5th switching arrangement control the 6th switching arrangement of the 2nd sub-pixel unit is opened, thus is the pixel electrode charging of the 2nd sub-pixel unit; When the 3rd signal wire chip pin wire be high level 3/1sts to four/2nd time in for high level, now the 4th signal wire is lower level, 7th switching arrangement control the 8th switching arrangement of the 3rd sub-pixel unit is opened, thus is the pixel electrode charging of the 3rd sub-pixel unit; When the 4th signal wire is high level within the time that chip pin wire is after high level 1/4th, now the 3rd signal wire is lower level, 9th switching arrangement control the tenth switching arrangement of the 4th sub-pixel unit is opened, thus is the pixel electrode charging of the 4th sub-pixel unit; When, in time second half section that chip pin wire is high level, the first signal wire is lower level, second signal line is high level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310322194.2A CN103426415B (en) | 2013-07-29 | 2013-07-29 | The driving circuit of a kind of display panels and drive waveform method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310322194.2A CN103426415B (en) | 2013-07-29 | 2013-07-29 | The driving circuit of a kind of display panels and drive waveform method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103426415A CN103426415A (en) | 2013-12-04 |
| CN103426415B true CN103426415B (en) | 2016-06-15 |
Family
ID=49651063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310322194.2A Active CN103426415B (en) | 2013-07-29 | 2013-07-29 | The driving circuit of a kind of display panels and drive waveform method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103426415B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104217694A (en) * | 2014-09-04 | 2014-12-17 | 深圳市华星光电技术有限公司 | Scanning driving circuit and display panel |
| US20160203801A1 (en) * | 2015-01-08 | 2016-07-14 | Pixtronix, Inc. | Low capacitance display address selector architecture |
| CN104700802B (en) * | 2015-03-25 | 2018-01-12 | 南京中电熊猫液晶显示科技有限公司 | A kind of drive circuit of liquid crystal panel |
| CN104977763B (en) * | 2015-06-18 | 2018-07-17 | 深圳市华星光电技术有限公司 | A kind of driving circuit and its driving method, liquid crystal display |
| KR102542853B1 (en) * | 2016-04-25 | 2023-06-14 | 삼성전자주식회사 | Led display module, display apparatus and controlling method thereof |
| CN109599405B (en) | 2019-01-02 | 2021-04-06 | 京东方科技集团股份有限公司 | Array substrate, display panel, display device and related method |
| CN111435200A (en) * | 2019-01-11 | 2020-07-21 | 惠科股份有限公司 | Liquid crystal display device, liquid crystal display panel and driving method thereof |
| TWI738281B (en) * | 2020-04-01 | 2021-09-01 | 友達光電股份有限公司 | Display panel |
| CN111402819B (en) * | 2020-04-26 | 2021-09-21 | 华南师范大学 | Electrowetting display driving system, method and apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236737A (en) * | 2008-02-29 | 2008-08-06 | 上海广电光电子有限公司 | Circuit for reducing gate driver circuit quantity and LCD device |
| CN202075968U (en) * | 2011-06-02 | 2011-12-14 | 北京京东方光电科技有限公司 | LCD module |
| CN102446498A (en) * | 2010-10-12 | 2012-05-09 | 北京京东方光电科技有限公司 | LCD (liquid crystal display) driving device and driving method |
| CN103021359A (en) * | 2012-12-10 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and driving control method and display device thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101048700B1 (en) * | 2004-04-30 | 2011-07-12 | 엘지디스플레이 주식회사 | LCD and its driving method |
-
2013
- 2013-07-29 CN CN201310322194.2A patent/CN103426415B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101236737A (en) * | 2008-02-29 | 2008-08-06 | 上海广电光电子有限公司 | Circuit for reducing gate driver circuit quantity and LCD device |
| CN102446498A (en) * | 2010-10-12 | 2012-05-09 | 北京京东方光电科技有限公司 | LCD (liquid crystal display) driving device and driving method |
| CN202075968U (en) * | 2011-06-02 | 2011-12-14 | 北京京东方光电科技有限公司 | LCD module |
| CN103021359A (en) * | 2012-12-10 | 2013-04-03 | 京东方科技集团股份有限公司 | Array substrate and driving control method and display device thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103426415A (en) | 2013-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103426415B (en) | The driving circuit of a kind of display panels and drive waveform method | |
| CN103730094B (en) | Goa circuit structure | |
| CN105469763B (en) | Drive element of the grid, gate driving circuit and display device | |
| CN103744206B (en) | A kind of array base palte drive circuit, array base palte and corresponding liquid crystal display | |
| CN102831867B (en) | Grid driving unit circuit, grid driving circuit of grid driving unit circuit, and display | |
| CN102460553B (en) | Display driving circuit, display device and display driving method | |
| CN101601081B (en) | Liquid crystal display device, and its driving method | |
| CN105405406A (en) | Gate drive circuit and display using same | |
| CN103761954B (en) | Display floater and gate drivers | |
| CN101523474B (en) | Display device | |
| CN105335003B (en) | Touch-control display panel and its touch-control circuit | |
| CN105405424B (en) | Pixel circuit and its driving method, driving circuit, display device | |
| TW200947026A (en) | Pixel circuit and driving method thereof | |
| CN102778798B (en) | Liquid crystal display panel and display driving method | |
| CN105632441A (en) | Gate driving circuit | |
| CN104391411A (en) | LCD panel | |
| CN103454823B (en) | A kind of array base palte and display panels | |
| CN110390903A (en) | Gate driving circuit and display device | |
| CN106233367B (en) | Active-matrix substrate and the display device for having it | |
| CN101178879B (en) | Display panel of LCD device and drive method thereof | |
| CN102393587A (en) | Signal wiring structure in GOA (gate driver on array) circuit of liquid crystal display | |
| CN105390086A (en) | GOA (gate driver on array) circuit and displayer using same | |
| CN102081270B (en) | Liquid crystal display device and driving method thereof | |
| CN108877720A (en) | Gate driving circuit, display device and driving method | |
| CN104952420A (en) | Multiplexer, as well as data driving circuit and liquid crystal display panel applying multiplexer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |