TWI738281B - Display panel - Google Patents

Abstract

A display panel has a display region and non-display region surrounding the display region. The display panel includes a plurality of pixel unit, a plurality of data lines, a plurality of gate lines, a gate driver circuit and a plurality of first signal lines. The plurality of pixel units is disposed in the display region and arranged as a pixel array. Each pixel unit includes a first sub-pixel, a second sub-pixel and a third sub-pixel and the first sub-pixel, the second sub-pixel and the third sub-pixel arrange along a first direction. The plurality of data lines includes a first data line, a second data line and a third data line. The plurality of data lines are electrically connected with the plurality of pixel unit. The first data line is electrically connected with the first sub-pixel. The second data line is electrically connected with the second sub-pixel. The third data line is electrically connected with the third sub-pixel. The plurality of gate lines includes a first gate line. The plurality of gate lines are electrically connected with the plurality of pixel unit. The first gate line is electrically connected with the first sub-pixel, the second sub-pixel and the third sub-pixel. The gate driver circuit includes a plurality of gate driver modules. One of the plurality of first signal lines is between the first sub-pixel and the second sub-pixel. The first data line and the first signal line are on the two sides of the first sub-pixel. The second data line and the first signal line are on the two sides of the second sub-pixel.

Description

Display panel

The present invention relates to a display panel provided with a gate driving circuit in the display area to increase the area of the display area.

Generally speaking, the gate drive circuit is arranged on the borders on the left and right sides of the display panel. The gate drive circuit occupies a large area, and it is difficult to meet the requirement of a narrow border, resulting in a reduction in the area of the display area. How to solve the aforementioned crux has become Problems to be solved.

In summary, the inventor of the present invention thought about and designed a display panel with a view to improving the lack of conventional technology, thereby enhancing the application and utilization in the industry.

In view of the above-mentioned conventional problems, the purpose of the present invention is to provide a display panel to solve the problems faced by the conventional technology.

Based on the above objective, the present invention provides a display panel having a display area and a non-display area surrounding the display area, which includes a plurality of pixel units, a plurality of data lines, a plurality of gate lines, a gate driving circuit, and a plurality of A signal line. A plurality of pixel units are arranged in the display area and arranged in a pixel array. Each pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel and the second sub-pixel The pixels and the third sub-pixels are arranged in a row along the first direction, respectively. Multiple data lines include The first data line, the second data line, and the third data line, and the data lines are respectively electrically connected to the pixel units, wherein the first data line is electrically connected to the first sub-pixel, and the second data line is electrically connected to the first sub-pixel. The data line is electrically connected to the second sub-pixel, and the third data line is electrically connected to the third sub-pixel. The plurality of gate lines include a first gate line, and the gate lines are electrically connected to the pixel units, respectively, and the first gate line is electrically connected to the first sub-pixel and the second sub-pixel, respectively. Sub-pixel and third sub-pixel. The gate drive circuit is arranged in the display area, and the gate drive circuit includes a plurality of gate drive circuit modules. One of the plurality of first signal lines is located between the first sub-pixel and the second sub-pixel, and the first data line and the first signal line are respectively located on opposite sides of the first sub-pixel, the first signal line and The second data lines are also located on opposite sides of the second sub-pixel.

In the embodiment of the present invention, the first signal lines and each data line extend along the second direction, and the first direction and the second direction intersect each other.

In the embodiment of the present invention, the pixel unit further includes a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel. The fourth, fifth, and sixth sub-pixels are along It is arranged in the first direction to form two adjacent rows with the first sub-pixel, the second sub-pixel, and the third sub-pixel. The first data line is electrically connected to the fourth sub-pixel, and the second data line is electrically connected For the fifth sub-pixel, the plurality of gate lines also include the next-level gate line, which is electrically connected to the fourth, fifth, and sixth sub-pixels, respectively, the first The data line and the first signal line are respectively located on opposite sides of the fourth sub-pixel, and the first signal line and the second data line are also located on opposite sides of the fifth sub-pixel.

In an embodiment of the present invention, the gate driving circuit further includes a plurality of first signal traces and a plurality of second signal traces, the plurality of first signal traces extend along the first direction, and the plurality of second signal traces The line extends along the second direction, and the first direction and the second direction intersect each other.

In an embodiment of the present invention, each gate drive circuit module includes a plurality of transistors and resistors, and the plurality of transistors respectively pass through at least one of the plurality of first signal traces and/or at least one of the plurality of second signals The wires are routed and electrically connected to the plurality of first signal wires.

In the embodiment of the present invention, the plurality of first signal lines include a first clock line, a second clock line, a reset signal line, a first high voltage line, a second high voltage line, and a low voltage line, and a plurality of The gate line includes the first two-stage gate line, the first three-stage gate line, and the last three-stage gate line.

In the embodiment of the present invention, the gate drive circuit module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, The eighth transistor, the ninth transistor, the tenth transistor, and the eleventh transistor.

The first transistor has a first end, a second end and a control end. The first end of the first transistor is connected to the first high voltage line, and the control end is connected to the first two-stage gate line or the first three-stage gate line.

The second transistor has a first end, a second end, and a control end. The first end of the second transistor is connected to the second end of the first transistor, and the second end of the second transistor is connected to the low voltage line. The control terminal of the crystal is connected to the rear three-stage gate line.

The third transistor has a first end, a second end and a control end. The control end of the third transistor is connected to the first end of the second transistor, and the second end of the third transistor is electrically connected to the low voltage line.

The fourth transistor has a first end, a second end and a control end. The first end of the fourth transistor is electrically connected to the second high voltage line, the control end of the fourth transistor is connected to the first clock line, and the fourth transistor is electrically connected to the first clock line. The second end of the crystal is connected to the first end of the third transistor.

The fifth transistor has a first end, a second end and a control end. The first end of the fifth transistor is connected to the reset signal line, and the control end of the fifth transistor is connected to the first end of the fifth transistor. The second end of the transistor is connected to the first end of the third transistor.

The sixth transistor has a first end, a second end and a control end. The control end of the sixth transistor is connected to the second end of the fifth transistor, and the second end of the sixth transistor is electrically connected to the low voltage line.

The seventh transistor has a first end, a second end and a control end, and the first end of the seventh transistor is connected to the second clock line.

The eighth transistor has a first end, a second end and a control end. The control end of the eighth transistor is connected to the control end of the sixth transistor. The second end of the eighth transistor is electrically connected to the low voltage line. The first end of the crystal is connected to the first gate line.

The ninth transistor has a first end, a second end and a control end. The second end of the ninth transistor is connected to the control end of the seventh transistor, and the first end of the ninth transistor is connected to the control end of the third transistor. The control terminal of the ninth transistor is connected to the second high voltage line.

The tenth transistor has a first end, a second end and a control end. The first end of the tenth transistor is connected to the first end of the seventh transistor, and the second end of the tenth transistor is connected to the first end of the eighth transistor. The control terminal of the tenth transistor is connected to the control terminal of the seventh transistor.

The eleventh transistor has a first end, a second end and a control end. The first end of the eleventh transistor is connected to the first end of the sixth transistor, and the second end of the eleventh transistor is connected to the eighth transistor. The first terminal of the eleventh transistor and the second terminal of the eleventh transistor are connected to the control terminal.

In the embodiment of the present invention, the resistors are arranged at the second end of the fourth transistor and the first end of the third transistor.

In the embodiment of the present invention, the material of the resistor is the same as the material of the semiconductor layer of the fourth transistor or the third transistor.

In the embodiment of the present invention, the first transistor, the seventh transistor, the tenth transistor, and the eleventh transistor are arranged along the first direction, so that they are all arranged in the same row, and the second transistor and the third transistor are arranged in the same row. The crystal and the fifth transistor are arranged along the first direction, so that they are all arranged in the same row, and the fourth, sixth, and eighth transistors are arranged along the first direction, so that they are all arranged in the other Same column.

In the embodiment of the present invention, the seventh transistor, the tenth transistor, and the eleventh transistor are arranged along the first direction so that they are all arranged in the same row, and the second transistor, the third transistor, and the fifth transistor are arranged in the same row. The crystals are arranged along the first direction so that they are all arranged in another same row, and the fourth transistor, the sixth transistor and the eighth transistor are arranged along the first direction so that they are all arranged in another same row.

In the embodiment of the present invention, the first high voltage line is located between the first clock line and the low voltage line, the reset signal line and the second high voltage line are located on opposite sides of the second clock line, and the reset signal The wire is located between the tenth transistor and the eleventh transistor.

In the embodiment of the present invention, each gate driving circuit module includes a plurality of transistors, and the transistors are respectively disposed between the first sub-pixel and the second sub-pixel.

In the embodiment of the present invention, the first transistor and the second transistor are respectively arranged along the second direction, the fifth transistor and the eleventh transistor are respectively arranged along the second direction, and the eighth transistor and the tenth transistor are respectively arranged along the second direction. The transistors are respectively arranged along the second direction.

As mentioned above, in the display panel of the present invention, the gate driving circuit is located in the display area, which meets the requirement of a narrow frame and increases the area of the display area, thereby increasing the resolution of the picture.

1: display panel

10: Pixel array

CLK: second clock line

DR: display area

Data(n-1): data line

Data(n): the first data line

Data(n+1): The second data line

Data(n+2): The third data line

D1~D11: second end

DR_1: First direction

DR_2: second direction

G1~G11: control terminal

GC: Gate drive circuit module

Gata(n): the first gate line

Gate(n-1): The previous gate line

Gate(n-2): The first two gate lines

Gate(n-3): The first three gate lines

Gate(n+1): The next level of gate line

Gate(n+2): The second second gate line

Gate(n+3): the last three gate lines

Gate(n+4): the last four gate lines

M1: The first transistor

M2: second transistor

M3: third transistor

M4: The fourth transistor

M5: fifth transistor

M6: sixth transistor

M7: seventh transistor

M8: Eighth Transistor

M9: Ninth Transistor

M10: Tenth Transistor

M11: The eleventh transistor

NDR: non-display area

PU: pixel unit

P1: The first sub-pixel

P2: The second sub-pixel

P3: The third sub-pixel

P4: Fourth sub-pixel

P5: Fifth sub-pixel

P6: The sixth sub-pixel

R: resistance

RST: reset signal line

S1~S11: the first end

VGH1: The first high voltage line

VGH2: The second high voltage line

VGL: Low voltage line

XCLK: the first clock line

Figure 1 is a schematic diagram of the display panel of the present invention.

FIG. 2 is a layout diagram of the pixel array of the first embodiment of the display panel of the present invention.

FIG. 3 is a layout diagram of the pixel array of the second embodiment of the display panel of the present invention.

FIG. 4 is a layout diagram of the pixel array of the third embodiment of the display panel of the present invention.

FIG. 5A is a layout diagram of the first embodiment of the gate drive circuit module of the display panel of the present invention.

FIG. 5B is a circuit diagram of the first embodiment of the gate drive circuit module of the display panel of the present invention.

FIG. 6A is a layout diagram of the second embodiment of the gate drive circuit module of the display panel of the present invention.

FIG. 6B is a circuit diagram of the second embodiment of the gate drive circuit module of the display panel of the present invention.

The advantages, features, and technical methods of the present invention will be described in more detail with reference to exemplary embodiments and the accompanying drawings to make it easier to understand, and the present invention can be implemented in different forms, so it should not be understood to be limited to what is here. The stated embodiments, on the contrary, for those with ordinary knowledge in the technical field, the provided embodiments will make this disclosure more thorough, comprehensive and complete to convey the meaning of the present invention Scope, and the present invention will only be defined by the appended patent scope.

It should be understood that although the terms "first", "second", etc. may be used in the present invention to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts Should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Therefore, the "first element", "first part", "first area", "first layer" and/or "first part" discussed below can be referred to as "second element", "second part" , "Second Area", "Second Layer" and/or "Second Part" without departing from the spirit and teachings of the present invention.

In addition, the terms "including" and/or "including" refer to the existence of the features, regions, wholes, steps, operations, elements, and/or components, but do not exclude one or more other features, regions, wholes, steps, operations , The presence or addition of elements, components, and/or combinations thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present invention have the same meanings as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having definitions consistent with their meanings in the context of related technologies and the present invention, and will not be interpreted as idealized or overly formal Unless explicitly defined as such in this article.

Please refer to Figure 1, which is a schematic diagram of the display panel of the present invention. As shown in FIG. 1, the display panel 1 of the present invention has a display area DR and a non-display area NDR surrounding the display area DR. For example, if the cross-sectional shape of the display panel 1 of the present invention is rectangular, the non-display area NDR can be located on two sides, three sides, or four sides of the display area DR; if the cross-sectional shape of the display panel 1 of the present invention is In a circular shape, the non-display area NDR may be located on the peripheral side of the display area DR. According to the cross-sectional shape of the display panel 1, the configuration of the display area DR and the non-display area NDR is adjusted accordingly, which is not limited to the scope of the present invention.

Please refer to FIG. 2, which is a layout diagram of the pixel array of the first embodiment of the display panel of the present invention. As shown in Figure 2, the display panel 1 of the present invention includes a plurality of pixel units PU, a plurality of data lines Data(n-1)~Data(n+3), and a plurality of gate lines Gate(n) ~Gate(n+1), gate drive circuit and a plurality of first signal lines S1. A plurality of pixel units PU are arranged in the display area and arranged as a pixel array 10. Each pixel unit includes a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3, and the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are arranged in a row along the first direction DR_1, respectively. The plural data lines Data(n-1)~Data(n+3) include the first data line Data(n), the second data line Data(n+1) and the third data line Data(n+2), and These data lines Data(n-1)~Data(n+3) respectively Are electrically connected to the pixel units PU, wherein the first data line Data(n) is electrically connected to the first sub-pixel P1, and the second data line Data(n+1) is electrically connected to the second sub-picture For pixel P2, the third data line Data(n+2) is electrically connected to the third sub-pixel P3. The gate lines Gata(n)~Gate(n+1) include the first gate line Gata(n), and the gate lines Gata(n)~Gate(n+1) are electrically connected to In the pixel units PU, the first gate line Gate(n) is electrically connected to the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3, respectively. The gate drive circuit is arranged in the display area DR, and the gate drive circuit includes a plurality of gate drive circuit modules GC (as shown in Figures 5A to 6B). The gate drive circuit modules GC will be described in detail later describe. One of the plurality of first signal lines S1 is located between the first sub-pixel P1 and the second sub-pixel P2, and the first data line Data(n) and the first signal line S1 are respectively located in the first sub-pixel P1 On opposite sides, the first signal line S1 and the second data line Data(n+1) are also located on opposite sides of the second sub-pixel P2.

Among them, the number of pixel units PU, data lines Data(n-1)~Data(n+3), and gate lines Gate(n)~Gate(n+1) are based on the number of display panel 1. The actual requirements are subject to change, and are not limited to the scope of the present invention. The materials of the plurality of data lines Data(n-1)~Data(n+3) and the plurality of gate lines Gate(n)~Gate(n+1) may include, for example, indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), beryllium Gold (AuBe), germanium beryllide (BeGe), nickel (Ni), lead tin (PbSn), chromium (Cr), gold zinc (AuZn), titanium (Ti), tungsten (W) and titanium tungsten (TiW) and other materials.

For example, the first direction DR_1 is the column direction, the second direction DR_2 is the row direction, the first direction DR_1 and the second direction DR_2 intersect and are perpendicular to each other; or the first direction DR_1 and the second direction DR_2 intersect but are not perpendicular to each other , But not limited to this. Therefore, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be arranged along the first direction DR_1 (that is, the row direction), and plural pieces of data The lines Data(n-1)~Data(n+3) and the plurality of first signal lines S1 extend along the second direction DR_2 (that is, the row direction), and the plurality of gate lines Gata(n)~Gate(n+1 ) Extends along the first direction DR_1 (that is, the column direction).

Please refer to FIG. 3, which is a layout diagram of the pixel array of the second embodiment of the display panel of the present invention. As shown in Figure 3, the difference between the second embodiment of the present invention and the first embodiment is that the first signal line S1 is located between the second data line Data(n+1) and the third data line Data(n+2) The second data line Data(n+1) and the first signal line S1 are respectively located on opposite sides of the second sub-pixel P2, and the first signal line S1 and the third data line Data(n+2) are also respectively located They are located on opposite sides of the third sub-pixel P3, and the description of other same elements will not repeat the details here.

Please refer to FIG. 4, which is a configuration diagram of the pixel array of the third embodiment of the display panel of the present invention. In this embodiment, the configuration of the components with the same component symbols is similar to that described above, and the similarities are not repeated here.

As shown in Figure 4, the difference between the third embodiment of the present invention and the first embodiment is that the pixel unit PU further includes a fourth sub-pixel P4, a fifth sub-pixel P5, and a sixth sub-pixel P6. The four sub-pixels P4, the fifth sub-pixel P5, and the sixth sub-pixel P6 are arranged along the first direction DR_1 to form a phase with the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3. Two adjacent rows, the second data line Data(n+1) is electrically connected to the fourth sub-pixel P4, the third data line Data(n+2) is electrically connected to the fifth sub-pixel P5, and a plurality of data lines Data(n-1)~Data(n+3) also includes a fourth data line Data(n+3), the fourth data line Data(n+3) is electrically connected to the sixth sub-pixel P6, and a plurality of gates The pole lines Gate(n)~Gate(n+1) also include the next-level gate line Gata(n+1), and the next-level gate line Gata(n+1) is electrically connected to the fourth sub-pixels P4, The fifth sub-pixel P5 and the sixth sub-pixel P6, the first data line Data(n) and the first signal line S1 are respectively located on opposite sides of the fourth sub-pixel P4, the first signal line S1 and the second data The line Data(n+1) is also located in the fifth sub On opposite sides of the pixel P5, the second data line Data(n+1) and the third data line Data(n+2) are also located on opposite sides of the sixth sub-pixel P6.

Please refer to Figures 5A and 5B, which are the layout diagrams of the first embodiment of the gate drive circuit module of the display panel of the present invention and the first embodiment of the gate drive circuit module of the display panel of the present invention The circuit diagram. It should be mentioned that the gate drive circuit includes a plurality of first signal traces CR1 and a plurality of second signal traces CR2, the plurality of first signal traces CR1 extend along the first direction DR_1, and the plurality of second signal traces The trace CR2 extends along the second direction D2, and the plurality of second signal traces CR2 can be the common mode voltage line Vcom or the wiring of the gate drive circuit, and it can also be other types of voltage lines or signal lines without limitation. Within the scope of the present invention. The plurality of first signal lines S1 includes a first clock line XCLK, a second clock line CLK, a reset signal line RST, a first high voltage line VGH1, a second high voltage line VGH2, and a low voltage line VGL. The pole lines Gate(n)~Gate(n+1) also include the previous level gate line Gate(n-1), the previous level two gate line Gate(n-2), and the first three level gate line Gate(n- 3) The last two-stage gate line Gate(n+2), the last three-stage gate line Gate(n+3), and the last four-stage gate line Gate(n+4).

As shown in Figures 5A and 5B, the gate drive circuit module GC includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a Six transistors M6, seventh transistor M7, eighth transistor M8, ninth transistor M9, tenth transistor M10, eleventh transistor M11 and resistor R, first transistor M1 to eleventh transistor M11 is respectively electrically connected to the plurality of first signal lines S1 through at least one of the plurality of first signal traces CR1 and/or at least one of the plurality of second signal traces CR2, and the first transistors M1 to The eleven transistors M11 are respectively arranged between the first sub-pixel P1 and the second sub-pixel P2.

Here, the detailed configuration of the first transistor M1 to the eleventh transistor M11 is described as follows: the first transistor M1 has a first terminal S1, a second terminal D1 and a control terminal G1, and the first terminal of the first transistor M1 S1 is connected to the first high voltage line VGH1, and the control terminal G1 is connected to the previous two-stage gate line Gate (n-2).

The second transistor M2 has a first terminal S2, a second terminal D2, and a control terminal G2. The first terminal S2 of the second transistor M2 is connected to the second terminal D1 of the first transistor M1, and the second terminal S2 of the second transistor M2 The terminal D2 is connected to the low-voltage line VGL, and the control terminal G2 of the second transistor M2 is connected to the third-stage gate line Gate(n+3).

The third transistor M3 has a first terminal S3, a second terminal D3 and a control terminal G3. The control terminal G3 of the third transistor M3 is connected to the first terminal S2 of the second transistor M2, and the second terminal of the third transistor M3 D3 is electrically connected to the low voltage line VGL.

The fourth transistor M4 has a first terminal S4, a second terminal D4 and a control terminal G4. The first terminal S4 of the fourth transistor M4 is electrically connected to the second high voltage line VGH2, and the control terminal G4 of the fourth transistor M4 is connected The first clock line XCLK, the second end D4 of the fourth transistor M4 is connected to the first end S3 of the third transistor M3, and the resistor R is set between the second end D4 of the fourth transistor M4 and the third transistor M3 The material of the first terminal S3 and the resistor R is the same as the material of the semiconductor layer of the fourth transistor M4 or the third transistor M3. The material of the semiconductor layer may include polysilicon, which may also be other preferable materials, and is not limited to this The enumerated range of the invention.

The fifth transistor M5 has a first terminal S5, a second terminal D5, and a control terminal G5. The first terminal S5 of the fifth transistor M5 is connected to the reset signal line RST, and the control terminal G5 of the fifth transistor M5 is connected to the fifth The first terminal S5 of the transistor M5 and the second terminal D5 of the fifth transistor M5 are connected to the first terminal S3 of the third transistor M3.

The sixth transistor M6 has a first terminal S6, a second terminal D6, and a control terminal G6. The control terminal G6 of the sixth transistor M6 is connected to the second terminal D5 of the fifth transistor M5, and the second terminal of the sixth transistor M6 D6 is electrically connected to the low voltage line VGL.

The seventh transistor M7 has a first terminal S7, a second terminal D7, and a control terminal G7. The first terminal S7 of the seventh transistor M7 is connected to the second clock line CLK; in addition, the seventh transistor M7 has a relatively large volume. Considering that the large volume will affect the aperture ratio of the pixel, it is represented by two small-volume seventh transistors M7 in Figure 5A.

The eighth transistor M8 has a first terminal S8, a second terminal D8 and a control terminal G8. The control terminal G8 of the eighth transistor M8 is connected to the control terminal G6 of the sixth transistor M6, and the second terminal D8 of the eighth transistor M8 The low voltage line VGL is electrically connected, and the first terminal S8 of the eighth transistor M8 is connected to the first gate line G(n).

The ninth transistor M9 has a first terminal S9, a second terminal D9 and a control terminal G9. The second terminal D9 of the ninth transistor M9 is connected to the control terminal G7 of the seventh transistor M7, and the first terminal of the ninth transistor M9 S9 is connected to the control terminal G3 of the third transistor M3, the second terminal D1 of the first transistor M1, and the first terminal S1 of the second transistor M2, and the control terminal of the ninth transistor is connected to the second high voltage line.

The tenth transistor M10 has a first terminal S10, a second terminal D10, and a control terminal G10. The first terminal S10 of the tenth transistor M10 is connected to the first terminal S7 of the seventh transistor M7, and the second terminal S7 of the tenth transistor M10 Terminal D10 is connected to the first terminal S8 of the eighth transistor M8, the first terminal S10 and the second terminal D10 of the tenth transistor M10 are connected to each other, and the control terminal G10 of the tenth transistor M10 is connected to the control terminal of the seventh transistor M7 G7 and the second terminal D9 of the ninth transistor M9.

The eleventh transistor M11 has a first terminal S11, a second terminal D11, and a control terminal G11. The first terminal S11 of the eleventh transistor M11 is connected to the first terminal S6 of the sixth transistor M6. The second terminal D11 of the body M11 is connected to the first terminal S8 of the eighth transistor M8, the second terminal D11 of the eleventh transistor M11 is connected to the control terminal G11, and the second terminal D11 and the tenth terminal of the eleventh transistor M11 are connected. The second end D10 of the transistor M10 and the first end S8 of the eighth transistor M8 are connected to each other.

Among them, the first transistor M1, the seventh transistor M7, the tenth transistor M10, and the eleventh transistor M11 are arranged along the first direction DR_1 so that they are all arranged in the same column; the second transistor M2, the third transistor The transistor M3 and the fifth transistor M5 are arranged along the first direction DR_1 so that they are all arranged in another same row; the fourth transistor M4, the sixth transistor M6 and the eighth transistor M8 are arranged along the first direction DR_1, So that they are all arranged in another same row. The first transistor M1 and the second transistor M2 are respectively arranged along the second direction DR_2, so that they are all arranged in the same line; the fifth transistor M5 and the eleventh transistor M11 are respectively arranged along the second direction DR_2, so that they They are all arranged in the same line; the eighth transistor M8 and the tenth transistor M10 are respectively arranged along the second direction DR_2, so that they are all arranged in the same line. The first high voltage line VGH1 is located between the first clock line XCLK and the low voltage line VGL, the reset signal line RST and the second high voltage line VGH2 are located on opposite sides of the second clock line CLK, and the reset signal line RST Located between the tenth transistor M10 and the eleventh transistor M11.

Please refer to Figures 6A and 6B, which are the layout diagrams of the second embodiment of the gate drive circuit module of the display panel of the present invention and the second embodiment of the gate drive circuit module of the display panel of the present invention The circuit diagram. In this embodiment, the configuration of the components with the same component symbols is similar to that described above, and the similarities are not repeated here.

As shown in Figure 6A and Figure 6B, the difference between the second embodiment of the gate drive circuit of the present invention and the first embodiment: (1) The control terminal G1 of the first transistor M1 is connected to the first three-stage gate lines Gate(n-3). (2) The seventh transistor M7, the tenth transistor M10, and the eleventh transistor M11 are arranged along the first direction DR_1 so that they are all arranged in the same row; the second transistor M2, the third transistor M3, and the fifth transistor Transistor M5 edge The fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 are arranged along the first direction DR_1 so that they are all arranged in another same row, so that they are all arranged in another same row.

As mentioned above, in the display panel of the present invention, the gate driving circuit GC is located in the display area DR, which meets the requirement of a narrow frame and increases the area of the display area DR, thereby increasing the resolution of the picture.

The above descriptions are merely illustrative and not restrictive. Any equivalent modifications or alterations that do not depart from the spirit and scope of the present invention should be included in the scope of the appended patent application.

Data(n-1): data line

Data(n): the first data line

Data(n+1): The second data line

Data(n+2): The third data line

DR_1: First direction

DR_2: second direction

Gata(n): the first gate line

Gate(n+1): The next level of gate line

PU: pixel unit

P1: The first sub-pixel

P2: The second sub-pixel

P3: The third sub-pixel

Claims (12)

A display panel has a display area and a non-display area surrounding the display area. The display panel includes a plurality of pixel units arranged in the display area and arranged in a pixel array. Each pixel unit includes a A first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged in a row along a first direction, respectively ; A plurality of data lines, including a first data line, a second data line and a third data line, and the data lines are electrically connected to the pixel units, wherein the first data line Is electrically connected to the first sub-pixel, the second data line is electrically connected to the second sub-pixel, and the third data line is electrically connected to the third sub-pixel; a plurality of gate lines include one The first gate line, and the gate lines are electrically connected to the pixel units, respectively, wherein the first gate line is electrically connected to the first sub-pixel and the second sub-pixel, respectively And the third sub-pixel; a gate drive circuit arranged in the display area, and the gate drive circuit includes a plurality of gate drive circuit modules; and a plurality of first signal lines, one of the first A signal line is located between the first sub-pixel and a second sub-pixel, and the first data line and the first signal line are respectively located on opposite sides of the first sub-pixel, the first signal line The second data line and the second data line are also located on opposite sides of the second sub-pixel; wherein the gate driving circuit further includes a plurality of first signal traces and a plurality of second signal traces, the plurality of first signal traces The traces extend along the first direction, the plurality of second signal traces extend along a second direction, the first direction and the second direction intersect each other, and each of the gate drive circuit modules includes a plurality of electrical circuits. Crystal and a resistor, The plurality of transistors are respectively electrically connected to the plurality of first signal lines via at least one of the plurality of first signal traces and/or at least one of the plurality of second signal traces. The display panel according to claim 1, wherein the first signal lines and each of the data lines extend along the second direction. The display panel according to claim 1, wherein the pixel unit further includes a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel, and the fourth sub-pixel and the fifth sub-pixel The pixel and the sixth sub-pixel are arranged along the first direction to form two adjacent rows with the first sub-pixel, the second sub-pixel, and the third sub-pixel, wherein the second data line is electrically connected Is electrically connected to the fourth sub-pixel, the third data line is electrically connected to the fifth sub-pixel, the plurality of gate lines also include a second-level gate line, and the second-level gate lines are electrically connected to each other. Connected to the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel, wherein the first data line and the first signal line are respectively located on opposite sides of the fourth sub-pixel, the The first signal line and the second data line are also located on opposite sides of the fifth sub-pixel. The display panel according to claim 1, wherein the plurality of first signal lines include a first clock line, a second clock line, a reset signal line, a first high voltage line, and a second high voltage line. A voltage line and a low-voltage line. The plurality of gate lines include a front two-stage gate line, a first three-stage gate line, and a back three-stage gate line. The display panel of claim 4, wherein the gate drive circuit module includes: a first transistor having a first terminal, a second terminal, and a control terminal, the first transistor of the first transistor Terminal is connected to the first high-voltage line, and the control terminal is connected to the first two-stage gate line or the first three-stage gate line; A second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is connected to the second terminal of the first transistor. The second terminal of the second transistor The second end is connected to the low voltage line, the control end of the second transistor is connected to the third-stage gate line; a third transistor has a first end, a second end, and a control end. The control end of the three transistors is connected to the first end of the second transistor, and the second end of the third transistor is electrically connected to the low voltage line; a fourth transistor has a first end, a A second end and a control end, the first end of the fourth transistor is electrically connected to the second high voltage line, the control end of the fourth transistor is connected to the first clock line, the fourth transistor The second end is connected to the first end of the third transistor; a fifth transistor has a first end, a second end and a control end, and the first end of the fifth transistor is connected to the Reset the signal line, the control end of the fifth transistor is connected to the first end of the fifth transistor, and the second end of the fifth transistor is connected to the first end of the third transistor; Six transistors having a first end, a second end and a control end, the control end of the sixth transistor is connected to the second end of the fifth transistor, and the second end of the sixth transistor Electrically connected to the low-voltage line; a seventh transistor having a first end, a second end, and a control end; the first end of the seventh transistor is connected to the second clock line; an eighth The transistor has a first end, a second end and a control end. The control end of the eighth transistor is connected to the control end of the sixth transistor, and the second end of the eighth transistor is electrically connected Connected to the low voltage line, and the first end of the eighth transistor is connected to the first gate line; A ninth transistor has a first end, a second end, and a control end. The second end of the ninth transistor is connected to the control end of the seventh transistor, and the second end of the ninth transistor is One end is connected to the control end of the third transistor, and the control end of the ninth transistor is connected to the second high voltage line; a tenth transistor has a first end, a second end, and a control end , The first end of the tenth transistor is connected to the first end of the seventh transistor, the second end of the tenth transistor is connected to the first end of the eighth transistor, the tenth transistor The control terminal is connected to the control terminal of the seventh transistor; and an eleventh transistor has a first terminal, a second terminal and a control terminal, and the first terminal of the eleventh transistor is connected The first end of the sixth transistor, the second end of the eleventh transistor is connected to the first end of the eighth transistor, and the second end of the eleventh transistor is connected to the control end . The display panel according to claim 5, wherein the resistor is provided at the second end of the fourth transistor and the first end of the third transistor. The display panel according to claim 5, wherein the material of the resistor is the same as the material of the semiconductor layer of the fourth transistor or the third transistor. The display panel according to claim 5, wherein the first transistor, the seventh transistor, the tenth transistor, and the eleventh transistor are arranged along the first direction such that they are all arranged in the same row, The second transistor, the third transistor, and the fifth transistor are arranged along the first direction such that they are all arranged in another same row, the fourth transistor, the sixth transistor, and the eighth transistor The crystals are arranged along the first direction so that they are all arranged in another same row. According to the display panel of claim 5, the seventh transistor, the tenth transistor, and the eleventh transistor are arranged along the first direction, so that they are all arranged in the same Row, the second transistor, the third transistor, and the fifth transistor are arranged along the first direction so that they are all arranged in another same row, the fourth transistor, the sixth transistor, and the fourth transistor The eight transistors are arranged along the first direction, so that they are all arranged in another same row. The display panel according to claim 5, wherein the first high voltage line is located between the first clock line and the low voltage line, and the reset signal line and the second high voltage line are located at the second clock line On opposite sides of the line, the reset signal line is located between the tenth transistor and the eleventh transistor. The display panel according to claim 1, wherein each of the gate driving circuit modules includes a plurality of transistors, and the transistors are respectively disposed between the first sub-pixel and the second sub-pixel. The display panel according to claim 5, wherein the first transistor and the second transistor are respectively arranged along the second direction, and the fifth transistor and the eleventh transistor are respectively arranged along the second direction Arranged, the eighth transistor and the tenth transistor are respectively arranged along the second direction.

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