JPH1164889A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a vertical or horizontal driving circuit concerning a display device provided with the rows and columns of mutually crossing scanning lines and signal lines, pixels arranged at the crossing parts of both the lines, a vertical driving circuit connected to the respective scanning lines so as to successively select pixels for one row, and a horizontal driving circuit connected to the respective signal lines so as to write signal voltages to the selected pixels for one row. SOLUTION: The pixel has a thin film transistor 0 formed on an insulated substrate 1 and connected to the scanning lines and signal lines and a pixel electrode to which the signal voltage is written through the thin film transistor 0. The vertical and horizontal driving circuits are composed of plural thin film transistors 0 integrally formed on the same insulated substrate 1 and metal wiring 10 and 12 for connecting these transistors as well. Concretely, the upper layer metal wiring 12 and lower layer metal wiring 10 overlapped vertically are formed through a 1st inter-layer insulating film 9 onto the insulated substrate 1. The upper layer metal wiring 12 is arranged just above the thin film transistor 0, and the lower layer metal wiring 10 is arranged anywhere except just above the thin film transistor 0 on the other hand.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a display device.
More particularly, the present invention relates to a metal wiring structure of a thin film transistor integrated on an insulating substrate of a display device.

[0002]

2. Description of the Related Art FIG. 8 schematically shows a general configuration of a conventional display device. The display device 200 is divided into a central effective pixel area and a peripheral area surrounding the central effective pixel area. In the effective pixel area 201, rows of scanning lines and columns of signal lines that intersect with each other, and pixels arranged at the intersections of both are formed. Each pixel includes, for example, a thin film transistor formed on an insulating substrate and connected to a scanning line and a signal line, and a pixel electrode to which a signal voltage is written through the thin film transistor. On the other hand, in the peripheral area, a vertical driving circuit 202 connected to each scanning line and sequentially selecting one row of pixels, and a horizontal driving circuit connected to each signal line and writing a signal voltage to the selected one row of pixels. A drive circuit 203 is formed. Vertical drive circuit 202 and horizontal drive circuit 2
Reference numeral 03 also includes a plurality of thin film transistors integrated on the same insulating substrate and metal wiring connecting these thin film transistors. The horizontal drive circuit 203 generates, for example, a grayscale signal voltage based on multi-bit digital image data, and writes the signal voltage to the selected one row of pixels. The size of the display device 200 has been increasing in recent years, and a display having a diagonal size of 14 inches or more is under development. Even in such a large-area display device, the vertical drive circuit 202 and the horizontal drive circuit 203 are arranged along the vertical and horizontal directions of the insulating substrate.

[0003]

For example, if the angle of view is 1
In the case of 4 inches, the vertical dimension of the effective pixel area 201 is about 2
14 mm, and the lateral dimension is about 286 mm. The vertical drive circuit 202 and the horizontal drive circuit 203 are arranged along this dimension. As a result, there is a problem that the length of metal wiring used for power supply, control, or signal supply becomes longer, and the resistance value increases. To suppress the wiring resistance, the wiring width may be increased. However, this increases the area occupied by the drive circuit in the display device 200. For example, as shown in FIG. 8, the exclusive width A of the horizontal drive circuit 203 increases. In particular, the horizontal drive circuit 203 that converts a digital signal into an analog signal has a complicated circuit configuration, so that the circuit scale is inevitably large. In the digital horizontal drive circuit 203, since a number of metal wires for power supply, control and signal supply are arranged in parallel,
The occupation width A increases. As described above, when a thin-film transistor or the like is integrated on a large-area display device with a diagonal dimension of 14 inches or more to incorporate a vertical drive circuit and a horizontal drive circuit on the same substrate, they are arranged in the peripheral portion of the effective pixel area Will do. In order to operate these drive circuits, it is necessary to extend the length of signal wiring for supplying a power supply voltage and a signal. Accordingly, the resistance of the metal wiring increases as the distance from the power supply increases. In this state, the voltage on the metal wiring fluctuates due to the resistance component. In order to avoid this, the wiring width may be increased, but this increases the size of the drive circuit.
In particular, in a display device, a large-sized drive circuit occupies the periphery of the effective pixel area, and the number of panels that can be taken out from one insulating substrate is limited.
In addition, the yield is reduced.

FIG. 9 schematically shows a circuit configuration of the horizontal drive circuit 203. As shown in the figure, CMOSs connected in multiple stages are provided along the upper side of the effective pixel area. Each CMOS has Pch TFT and Nch T
It consists of a set of FTs. A power supply voltage VDD and a ground voltage VSS are supplied to each CMOS via parallel metal wirings.
Focusing on one metal wiring, assuming that the sheet resistance value is R, the wiring length is L, and the wiring width is W, the wiring resistance is represented by R × L / W. In the case of a display device having an angle of view of 14 inches, the wiring length L of the metal wiring formed in the horizontal drive circuit 203 is, for example, about 285 mm. When aluminum is used as the metal wiring, the sheet resistance R is 40 mΩ /
□. If an attempt is made to secure a wiring resistance of, for example, 200Ω in order to prevent a decrease in the power supply voltage, the wiring width W is 100 μm from the above equation. Generally, from 100 μm to 2
It is necessary to secure a wiring width W of 00 μm. When the configuration of the horizontal drive circuit 203 becomes complicated, the number of metal wirings ranges from several tens to several hundreds, and the occupied area becomes extremely large. In order to reduce the wiring resistance without increasing the wiring width, it is conceivable to increase the thickness of the metal wiring.
However, in order to keep the integration density of the horizontal drive circuit 203 high, fine wiring accuracy is required, and the thickness of the metal wiring must be reduced to some extent. For this reason, 14
When a driving circuit is built on an inch-size transparent insulating substrate, the width of each metal wiring is actually set to 100 μm to 20 μm.
It is necessary to secure it in the range of 0 μm. This inevitably increases the size of the horizontal drive circuit.

[0005]

Means for Solving the Problems In order to solve the above-mentioned problems of the prior art, the following measures have been taken. That is, the display device according to the present invention has, as a basic configuration, a row of scanning lines and a column of signal lines that intersect each other, a pixel disposed at an intersection of the two, and one row connected to each scanning line and sequentially. And a horizontal drive circuit connected to each signal line and writing a signal voltage to the selected one row of pixels. The pixel has a thin film transistor formed on an insulating substrate and connected to the scanning line and the signal line, and a pixel electrode to which a signal voltage is written via the thin film transistor. The vertical drive circuit and the horizontal drive circuit are also composed of a plurality of thin film transistors integrated on the same insulating substrate and metal wiring connecting these thin film transistors. As a feature, at least a part of the metal wiring is formed immediately above each thin film transistor.

Specifically, on the insulating substrate, an upper metal wiring and a lower metal wiring which are vertically stacked with an interlayer insulating film interposed therebetween are formed. The upper metal wiring is disposed immediately above each thin film transistor, while the lower metal wiring is disposed other than immediately above each thin film transistor. Preferably, the upper metal wiring is commonly connected to each thin film transistor, and is used for power supply, control, or signal supply. Preferably, the upper metal wiring is
It is formed in a linear and continuous pattern. Preferably, the horizontal drive circuit generates a reference voltage based on multi-bit digital image data. In this case, the upper metal wiring is used for supplying digital image data or supplying a reference voltage.

According to the present invention, an upper-layer metal wiring is provided in addition to a lower-layer metal wiring, and this is disposed immediately above a thin film transistor. With such a configuration, the circuit size can be significantly reduced without changing the circuit design.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic sectional view showing a basic configuration of a display device according to the present invention. An active matrix type display device basically includes a set of pixel electrodes, a set of switching elements for individually driving the pixel electrodes, and a drive circuit for operating the switching elements, which are integrated on an insulating substrate. is there. The switching element and the driving circuit are constituted by thin film transistors. FIG. 1 shows only one thin film transistor constituting a driving circuit for easy understanding. This thin film transistor 0 has a bottom gate structure, and has an insulating substrate 1
Electrode 2 formed by patterning, gate insulating film 3 covering the same, and semiconductor thin film 4 formed thereon
And The semiconductor thin film 4 is made of, for example, polycrystalline silicon crystallized by laser light irradiation. In this semiconductor thin film 4, a channel region 5 and a high-concentration impurity region 6 serving as a drain D / source S are formed. In this example, the thin film transistor 0 is an n-channel type, and the high concentration impurity region 6 is N +. The channel region 5 is covered with a protective film 8 which also serves as a mask during ion doping. Further, the entire thin film transistor 0 is covered with the first interlayer insulating film 9. A lower metal wiring 10 is formed on the first interlayer insulating film 9 by patterning, and is electrically connected to a drain D and a source S via a contact hole. Further, a second interlayer insulating film 11 is formed so as to cover lower metal wiring 10. An upper metal wiring 12 is formed thereon. The upper metal wiring 12 is electrically connected to the lower metal wiring 10 via a contact hole opened in the second interlayer insulating film 11. The thin-film transistor 0 has a low-concentration impurity region 7 between the high-concentration impurity region 6 on the drain D side and the channel region 5. Also, the high concentration impurity region 6 on the source S side
A low-concentration impurity region 7 is also provided between and channel region 5. The low-concentration impurity region 7 is provided to reduce the electric field concentration at the drain end and to suppress the leak current.

As a feature of the present invention, at least a part of the metal wiring is formed immediately above the thin film transistor 0. Specifically, the second interlayer insulating film 1 is formed on the insulating substrate 1.
The upper metal wiring 12 and the lower metal wiring 10 are vertically overlapped with the upper metal wiring 12 interposed therebetween.
Numeral 0 is arranged other than immediately above the thin film transistor 0. In the drawing, the wiring width of the upper metal wiring 12 is represented by W.
Since the width portion of the upper metal wiring 12 is basically located directly above the thin film transistor 0, the device size Z1 can be relatively small. The upper metal wiring 12 is commonly connected to each of the thin film transistors 0, and is used for power supply, control, or signal supply. Upper layer metal wiring 1
2 is formed in a linear and continuous pattern.

According to the present invention, in addition to the lower metal wiring 10 conventionally connected to the drain D and the source S, the upper metal wiring 1
2 is provided, which is disposed immediately above the thin film transistor 0. As the lower metal wiring 10, for example, a laminate in which an aluminum thin film is covered with a molybdenum thin film is used. This is because the lower metal wiring 10 and the upper metal wiring 1 are formed on the second interlayer insulating film 11.
When opening a contact hole to make a connection with 2,
This is to prevent the lower metal wiring 10 from being corroded by the HF-based etchant. On the other hand, the upper metal wiring 12 uses an aluminum thin film or a Mo / Al thin film. In addition,
The contact hole opened in the second interlayer insulating film 11 is provided at a different place from the contact hole opened in the first interlayer insulating film 9. Alternatively, it is desirable that the size of the contact hole opened in the first interlayer insulating film 9 be smaller than the size of the contact hole opened in the second interlayer insulating film 11. This makes it possible to prevent corrosion of the metal wiring.

FIG. 2 schematically shows a wiring structure of a conventional thin film transistor. Figure 1 for easy understanding
The parts corresponding to those of the embodiment of the present invention shown in FIG. In the conventional example, connection of individual thin film transistors is performed using only one metal wiring 10. The metal wiring 10 is formed in a portion other than immediately above the thin film transistor 0, and its width is represented by W. As is clear from the figure, the device size Z2 of the thin film transistor 0 becomes larger than the device size Z1 of the thin film transistor according to the present invention shown in FIG.

FIG. 3 schematically shows a conventional contact structure in a multilayer wiring. Parts corresponding to those of the present embodiment shown in FIG. 1 are denoted by corresponding reference numerals to facilitate understanding. In this conventional example, the second interlayer insulating film 11 is formed on the semiconductor thin film 4 at the same location and the same size as the first contact hole 15 opened in the first interlayer insulating film 9.
The second contact hole 16 is opened. In such a contact structure, the step coverage at the step portion is deteriorated, so that the HF-based etchant enters at the step edge portion. In this case, the lower metal wiring 10 is disconnected, and thereafter, it becomes difficult to electrically connect the lower metal wiring 10 to the thin film transistor and the upper metal wiring 12. In order to prevent this, in the embodiment of the present invention shown in FIG. 1, the second contact hole is provided at a different place from the first contact hole, or the size of the second contact hole is reduced to the size of the first contact hole. Is set smaller than In the conventional example of FIG. 3, around the first contact hole 15,
Since a concave step is formed and the step coverage of the second interlayer insulating film 11 is poor, the portion of the metal wiring formed on the side wall of the first contact hole 15 is extremely thin as compared with the plane portion. For this reason, when a voltage is applied to the metal wiring, dielectric breakdown easily occurs. The conventional structure shown in FIG. 3 is disclosed, for example, in Japanese Patent Application Laid-Open No. 7-193128.

FIG. 4 is a schematic sectional view showing another embodiment of the present invention. Parts corresponding to those of the embodiment shown in FIG. 1 are denoted by corresponding reference numerals to facilitate understanding. The thin film transistor according to the present embodiment has a top gate structure. This display device is configured using a transparent insulating substrate 1 made of glass or the like. A semiconductor thin film 4 made of polycrystalline silicon or the like is formed thereon. The thin film transistor 0 is integrally formed using the semiconductor thin film 4 as an active layer. The thin film transistor 0 has a gate electrode 2 formed by patterning on a semiconductor thin film 4 via a gate insulating film 3. The portions of the semiconductor thin film 4 located on both sides of the gate electrode 2 are heavily doped with n-type impurities, and
And a drain region D. Thus, an N-channel thin film transistor is obtained. In the case of forming a P-channel thin film transistor, a p-type impurity may be injected into the semiconductor thin film 4.

The thin-film transistor 0 having the above-described structure is composed of P
It is covered with a first interlayer insulating film 9 made of SG or the like. On the first interlayer insulating film 9, a lower metal wiring 10 is formed by patterning. The lower metal wiring 10 is obtained by depositing aluminum by sputtering and then patterning it into a predetermined shape. An aluminum / silicon alloy containing about 1% of silicon may be used instead of aluminum. Alternatively, a metal material such as molybdenum, titanium, gold, silver, palladium, tantalum, tungsten, nickel, or chromium can be used instead of aluminum. Further, instead of a pure metal, silicide which is a compound of silicon and these metal elements may be used. The first interlayer insulating film 9 is provided with a contact hole in advance, through which a lower metal wiring 10 is formed.
Is electrically connected to the source region S and the drain region D of the thin film transistor 0. The lower metal wiring 10 is also covered with a second interlayer insulating film 11 made of PSG or the like.
An upper metal wiring 12 is formed thereon by patterning. The upper metal wiring 12 is connected to the lower metal wiring 10 via a contact hole opened in the second interlayer insulating film 11. The upper metal wiring 12 can be formed using the same conductive material as the lower metal wiring 10. The upper metal wiring 12 is located immediately above the thin film transistor 0.

FIG. 5 shows a plan structure of a display device according to the present invention, and particularly, one CMOS is taken out and schematically shown. The CMOS is connected in multiple stages as schematically shown in FIG. 9 to constitute a part of a horizontal drive circuit or a vertical drive circuit. FIG. 5A shows a conventional wiring structure, and FIG.
It corresponds to. On the other hand, (B) shows the wiring structure according to the present invention, which corresponds to the two-layer wiring structure of FIG.
The CMOS includes a pair of P-channel thin-film transistors 0P and N-type thin-film transistors 0N. The source S of the P-channel thin-film transistor 0P is the power supply voltage V
N-channel thin-film transistor 0N connected to the DD side
Is connected to the ground voltage VSS side. The drains D of the pair of thin film transistors 0P and 0N are connected to each other.

As shown in FIG. 1A, in the conventional example, a single-layer metal wiring 10 is connected to the VDD side, and a single-layer metal wiring 10 is used also to the VSS side. The width dimension of these metal wires 10 is represented by W. Since the metal wiring 10 is provided so as not to be located immediately above each of the thin film transistors 0P and 0N, the device size is increased. The gate wiring 2A extending from the gate electrode 2 passes below the metal wiring 10. On the other hand, in the wiring structure of the present invention shown in (B), the upper-layer metal wiring 12 is used on the VDD side, and is disposed almost directly above the P-channel thin film transistor 0P. Further, the upper metal wiring 12 is also used on the VSS side, and is arranged almost directly above the N-channel thin film transistor 0N. Thereby, the device size can be reduced.
Alternatively, if the device size is the same as that of the conventional example shown in (A), the width W of each upper metal wiring 12 can be increased correspondingly, which is effective in reducing the wiring resistance. The drain D of the P-channel thin film transistor OP and the drain D of the N-channel thin film transistor are connected to each other by a lower metal wiring 10. Furthermore,
Although not shown, the gate wiring 2A is connected to the lower metal wiring 10 by using the same metal wiring as that of the lower-layer metal wiring 10, so that necessary electrical connection is established.

FIG. 6 is a schematic block diagram showing the entire configuration of the display device according to the present invention. This display device includes a pixel array section 110 constituting a screen, a vertical drive circuit 120 and a horizontal drive circuit 130 disposed around the pixel array section 110, and an external timing generation circuit 140. This display device is, for example, an active matrix type liquid crystal display (LCD) using a polycrystalline silicon thin film transistor as a switching element. The peripheral vertical drive circuit 120 and the horizontal drive circuit 130 are integrally formed on the same substrate as the pixel array unit 110. In the pixel array section 110, scanning lines X and signal lines Y intersecting with each other are formed. Pixels PXL are formed at intersections of the row-shaped scanning lines X and the column-shaped signal lines Y. The pixel PXL includes a pixel electrode and a counter electrode COM facing the pixel electrode, and an electro-optical material such as a liquid crystal is held between the two electrodes. Each pixel PXL
Is a thin film transistor Tr using polycrystalline silicon as an active layer.
Driven by The drain electrode of the thin film transistor Tr is connected to the corresponding pixel PXL, the source electrode is connected to the corresponding signal line Y, and the gate electrode is connected to the corresponding scanning line X. The vertical drive circuit 120 includes a vertical shift register circuit 121 and an output buffer circuit 122. The vertical shift register circuit 121 is connected to each scanning line X via an output buffer circuit 122, and sequentially selects one row of pixels PXL. The horizontal drive circuit 130 includes a horizontal shift register circuit 131 and a line memory circuit 132
, Level conversion circuit 133 and digital / analog conversion circuit 1
34 are formed in an integrated manner. This horizontal drive circuit 1
Reference numeral 30 is connected to each signal line Y, generates a multi-gradation signal voltage based on multi-bit digital image data, and writes the signal voltage to the selected one row of pixels PXL. The signal voltage is generated by modulating a reference voltage based on digital image data. The timing generation circuit 140 includes the vertical drive circuit 120 and the horizontal drive circuit 1
30 is performed. As illustrated, a plurality of metal wirings for supplying digital image data and a plurality of metal wirings for supplying a reference voltage are formed in the horizontal drive circuit 130 in parallel. Further, metal wiring for supplying a power supply voltage to each circuit is also formed. By configuring these metal wirings with upper metal wirings disposed immediately above the thin film transistors constituting each circuit, the area dimensions of the horizontal drive circuit 130 can be reduced.

FIG. 7 is a block diagram showing a specific configuration example of the digital-to-analog conversion circuit 134 shown in FIG. In this figure, only one stage of digital-to-analog conversion circuit corresponding to one signal line is shown for easy understanding. This digital-to-analog conversion circuit comprises a series connection of a decoder DEC1 at the preceding stage and a decoder DEC2 at the subsequent stage. The decoder DEC1 in the preceding stage is used for selecting a reference voltage, and includes a pair of analog gate elements TG1 and TG2. Here, a CMOS transmission gate element is used as the analog gate element. The decoder DEC1 outputs a selection signal in accordance with the higher three bits d1d2d3 of the 6-bit digital image data, and opens TG1 and TG2 to select a pair of reference voltages. The pair of reference voltages that have passed through TG1 and TG2 are sent to the subsequent stage as primary gradation signals. Subsequent decoder D
EC2 outputs a selection signal according to the lower-order 3-bit data d4d5d6, opens the analog gate element TG3, and outputs a secondary gradation signal as a final signal voltage.
The latter-stage decoder DEC2 includes a plurality of resistance elements RS connected in series. A primary gradation signal is applied to both ends of the series connection of the resistance element RS. As described above, this primary gradation signal is a pair of reference voltages selected by the preceding analog gate elements TG1 and TG2. The potential difference between the first reference voltage on the high level side and the second reference voltage on the low level side is divided by a resistor RS connected in series, and a desired voltage division is selected by TG3.
The power supply voltage VDD and the ground voltage VSS are supplied to each decoder via metal wiring. Also, a required reference voltage is supplied via the metal wiring. All of these metal wirings are constituted by upper metal wirings according to the present invention, and pass right above the thin film transistors.

[0019]

As described above, according to the present invention,
At least a part of the metal wiring included in the display device is formed immediately above each thin film transistor. With such a configuration,
The area occupied by the peripheral drive circuit can be reduced, and the effective pixel area becomes much larger. It is possible to reduce the size of the drive circuit built in the display device without lowering the power supply voltage of the drive circuit or delaying signal transmission.
Further, it is possible to form a contact portion with a stable and low resistance value in each thin film transistor.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a structure of a thin film transistor integratedly formed in a display device according to the present invention.

FIG. 2 is a schematic partial sectional view showing the structure of a conventional thin film transistor.

FIG. 3 is a partial cross-sectional view showing a conventional contact structure.

FIG. 4 is a partial cross-sectional view showing another embodiment of a thin film transistor integratedly formed in a display device according to the present invention.

FIG. 5 is a plan view showing a wiring structure around a thin film transistor.

FIG. 6 is a block diagram illustrating an overall configuration of a display device according to the present invention.

FIG. 7 is a circuit diagram showing a specific example of a digital-to-analog conversion circuit incorporated in the horizontal drive circuit of the display device shown in FIG.

FIG. 8 is a schematic plan view showing an example of a conventional display device.

FIG. 9 is a schematic diagram illustrating a configuration of a conventional driving circuit.

[Explanation of symbols]

0 ... Thin film transistor, 1 ... Insulating substrate, 2 ...
・ Gate electrode, 3 ・ ・ ・ Gate insulating film, 4 ・ ・ ・ Semiconductor thin film, 5 ・ ・ ・ Channel region, 8 ・ ・ ・ Protective film, 9 ・ ・
.First interlayer insulating film, 10... Lower metal wiring, 11.
.Second interlayer insulating film, 12 ... upper metal wiring

Claims (5)

[Claims] 1. A row of scanning lines and a column of signal lines crossing each other, pixels arranged at the intersection of the two, and a vertical drive circuit connected to each scanning line and sequentially selecting one row of pixels. ,
A horizontal drive circuit connected to each signal line and writing a signal voltage to a pixel of a selected one row, wherein the pixel is formed on an insulating substrate and the scanning line and the signal line A vertical driving circuit and a horizontal driving circuit are also formed on the same insulating substrate, and a plurality of thin-film transistors and a metal connecting the thin-film transistors to each other. And a wiring, wherein at least a part of the metal wiring is formed immediately above each thin film transistor. 2. An upper metal wiring and a lower metal wiring which are vertically overlapped with each other via an interlayer insulating film are formed on the insulating substrate, and the upper metal wiring is disposed immediately above each thin film transistor. 2. The display device according to claim 1, wherein the lower metal wiring is arranged other than immediately above each thin film transistor. 3. The display device according to claim 2, wherein the upper metal wiring is commonly connected to each of the thin film transistors, and is used for power supply, control, or signal supply. 4. The method according to claim 3, wherein the upper metal wiring is formed in a linear and continuous pattern.
The display device according to the above. 5. The horizontal driving circuit according to claim 1, wherein the horizontal drive circuit generates a signal voltage by gradation-converting a reference voltage based on multi-bit digital image data. The display device according to claim 1, wherein the display device is used for supplying a liquid crystal display.