CN102393587A - Signal wiring structure in GOA (gate driver on array) circuit of liquid crystal display - Google Patents
Signal wiring structure in GOA (gate driver on array) circuit of liquid crystal display Download PDFInfo
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- CN102393587A CN102393587A CN2011103717027A CN201110371702A CN102393587A CN 102393587 A CN102393587 A CN 102393587A CN 2011103717027 A CN2011103717027 A CN 2011103717027A CN 201110371702 A CN201110371702 A CN 201110371702A CN 102393587 A CN102393587 A CN 102393587A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 83
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 6
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 6
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 6
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 6
- 102100040856 Dual specificity protein kinase CLK3 Human genes 0.000 description 5
- 101000749304 Homo sapiens Dual specificity protein kinase CLK3 Proteins 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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Abstract
The invention provides a signal wiring structure in a GOA (gate driver on array) circuit of a liquid crystal display. The structure comprises a plurality of first metal layers, an insulating layer and a plurality of second metal layers, wherein each first metal layer is provided with a control signal wire; the insulating layer is formed under the first metal layers; the plurality of second metal layers are formed under the insulating layer, and the control signal wire on each first metal layer is electrically connected with the corresponding second metal layer through a plurality of through holes; and the number of the through holes formed on the control signal wire on each first metal layer is the same. According to the signal wiring structure, the control signal wire on each first metal layer is electrically connected with the second metal layer through a plurality of through holes, and the number of the through holes formed on the control signal wire on each first metal layer is the same, so that the impedance values on all control signal wires are uniform, and input and output signals of each stage of the GOA circuit are stable, and the image display quality is improved.
Description
Technical Field
The present invention relates to a GOA circuit of a liquid crystal display, and more particularly, to a signal routing structure for a GOA circuit.
Background
Currently, in an Active Matrix Liquid Crystal Display (AMLCD), each pixel has a Thin Film Transistor (TFT) with a gate electrically connected to a scan line in a horizontal direction, a drain electrically connected to a data line in a vertical direction, and a source electrically connected to a pixel electrode. If a positive voltage is applied to a certain scan line in the horizontal direction, all TFTs on the scan line are turned on, and the pixel electrode corresponding to the scan line is connected to the data line in the vertical direction, so as to write the video signal voltage of the data line into the pixel, thereby controlling the transmittance of different liquid crystals and further achieving the effect of controlling the color.
In the prior art, the driving circuit is mainly completed by attaching an IC to the outside of the liquid crystal panel, and a CMOS process is used. In contrast, the GOA technology (Gate driver on array, array substrate line driving technology) is a technology for directly manufacturing a Gate driving circuit on an array substrate to replace a driving chip manufactured by an external silicon chip. The GOA circuit can be directly manufactured around the panel, so that the manufacturing process is simplified, the product cost can be reduced, the integration level of the TFT-LCD panel is improved, and the panel tends to be thinner.
However, in the conventional method, a double metal layer is used as much as possible to reduce the impedance value when the GOA signal is routed, and vias are used to electrically connect different signal crosswires in series. On the other hand, the different numbers of through holes will cause impedance mismatching of signal traces, because when the through holes are used for electrical series connection of the upper and lower metal layers, although the impedance value can be reduced, the impedance of the through holes themselves is higher than that of a single metal layer, and when the number of the through holes used by the signal line is larger, the impedance effect of the double-layer metal layer is reduced. For example, the signal bus CK6 is located at the farthest outer side from the GOA circuit, and the number of times of being crossed by other signal traces is the least, so the impedance value is the lowest; the signal bus CK1 is located at the nearest inner side of the GOA circuit, and is crossed by other signal traces the most times, so that the impedance value is the highest. As a result, the impedances on the signal buses CK1 to CK6 are not uniform, which affects the input and output of each stage of the GOA circuit, resulting in abnormal image display.
In view of the above, an urgent need exists in the art for a signal routing structure in a GOA circuit of a liquid crystal display to make the impedance on the signal bus uniform, improve the stability of the GOA circuit, and improve the image display quality.
Disclosure of Invention
Aiming at the defects existing in the prior art when the signal routing structure used in the GOA circuit of the liquid crystal display is used, the invention provides a novel signal routing structure.
According to an aspect of the present invention, a signal routing structure in a Gate driver On Array (GOA) circuit for a liquid crystal display is provided, wherein the signal routing structure comprises:
the plurality of first metal layers are arranged along the vertical direction, and each first metal layer is provided with a control signal routing;
an insulating layer formed below the first metal layer; and
the plurality of second metal layers are arranged along the vertical direction and formed below the insulating layer, and the control signal routing on each first metal layer is electrically connected with the corresponding second metal layer through a plurality of through holes;
the number of the through holes formed on the control signal routing line on each first metal layer is the same.
Preferably, each of the plurality of first metal layers is coupled to the corresponding GOA circuit by a conductive connection line in the horizontal direction.
Preferably, the plurality of GOA circuits includes a first GOA circuit and a second GOA circuit, and the plurality of first metal layers includes a left metal layer and a right metal layer. More preferably, the first GOA circuit is electrically connected to the control signal trace on the left metal layer by a conductive connection line, and the second GOA circuit is electrically connected to the control signal trace on the right metal layer by another conductive connection line.
Preferably, the plurality of vias on each first metal layer divide the corresponding first metal layer into N segments, where N is a natural number greater than or equal to 2. More preferably, in the horizontal direction, the corresponding segment position of each of the plurality of first metal layers is the same.
Preferably, the through holes formed on the control signal traces on each first metal layer have the same outer dimension.
Preferably, the plurality of GOA circuits are periodically coupled to respective ones of the plurality of first metal layers by a conductive connection line.
Preferably, the horizontal routing direction of the conductive connection line corresponds to the position of the section formed by the through hole.
By adopting the signal routing structure for the GOA circuit of the liquid crystal display, the control signal lines are arranged on the plurality of first metal layers, the plurality of second metal layers are correspondingly arranged below each first metal layer through the insulating layer, the control signal lines on each first metal layer are electrically connected with the second metal layers through the plurality of through holes, and the number of the through holes formed on the control signal lines on each first metal layer is set to be the same, so that the impedance values on all the control signal lines can be ensured to be uniform, the input signals and the output signals of each GOA circuit are further stable, and the image display quality is improved.
Drawings
The various aspects of the present invention will become more apparent to the reader after reading the detailed description of the invention with reference to the attached drawings. Wherein,
fig. 1 is a block diagram illustrating a signal routing structure in a GOA circuit for a liquid crystal display according to an aspect of the present invention.
Detailed Description
In order to make the present disclosure more complete and complete, reference is made to the accompanying drawings, in which like references indicate similar or analogous elements, and to the various embodiments of the invention described below. However, it will be understood by those of ordinary skill in the art that the examples provided below are not intended to limit the scope of the present invention. In addition, the drawings are only for illustrative purposes and are not drawn to scale.
Specific embodiments of various aspects of the present invention are described in further detail below with reference to the accompanying drawings.
Fig. 1 is a block diagram illustrating a signal routing structure in a Gate driver On Array (GOA) circuit for a liquid crystal display according to an aspect of the present invention. Referring to fig. 1, the signal routing structure includes a plurality of first metal layers, an insulating layer, and a plurality of second metal layers. The plurality of first metal layers are arranged along the vertical direction, and each first metal layer has a control signal trace, for example, the leftmost first metal layer has a control signal bus line CLK3 thereon, the middle first metal layer has a control signal bus line CLK2 thereon, and the rightmost first metal layer has a control signal bus line CLK1 thereon. The insulating layer is formed below the first metal layer, and a plurality of second metal layers are formed below the insulating layer and arranged in parallel with the first metal layer. The control signal bus on each first metal layer is electrically connected with the corresponding second metal layer through a plurality of through holes, and the number of the through holes of the control signal bus formed on each first metal layer is the same.
In one embodiment, each of the plurality of first metal layers is coupled to the corresponding GOA circuit by a conductive connection line in the horizontal direction. In detail, the control signal bus CLK1 is connected to the GOA circuit 1 (numeral 10) via an electrical connection 101. The control signal bus CLK2 is connected to the GOA circuit 2 (numeral 12) via an electrical connection 121, and the positions where the electrical connection 121 intersects the control signal buses CLK1 and CLK2, respectively, each include a through hole. The control signal bus CLK3 is connected to the GOA circuit 3 (numeral 14) via an electrical connection 141, and the positions where the electrical connection 141 intersects the control signal buses CLK1, CLK2 and CLK3 respectively include through holes.
In another embodiment, the plurality of vias on each first metal layer divide the corresponding first metal layer into N segments, where N is a natural number greater than or equal to 2. Referring to fig. 1, each of the control signal buses CLK1, CLK2, and CLK3 includes 3 vias, i.e., via 161, via 162, and via 163, by which the first metal layer in which the control signal buses are located is divided into two sections. Preferably, in the horizontal direction, the corresponding segment position of each of the plurality of first metal layers is the same, that is, the through holes of the corresponding segment positions are on the same straight line in the horizontal direction.
In a specific embodiment, the through holes formed on the control signal traces on each first metal layer have the same outer dimension, so that the impedance values of the through holes on different control signal buses are substantially the same.
In yet another embodiment, a plurality of GOA circuits are periodically coupled to respective ones of the plurality of first metal layers by a conductive connection line. In fig. 1, the situation of 3 GOA circuits is only schematically shown, but the invention is not limited thereto. In other embodiments, GOA circuit 4 is coupled to control signal bus CLK1 similar to GOA circuit 1, GOA circuit 5 is coupled to control signal bus CLK2 similar to GOA circuit 2, and GOA circuit 6 is coupled to control signal bus CLK3 similar to GOA circuit 3.
By adopting the signal routing structure for the GOA circuit of the liquid crystal display, the control signal lines are arranged on the plurality of first metal layers, the plurality of second metal layers are correspondingly arranged below each first metal layer through the insulating layer, the control signal lines on each first metal layer are electrically connected with the second metal layers through the plurality of through holes, and the number of the through holes formed on the control signal lines on each first metal layer is set to be the same, so that the impedance values on all the control signal lines can be ensured to be uniform, the input signals and the output signals of each GOA circuit are further stable, and the image display quality is improved.
Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present invention without departing from the spirit and scope of the invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.
Claims (9)
1. A signal routing structure for a Gate driver On Array (GOA) circuit of a Liquid Crystal Display (LCD), the signal routing structure comprising:
the plurality of first metal layers are arranged along the vertical direction, and each first metal layer is provided with a control signal routing;
an insulating layer formed below the first metal layer; and
the plurality of second metal layers are arranged along the vertical direction and formed below the insulating layer, and the control signal routing on each first metal layer is electrically connected with the corresponding second metal layer through a plurality of through holes;
the number of the through holes formed on the control signal routing line on each first metal layer is the same.
2. The signal routing structure according to claim 1, wherein each of the plurality of first metal layers is coupled to the corresponding GOA circuit by a conductive connection line in a horizontal direction.
3. The signal routing structure according to claim 1, wherein the plurality of GOA circuits includes a first GOA circuit and a second GOA circuit, and the plurality of first metal layers includes a left metal layer and a right metal layer.
4. The signal routing structure according to claim 3, wherein the first GOA circuit is electrically connected to the control signal routing on the left metal layer by a conductive connection line, and the second GOA circuit is electrically connected to the control signal routing on the right metal layer by another conductive connection line.
5. The signal routing structure according to claim 1, wherein each of the plurality of vias on each of the first metal layers divides the corresponding first metal layer into N segments, where N is a natural number greater than or equal to 2.
6. The signal routing structure of claim 5, wherein the corresponding segment location of each of the plurality of first metal layers is the same in a horizontal direction.
7. The signal trace structure according to claim 1, wherein the through holes formed on the control signal traces on each of the first metal layers have the same outer dimension.
8. The signal routing structure according to claim 1, wherein the plurality of GOA circuits are periodically coupled to respective ones of the plurality of first metal layers by a conductive connection line.
9. The signal routing structure according to claim 1, wherein a horizontal routing direction of the conductive connection line corresponds to a segmented position formed by the through holes.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103717027A CN102393587A (en) | 2011-11-10 | 2011-11-10 | Signal wiring structure in GOA (gate driver on array) circuit of liquid crystal display |
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| CN2011103717027A CN102393587A (en) | 2011-11-10 | 2011-11-10 | Signal wiring structure in GOA (gate driver on array) circuit of liquid crystal display |
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| WO2014190710A1 (en) * | 2013-05-30 | 2014-12-04 | 京东方科技集团股份有限公司 | Array substrate, display device, and fabrication method of array substrate |
| CN104617106A (en) * | 2015-01-09 | 2015-05-13 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN105974703A (en) * | 2016-07-13 | 2016-09-28 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| CN106647085A (en) * | 2017-02-27 | 2017-05-10 | 武汉华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| WO2017113931A1 (en) * | 2015-12-30 | 2017-07-06 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN107966860A (en) * | 2017-11-24 | 2018-04-27 | 深圳市华星光电技术有限公司 | A kind of GOA circuits, display panel and display device |
| CN108037627A (en) * | 2017-12-29 | 2018-05-15 | 武汉华星光电技术有限公司 | The signal lead structure and array base palte of GOA circuits, liquid crystal display panel |
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| CN109100894A (en) * | 2018-07-02 | 2018-12-28 | 深圳市华星光电技术有限公司 | GOA circuit structure |
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- 2011-11-10 CN CN2011103717027A patent/CN102393587A/en active Pending
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| WO2014190710A1 (en) * | 2013-05-30 | 2014-12-04 | 京东方科技集团股份有限公司 | Array substrate, display device, and fabrication method of array substrate |
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| CN105974703A (en) * | 2016-07-13 | 2016-09-28 | 武汉华星光电技术有限公司 | Liquid crystal display panel |
| CN106647085B (en) * | 2017-02-27 | 2020-03-31 | 武汉华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN106647085A (en) * | 2017-02-27 | 2017-05-10 | 武汉华星光电技术有限公司 | Liquid crystal display panel and liquid crystal display device |
| CN107966860A (en) * | 2017-11-24 | 2018-04-27 | 深圳市华星光电技术有限公司 | A kind of GOA circuits, display panel and display device |
| CN108037627A (en) * | 2017-12-29 | 2018-05-15 | 武汉华星光电技术有限公司 | The signal lead structure and array base palte of GOA circuits, liquid crystal display panel |
| CN109036251A (en) * | 2018-06-22 | 2018-12-18 | 友达光电股份有限公司 | Display panel |
| CN109100894A (en) * | 2018-07-02 | 2018-12-28 | 深圳市华星光电技术有限公司 | GOA circuit structure |
| CN109100894B (en) * | 2018-07-02 | 2021-04-23 | Tcl华星光电技术有限公司 | GOA circuit structure |
| WO2020051987A1 (en) * | 2018-09-13 | 2020-03-19 | 惠科股份有限公司 | Display panel and display apparatus |
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| CN110689836A (en) * | 2019-10-22 | 2020-01-14 | 深圳市华星光电技术有限公司 | GOA circuit and display panel |
| CN113325639A (en) * | 2021-05-27 | 2021-08-31 | Tcl华星光电技术有限公司 | GOA circuit and display device |
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Application publication date: 20120328 |