KR102047744B1

KR102047744B1 - Array Substrate For Liquid Crystal Display Device

Info

Publication number: KR102047744B1
Application number: KR1020130009437A
Authority: KR
Inventors: 최승규
Original assignee: 엘지디스플레이 주식회사
Priority date: 2013-01-28
Filing date: 2013-01-28
Publication date: 2019-11-22
Also published as: KR20140096636A

Abstract

An array substrate for a liquid crystal display device according to the present invention includes: a substrate in which a first image display area and a first, second, third, and fourth non-display areas are defined on the top, bottom, left and right sides of the display area; Gate wiring and data wiring intersecting each other in the display area on the substrate; A plurality of flexible printed cables (FPCs) connected to the gate lines and the data lines in the first non-display area on the substrate; A sub glass connected to the FPC and forming a link portion; A plurality of chip on films (COFs) in contact with the link portion of the subglass; It characterized in that it comprises a printed circuit board which the plurality of COF contacts.

Description

Array Substrate For Liquid Crystal Display Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device in which a narrow bezel having a width of 4 mm or less in a non-display area is implemented.

In general, the liquid crystal display device is a device using the optical anisotropy of the liquid crystal. That is, the liquid crystal display device is a device for representing an image by using a characteristic that can control the light according to the intensity of the electric field and the light is adjusted according to the molecular arrangement of the liquid crystal when the voltage is applied, comprising a common electrode The lower substrate includes an upper substrate and a pixel electrode, and a liquid crystal layer filled between the two substrates.

A liquid crystal display device will be described in more detail with reference to the drawings. 1 is a plan view schematically illustrating a general liquid crystal display device. As illustrated, a general liquid crystal display device 10 includes a color filter substrate (not shown) including a color filter layer, a thin film transistor Tr, a gate line GL, a data line DL, and a pixel electrode 14. The array substrate 11 is provided with a liquid crystal layer (not shown) between the two substrates 11 (not shown).

In addition, the array substrate 11 of the liquid crystal display device 10 may have a rectangular display area DA for displaying an image, and border the display area DA outside the display area DA. Four non-display areas NA1, NA2, NA3, and NA4 are provided.

One of the four non-display areas NA1, NA2, NA3, and NA4 of the array substrate 11 includes a plurality of gates connected to an external circuit in one non-display area (hereinafter, referred to as a first non-display area) NA1. A pad electrode (not shown) and a data pad electrode (not shown), and gates and data link wirings (not shown) connected to them, respectively, are formed. In addition, a plurality of gate lines GL are connected to the display area DA of the array substrate 11 through the gate pad electrodes (not shown) and the gate link wiring lines (not shown) and extend in a horizontal direction. And data lines DL connected to the respective data pad electrodes (not shown) and the data link wirings (not shown) to extend in the vertical direction to define a plurality of pixel regions P. have. In this case, in order to connect the plurality of gate lines GL extending in the horizontal direction to the plurality of gate pad electrodes (not shown) and the plurality of gate link wirings (not shown) formed in the first non-display area NA1. The auxiliary gate line 13 is further formed to be spaced apart from the plurality of data lines DL in a direction perpendicular to the gate line GL and connected to the plurality of gate lines GL.

In addition, thin film transistors Tr are formed at the intersections of the gates and data lines GL and DL, and drain electrodes (not shown) of the thin film transistors Tr are formed in the pixel regions P, respectively. The pixel electrode 14 to be connected is formed.

A color filter substrate (not shown) is formed to face the array substrate 11 having the above structure. The color filter substrate (not shown) includes a color filter layer (not shown) corresponding to each pixel area P, and includes a red, green, and blue color filter pattern sequentially and repeatedly between the color filter pattern and the pattern. The black matrix (not shown) corresponds to the non-display areas NA1, NA2, NA3, and NA4 surrounding the gate wiring GL, the data wiring DL, and the outside of the display area DA of the array substrate 11. ) Is formed, and a common electrode (not shown) is formed on the front surface.

In addition, a liquid crystal layer (not shown) is interposed between the array substrate 11 and the color filter substrate (not shown), and the non-display areas NA1 and NA2 of the edges corresponding to the two substrates 11 (not shown). , NA3 and NA4 have seal patterns (not shown).

On the other hand, one end of the data line DL is positioned in the first non-display area NA1, and one end of the data line DL is connected to the first non-display area NA1. Film: 17) is located, the IC chip (not shown) is mounted on the plurality of COF (17). The printed circuit board 15 is connected to the other ends of the plurality of COFs 17.

In this case, the three non-display areas NA2, NA3, and NA4 except for the first non-display area NA1 do not need an area in which a separate COF 17 is to be mounted. NA4) may be formed to have a narrower width than that of the first non-display area NA1. Accordingly, the three non-display areas NA2, NA3, and NA4 except for the first non-display area NA1 implement a narrow bezel.

The liquid crystal display device 10 having the above-described configuration is actively applied to various electronic devices such as TVs, monitors, notebook computers, mobile phones, PDAs, and the like.

On the other hand, in recent years, display devices have been required to maximize the display area and to make the non-display area as small as possible. However, in the case of the general liquid crystal display device 10, the plurality of data lines DL and the auxiliary gate lines 13 of the pixel region P pass through the link wirings (not shown) of the respective link units, respectively. C) and a data IC (not shown) are formed extending to a plurality of COFs 17 mounted thereon.

At this time, since the COF 17 is formed to have a smaller width than the pixel region P, the pattern of the link wiring (not shown) connected to the COF 17 is relatively larger than the wiring pattern of the pixel region P. It is formed to have a small pitch between wirings. In addition, when the pixel region P and the COF 17 are connected, a link wiring (not shown) formed in the link portion is formed along the shortest distance from which the respective wiring reaches the COF 17 from the pixel region P. FIG. If the link wirings (not shown) are formed to correspond to the shortest distances, a resistance difference may occur between the link wirings (not shown).

Therefore, the link wiring (not shown) is formed to correspond to the shortest distance, but in order to compensate for the resistance difference generated between the link wirings, the link wiring (not shown) is provided with a pattern having a plurality of bends, thereby linking Since the width for mounting the wiring (not shown) is required, the first non-display area NA1 may not have a narrow bezel.

Therefore, the conventional liquid crystal display device 10 is limited in that the entire non-display areas NA1, NA2, NA3, and NA4 are compactly constructed.

The present invention is to solve the above problems, the four non-display areas provided in the form of bordering the display area outside the display area of the liquid crystal display device each having a width of 2mm or less array substrate To provide that purpose.

In order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention comprises: a substrate in which a first image display area and a first, second, third and fourth non-display areas are defined on the top, bottom, left and right sides of the display area; A gate wiring and a data wiring formed to cross each other in the display area on the substrate; A plurality of flexible printed cables (FPCs) connected to the gate lines and the data lines in the first non-display area on the substrate; A sub glass connected to the FPC and forming a link portion; A plurality of chip on films (COFs) in contact with the link portion of the subglass; It characterized in that it comprises a printed circuit board which the plurality of COF contacts.

The display area includes a plurality of pixel areas defined by the gate line and the data line that cross each other.

Each pixel area may include a thin film transistor connected to the gate line, the data line crossing the gate line, and a pixel electrode connected to a drain electrode of each thin film transistor.

The sub glass, the COF and the printed circuit board are disposed on the rear surface of the substrate by the FPC being flipped to the rear surface of the substrate.

The COF may be equipped with a gate IC and a data IC.

The sub glass may be manufactured together with the substrate on the mother glass on which the substrate is formed.

The first, second, third, and fourth non-display areas may have a width of 2 mm or less to form a narrow bezel.

The array substrate for a liquid crystal display device uses a dual rate drive type liquid crystal display device capable of driving a data signal to two adjacent pixel areas in a left and right direction through a single data line. It is characterized by.

The array substrate for a liquid crystal display device may include an auxiliary gate line.

The gate line is connected to the FPC through the auxiliary gate line.

In the array substrate for a liquid crystal display device according to the present invention, the link portion is formed on a separate sub glass and positioned on the rear side of the array substrate, thereby reducing the non-display area, thereby reducing the width of the bezel.

1 is a plan view schematically illustrating a general liquid crystal display device.
2 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a plan view of a mother glass according to an embodiment of the present invention.
4 is a plan view illustrating a portion of a display area of an array substrate in a liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a plan view of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 3 is a plan view of a mother glass according to an exemplary embodiment of the present invention, and FIG. 4 is an array of the liquid crystal display according to an exemplary embodiment of the present invention. A plan view showing a part of the display area of the substrate. In this case, a thin film transistor provided in each pixel area is briefly illustrated for convenience of description.

First, referring to FIG. 2, the array substrate 110 of the liquid crystal display device 100 according to the present invention includes a display area DA for displaying an image and the display area DA outside the display area DA. Four non-display areas NA1, NA2, NA3, and NA4 are provided in the form of borders.

The non-display area of any one of the four non-display areas NA1, NA2, NA3, and NA4, more specifically, the auxiliary gate connected in a direction perpendicular to the data line 130 and the gate lines 113a and 113b formed in the horizontal direction. A film-type flexible printed cable (FPC) 120 having a plurality of signal wires (not shown) is connected to a non-display area (hereinafter, referred to as a first non-display area) NA1 where one end of the wire 132 is positioned. The auxiliary gate line 132 connected to the data line 130 and the gate lines 113a and 113b and the signal line (not shown) of the FPC 120 are connected one-to-one and electrically connected to each other.

In this case, the FPC 120 has a plurality of signal wires (not shown) formed on a base film (not shown) having a flexible property, and a plurality of input / output pins (not shown) are formed at both ends of the FPC 120, respectively. do. The FPC 120 extends the data line 130 and the auxiliary gate line 132 to a separate sub glass 140 through a base input (not shown) through a series of input pins (not shown). It is connected to the, and is connected to a separate sub glass 140 through the output pin (not shown) of the other end.

Here, a plurality of link wires (not shown) are mounted on the separate sub glass 140 to form a link unit 140a, and are electrically connected to the FPC 120. The other end of the sub glass 140 is connected to the other end of the sub glass 140. A plurality of COFs (Chip On Film) 170 are connected, and the plurality of COFs 170 are electrically connected to the printed circuit board 150.

At this time, the COF 170 simultaneously mounts a gate IC (not shown) and a data IC (not shown) in one COF 170.

Here, since the plurality of COF 170 is formed in a relatively small width compared to the sub glass 140, the pattern of the link wiring (not shown) connected to the COF 170 is compared with the wiring pattern of the sub glass 140 It is formed to have a relatively small pitch between wirings. In addition, when the sub glass 140 and the COF are connected, the link wiring formed in the link unit 140a is formed along the shortest distance from which the respective wires reach the COF 170 from the sub glass 140, each of which is the shortest. If the link wiring (not shown) is formed to correspond to the distance, a resistance difference may occur between each link wiring (not shown).

Therefore, the link wirings (not shown) are formed to correspond to the shortest distance, and the link wirings (not shown) are provided with a pattern having a plurality of bends to compensate for the resistance difference generated between each link wiring (not shown). .

As a result, in the conventional liquid crystal display, since the link portion is formed on the first non-display area NA1, the width of the first non-display area NA1 cannot be reduced. However, in the present invention, the link portion 140a is separately provided. The link portion 140a is not formed in the first non-display area NA1, which is the bezel area, by being formed on the sub glass 140.

And by using the flexible properties of the plurality of FPC 120, the FPC 120 is folded toward the rear of the array substrate 110 to form a sub-glass 140, a plurality of COF 170 and the link portion 140a is formed Since the circuit board 150 may be positioned behind the array substrate 110, each of the four non-display areas NA1, NA2, NA3, and NA4 may be implemented as a narrow bezel.

In addition, the printed circuit board 150 connected to the plurality of COFs 170 on which the gate IC (not shown) and the data IC (not shown) are mounted may be formed of at least one substrate, as shown in FIG. 2. Likewise, the display panel DA may be separated into two parts based on the center portion of the display area DA, or may be separated into four parts although not shown.

In addition, as shown in FIG. 3, instead of separately manufacturing the subglass 140, the subglass 140 is configured in an unused portion of the mother glass 190 for manufacturing the array substrate 110. Since it can be manufactured together with the array substrate 110, It does not require additional costs and additional processes required to manufacture a separate sub-glass 140. Accordingly, the subglass 140 and the substrate of the array substrate 110 are made of the same material and have the same thickness.

On the other hand, the liquid crystal display device 100 according to the present invention has a thin film transistor provided in each pixel area in a pixel area adjacent to each other left and right, and diagonally based on the data line 130 positioned at the boundary between the two pixel areas. In the direction. Accordingly, a dual rate drive type liquid crystal display device capable of driving a data signal to two pixel areas adjacent to each other in the left and right directions through one data line 130 is used.

Referring to FIG. 4, the display area DA of the array substrate 110 for a liquid crystal display device according to the present invention is spaced apart in parallel in one direction from the first gate line 113a and the first gate line 113a. The second gate wiring 113b is formed as a pair, and the pair of gate wirings 113a and 113b are formed in parallel with each other by the long axis of the pixel electrode 147.

At this time, although not shown in the drawing, the one spaced apart from each other by the length of the long axis of the pixel electrode 147 between the pair of gate lines 113a and 113b, that is, the area where the pixel electrode 147 is formed is formed. A common wiring (not shown) may be further formed of the same material on the same layer on which the pair of gate wirings 113a and 113b are formed.

The data line 130 is formed to cross each other with the first and second gate lines 113a and 113b interposed therebetween with a gate insulating film (not shown) therebetween. In this case, the pair of gate lines 113a and 113b crossing each other and the region surrounded by the data line 130 (hereinafter referred to as the first pixel region P) are adjacent to each other in the same pixel line in the horizontal direction. One pixel area P1, P2 is formed.

Here, referring to the configuration of one pixel region P, each pixel region P1 and P2 includes a pair of gate lines 113a and 113b and a thin film transistor Tr connected to the data line 130. The pixel electrode 147 connected to the drain electrode of the thin film transistor Tr is formed.

In addition, the center portion of each of the first pixel regions P including two adjacent pixel regions P1 and P2 captured by the pair of gate lines 113a and 113b and the data line 130 passes through the center portion. And alternately spaced apart at a predetermined interval in parallel with the data line 130, and a plurality of auxiliary gate lines 132 are formed over the entire display area DA, and the auxiliary gate lines 132 are formed on the data lines 130. Located on the same floor as).

Accordingly, the pixel regions P1 and P2 may be spaced apart from each other by the long axis size of the data line 130, the auxiliary gate line 132, and the pixel electrode 147. , 113b).

In addition, each of the plurality of auxiliary gate wires 132 is electrically connected to the pair of gate wires 113a and 113b through a gate contact hole chl provided in a gate insulating film (not shown), respectively. to be. That is, all the gate wirings 113 formed in the display area DA are sequentially numbered from top to bottom regardless of the first and second gate wirings 113a and 113b (gl1, gl2, gl3, ...). .), And the data wiring 130 and the auxiliary gate wiring 132 are sequentially numbered from left to right (dl1, dl2, ..., agl1, agl2, ...), the first auxiliary The gate wiring agl1 contacts the first gate wiring gl1 through the gate contact hole ch1, and the second auxiliary gate wiring agl2 contacts the second gate wiring gl2 and the gate contact hole chl. The third auxiliary gate line agl3 is configured to be contacted through the third gate line gl3 and the gate contact hole chl, so that all the gate lines 113 may each have one auxiliary gate line ( 132) is electrically connected.

Meanwhile, the gate signal voltages to the gate wiring 113 are formed by all the gate wirings 113 contacting the auxiliary gate wirings 132 alternately in parallel with the data wiring 130. Application is possible via the auxiliary gate wiring 132.

In addition, since the auxiliary gate line 132 is formed to be parallel to the data line 130, an end of the auxiliary gate line 132 is positioned in the first non-display area NA1 on the upper side where the end of the data line 130 is located. ) And the auxiliary gate lines 132 are located together, so that each of the data lines 130 and the auxiliary gate lines 132 are connected one-to-one with a plurality of FPCs 120 to connect the plurality of FPCs 120. The link portion 140a is electrically connected to the sub glass 140 formed therethrough.

Accordingly, the present invention can connect a plurality of FPCs 120 through one non-display area NA1, and can also implement a narrow bezel as only one link unit 140a configured separately is required.

On the other hand, when the common wiring (not shown) is formed, the common wiring (not shown) and the pixel electrode 147 overlap to form a storage capacitor, and when the common wiring (not shown) is not formed, the pixel The electrodes 147 are formed to overlap the gate wirings 113a and 113b that are not connected to the pixel electrode 147, that is, the gate wirings at the front end or the gate wirings at the rear end, so that the overlapping portions are connected to the storage capacitors. It is coming true.

The thin film transistor Tr is, for example, sequentially stacked on the array substrate 110. The thin film transistor Tr includes a gate electrode, a gate insulating layer, and an ohmic contact layer of impurity amorphous silicon, which is spaced apart from an active layer of pure amorphous silicon. The semiconductor layer may be formed of a source and a drain electrode spaced apart from each other.

As described above, the array substrate 110 for a liquid crystal display device of the present invention is formed in four non-display areas NA1, NA2, NA3, and NA4 by forming the link unit 140a in a separate subglass 140a. The area where COF 170 of is to be mounted is not necessary. In addition, by folding the FPC 120 toward the rear surface of the array substrate 110 by using the plurality of FPC 120, the sub glass 140, a plurality of COF 170 and the printed circuit board is formed link portion (140a) Since 150 may be positioned on the rear surface of the array substrate 110, each of the four non-display areas NA1, NA2, NA3, and NA4 may be implemented as a narrow bezel.

In addition, since the sub glass 140 may be configured in an unused portion of the mother glass 190 for manufacturing the array substrate 110, the sub glass 140 may be manufactured together with the array substrate 110. It does not require additional costs and processes required for the production of a separate subglass 140.

Meanwhile, in the above-described embodiment of the present invention, in consideration of the aperture ratio and the like, a double rate drive type array substrate 110 for driving a liquid crystal display device in which two pixel regions are driven by one data line 130 is provided. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

100: liquid crystal display 110: array substrate
113 (113a, 113b): gate wiring 120: FPC
130: data wiring 132: auxiliary gate wiring
140: subglass 147: pixel electrode
150: printed circuit board 160: IC chip
170: COF 190: Mother Glass
DA: Display area
NA1, NA2, NA3, NA4: first to fourth non-display areas

Claims

A substrate having a central image display area and first, second, third, and fourth non-display areas defined above, below, left, and right of the display area;
Gate wiring and data wiring intersecting each other in the display area on the substrate;
A plurality of flexible printed cables (FPCs) connected to the gate lines and the data lines in the first non-display area on the substrate;
A sub glass connected to the FPC and forming a link portion;
A plurality of chip on films (COFs) in contact with the link portion of the subglass;
Printed circuit board contacting the plurality of COF
Including;
An IC chip is mounted on the plurality of COFs, and the FPC and the sub glass are positioned between the substrate and the IC chip.

The method of claim 1,
And a plurality of pixel regions defined by the gate lines and the data lines crossing each other in the display area.

The method of claim 2,
And each pixel area includes a thin film transistor connected to the gate line, the data line crossing the gate line, and a pixel electrode connected to a drain electrode of each of the thin film transistors.

The method of claim 1,
And the sub glass, the COF, and the printed circuit board are disposed on a rear surface of the substrate by the FPC being flipped to the rear surface of the substrate.

The method of claim 1,
And the gate IC and the data IC are mounted together in the COF.

The method of claim 1,
And the sub glass is manufactured together with the substrate on a mother glass on which the substrate is formed.

The method of claim 1,
And each of the first, second, third and fourth non-display areas is formed to have a width of 2 mm or less so that four surfaces form a narrow bezel.

The method of claim 1,
The array substrate for a liquid crystal display device uses a dual rate drive type liquid crystal display device capable of driving a data signal to two adjacent pixel areas in a left and right direction through a single data line. An array substrate for a liquid crystal display device, characterized in that.

The method of claim 8,
The array substrate for a liquid crystal display device includes an auxiliary gate wiring.

The method of claim 9,
And the gate wiring is connected to the FPC through the auxiliary gate wiring.

The method of claim 1,
And the substrate and the sub glass are made of the same material and have the same thickness.