KR102248643B1 - Array Substrate For Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to an array substrate for a liquid crystal display device, wherein first and second pixel electrodes are formed in one pixel region, and voltages are applied to first and second pixel electrodes through first and second thin film transistors. It drives liquid crystal molecules. At this time, while increasing the aperture ratio by adjusting the number of blocks between the patterns of the first and second pixel electrodes, the first and second dummy electrodes formed on the same layer as the common wiring are electrically separated from the common wiring, and the second pixel By connecting the electrode and applying the same voltage, the parasitic capacitance variation between the first and second pixel electrodes is eliminated.

Description

Array Substrate For Liquid Crystal Display Device

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of increasing a response speed and improving an aperture ratio and luminance.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and liquid crystal display devices (LCD devices) and organic light emitting diode devices (OLEDs) device) has been widely developed and applied to various fields.

Among these flat panel display devices, liquid crystal display devices are widely used because they have advantages such as miniaturization, weight reduction, thinness, and low power driving.

A liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal, and includes a liquid crystal layer between two substrates and two substrates, and a pixel electrode and a common electrode for driving liquid crystal molecules of the liquid crystal layer. Accordingly, the liquid crystal display device adjusts the arrangement of liquid crystal molecules by an electric field generated by applying a voltage to a pixel electrode and a common electrode, and displays an image by varying light transmittance. Such liquid crystal display devices are applied in various ways from portable devices such as mobile phones and multimedia devices to notebook computers or computer monitors and large televisions.

However, in such a liquid crystal display device, an afterimage may occur depending on the response speed of liquid crystal molecules. Accordingly, various studies have been made to speed up the response speed of liquid crystal molecules, and as an example, an array substrate for a liquid crystal display device capable of driving liquid crystal molecules with high voltage has been proposed.

1 is a diagram schematically illustrating a pixel area of an array substrate for a conventional liquid crystal display device.

As shown in FIG. 1, a conventional array substrate for a liquid crystal display device includes a gate wiring GL and first and second data wirings DL1 and DL2. The gate line GL and the first and second data lines DL1 and DL2 cross each other to define a pixel area.

The first thin film transistor T1 is connected to the gate line GL and the first data line DL1, and the second thin film transistor T2 is connected to the gate line GL and the second data line DL2.

A first pixel electrode PE1 connected to the first thin film transistor T1 and a second pixel electrode PE2 connected to the second thin film transistor T2 are positioned in the pixel region. Each of the first pixel electrode PE1 and the second pixel electrode PE2 includes a plurality of patterns, and the pattern of the first pixel electrode PE1 and the pattern of the second pixel electrode PE2 are alternately disposed.

A block is defined between the pattern of the adjacent first pixel electrode PE1 and the pattern of the second pixel electrode PE2, and one pixel region includes a plurality of blocks. Here, one pixel region may include five blocks.

On the other hand, in recent years, a high-resolution liquid crystal display is required. In a high-resolution liquid crystal display device, since the number of pixel areas in the same area increases, the allocated area of each pixel area decreases. Accordingly, the aperture ratio of each pixel region is lowered and the luminance is lowered.

In the liquid crystal display device including the array substrate of FIG. 1, since the aperture ratio of the pixel region varies according to the number of blocks, the number of blocks in the pixel region must be adjusted to improve the aperture ratio.

The present invention has been presented in order to solve the above problems, and an object of the present invention is to provide an array substrate for a liquid crystal display device capable of increasing a response speed and improving an aperture ratio and luminance.

In order to achieve the above object, the present invention provides a substrate, a gate wiring disposed on the substrate and extending along a first direction, and extending along a second direction and crossing the gate wiring to define a pixel region. First and second data wires, a common wire spaced apart from the gate wire and extending along the first direction, and adjacent to the first and second data wires, respectively, and located on the same layer as the common wire, and the First and second dummy electrodes spaced apart from a common wire, a first thin film transistor connected to the gate wire and the first data wire, and a second thin film transistor connected to the gate wire and the second data wire, , A first pixel electrode located in the pixel region and connected to the first thin film transistor, and a second pixel electrode located in the pixel region and connected to the second thin film transistor, wherein the first and second dummy electrodes An array substrate for a liquid crystal display device overlapping with the second pixel electrode and receiving the same voltage as that of the second pixel electrode is provided.

The patterns of the first pixel electrode and the patterns of the second pixel electrode are alternately arranged, a block is defined between the pattern of the adjacent first pixel electrode and the pattern of the second pixel electrode, and the pixel region is Includes blocks.

The number of patterns of the second pixel electrode is greater than the number of patterns of the first pixel electrode.

The array substrate for a liquid crystal display device of the present invention further includes a third dummy electrode connecting the first and second dummy electrodes, and one of the first and second dummy electrodes is in contact with the second pixel electrode. .

The first and second pixel electrodes have bent portions, and the third dummy electrode passes through the bent portions of the first and second pixel electrodes.

The array substrate for a liquid crystal display device of the present invention further includes a first pixel connector connecting one end of the patterns of the first pixel electrode, and a second pixel connector connecting one end of the patterns of the second pixel electrode, The third dummy electrode overlaps the second pixel connector.

In the array substrate for a liquid crystal display device of the present invention, by applying a voltage to the first and second pixel electrodes to drive the liquid crystal molecules, the liquid crystal molecules can be driven with a high voltage, and the response speed of the liquid crystal molecules can be accelerated. .

In addition, since one pixel region includes an even number of blocks, the aperture ratio and luminance can be increased.

In addition, by electrically separating the first and second dummy electrodes formed on the same layer as the common wiring from the common wiring and connecting them to the second pixel electrode so that the same voltage is applied, the parasitic capacitance deviation between the first and second pixel electrodes Can be solved and the picture quality deterioration can be prevented.

1 is a diagram schematically illustrating a pixel area of an array substrate for a conventional liquid crystal display device.
2 is a plan view of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.
3 is a diagram showing transmittance of a liquid crystal display device including an array substrate according to a first embodiment of the present invention.
4 is a plan view of an array substrate for a liquid crystal display device according to a second embodiment of the present invention.
5 and 6 are cross-sectional views of an array substrate for a liquid crystal display device according to a second embodiment of the present invention.
7 is a circuit diagram of a liquid crystal display device according to a second embodiment of the present invention.
8 is a plan view of an array substrate for a liquid crystal display device according to a third embodiment of the present invention.

Hereinafter, an embodiment of the present invention capable of solving the above problems will be described with reference to the drawings.

-First Example-

2 is a plan view of an array substrate for a liquid crystal display device according to a first embodiment of the present invention.

As shown in FIG. 2, a gate wiring 112 is formed along a first direction, first and second data wirings 131 and 132 are formed along a second direction, and The first and second data lines 131 and 132 cross each other to define a pixel region.

In addition, the first and second common wirings 118 are formed along the first direction by being spaced apart from the gate wiring 112, and the first and second auxiliary common wirings 118a and 118b extend from the common wiring 118. As a result, they are positioned adjacent to the first and second data lines 131 and 132, respectively.

First and second thin film transistors connected thereto are formed at intersections of the gate wiring 112 and the first and second data lines 131 and 132. The first thin film transistor includes a first gate electrode 114, a first semiconductor layer (not shown), a first source electrode 133 and a first drain electrode 134, and the second thin film transistor includes a second thin film transistor. A gate electrode 116, a second semiconductor layer (not shown), a second source electrode 135, and a first drain electrode 136 are included.

The first gate electrode 114 and the second gate electrode 116 are connected to the gate wiring 112. The first source electrode 133 is connected to the first data line 131, and the second source electrode 135 is connected to the second data line 132. The first drain electrode 134 is positioned to be spaced apart from the first source electrode 133, and the second drain electrode 136 is positioned to be spaced apart from the second source electrode 135. The first and second drain electrodes 134 and 136 overlap the common wiring 118 to form first and second storage capacitors, respectively.

A first pixel electrode 162 and a second pixel electrode 164 are positioned in the pixel area. Each of the first pixel electrode 162 and the second pixel electrode 164 includes a plurality of patterns substantially extending along the second direction and spaced apart from each other along the first direction. The pattern of the second pixel electrode 164 is alternately disposed to be spaced apart from the pattern of the first pixel electrode 162 along the first direction. Each pattern of the first pixel electrode 162 and the second pixel electrode 164 is bent with respect to the center of the pixel region and thus has a certain angle with respect to the second direction, and passes through the center of the pixel region along the first direction. It has a structure that is substantially symmetric with respect to an imaginary line.

The number of patterns of the second pixel electrode 164 is greater than the number of patterns of the first pixel electrode 162, and the pattern of the second pixel electrode 164 is positioned adjacent to the first and second data lines 131. The pattern of the second pixel electrode 164 adjacent to the first and second data lines 131 overlaps the first and second auxiliary common wirings 118a and 118b, respectively.

One end of the first pixel electrode 162 extends and contacts the first drain electrode 134 through the first contact hole 150a, and one end of the second pixel electrode 164 extends to the second contact hole 150b. ) Through the second drain electrode 136.

In the array substrate for a liquid crystal display device according to the first embodiment of the present invention, a block is defined between the pattern of the adjacent first pixel electrode 162 and the pattern of the second pixel electrode 164, and one pixel The region contains a number of blocks.

Here, one pixel region includes an even number of blocks. For example, the number of blocks may be 4. The array substrate for a liquid crystal display device according to the first embodiment of the present invention can increase the aperture ratio compared to the prior art.

3 is a diagram showing transmittance of a liquid crystal display device including an array substrate according to a first embodiment of the present invention, and one pixel region includes an even number of blocks.

As shown in FIG. 3, one pixel region of the liquid crystal display device including the array substrate according to the first embodiment of the present invention includes an even number of blocks, for example, four blocks. On the other hand, one pixel area of the conventional liquid crystal display device of FIG. 1 includes an odd number of blocks, for example, 5 blocks, and the liquid crystal display device of the present invention including 4 blocks is a conventional liquid crystal display device including 5 blocks. It can be seen that it has a higher transmittance than a liquid crystal display device. At this time, the transmission efficiency of the liquid crystal display device of the present invention increases by about 7% or more compared to the conventional liquid crystal display device.

Therefore, it is possible to increase the aperture ratio and luminance by reducing the conventional number of odd-numbered blocks to even-numbered blocks.

However, in the liquid crystal display according to the first embodiment of the present invention, the second pixel electrode 164 overlaps the first and second auxiliary common wirings 118a and 118b to form a side storage capacitor. On the other hand, the first pixel electrode 162 does not overlap the first and second auxiliary common wirings 118a and 118b and does not form a side storage capacitor.

Accordingly, a difference in capacity of the storage capacitor occurs between the first and second pixel electrodes 162 and 164, which is a difference in data charging and holding between the first and second pixel electrodes 262. Causes. Accordingly, a difference in luminance may occur and image quality may deteriorate.

An embodiment of the present invention capable of solving the deviation of the storage capacitor will be described with reference to the drawings.

-Second Example-

4 is a plan view of an array substrate for a liquid crystal display device according to a second embodiment of the present invention, and FIGS. 5 and 6 are cross-sectional views of an array substrate for a liquid crystal display device according to a second embodiment of the present invention. 4, 5, and 6 show one pixel area, FIG. 5 shows a cross section corresponding to the line V-V of FIG. 4, and FIG. 6 shows a cross section corresponding to the line VI-VI of FIG. 4.

4, 5, and 6, a gate wiring 212 made of a conductive material on a transparent insulating substrate 210, a first gate electrode 214, a second gate electrode 216, a common wiring ( 218), and first, second, and third dummy electrodes 219a, 219b, and 219c are formed.

The gate wiring 212 extends in the first direction, and the first and second gate electrodes 214 and 216 are connected to the gate wiring 212. The first and second gate electrodes 214 and 216 are formed as a part of the gate wiring 212 and may have a wider width than other portions of the gate wiring 212. Alternatively, the first and second gate electrodes 214 and 216 may extend from the gate wiring 212.

The common wiring 218 extends in the first direction and is positioned to be spaced apart from the gate wiring 212.

The first, second, and third dummy electrodes 219a, 219b, and 219c are positioned to be spaced apart from the gate wiring 212 and the common wiring 218. The first and second dummy electrodes 219a and 219b extend substantially along a second direction crossing the first direction and are parallel to each other. The first and second dummy electrodes 219a and 219b may have a bent portion at the center. The third dummy electrode 219c extends in the first direction to connect the first and second dummy electrodes 219a and 219b. In this case, the third dummy electrode 219c is connected to the bent portions of the first and second dummy electrodes 219a and 219b.

The substrate 210 may be made of glass or plastic. In addition, the gate wiring 212, the first and second gate electrodes 214 and 216, the common wiring 218, and the first, second and third dummy electrodes 219a, 219b, 219c are made of aluminum. However, it may be made of molybdenum, nickel, chromium, copper, or an alloy thereof, and may have a single layer or multilayer structure.

Subsequently, a gate insulating layer is formed on the gate wiring 212, the first and second gate electrodes 214 and 218, the common wiring 218, and the first, second and third dummy electrodes 219a, 219b, and 219c. 220) is formed and covers them. The gate insulating layer 220 may be made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ).

First and second semiconductor layers 222 and 224 are formed on the gate insulating layer 220. The first semiconductor layer 222 corresponds to the first gate electrode 214, and the second semiconductor layer 224 corresponds to the second gate electrode 216.

Each of the first and second semiconductor layers 222 and 224 includes first and second active layers 222a and 224a of intrinsic amorphous silicon and first and second ohmic contact layers 222b and 224b of impurity-doped amorphous silicon. ). Alternatively, the first and second semiconductor layers 222 and 224 may be formed of an oxide semiconductor. In this case, the first and second ohmic contact layers 222b and 224b are omitted, and corresponding to the first and second gate electrodes 214 and 216 above the first and second semiconductor layers 222 and 224 An etch stop layer may be formed.

In addition, first and second semiconductor patterns 226 and 228 are formed on the gate insulating layer 220 to be adjacent to the first and second dummy electrodes 219a and 219b, respectively. Each of the first and second semiconductor patterns 226 and 228 includes first patterns 226a and 228a of intrinsic amorphous silicon and second patterns 226b and 228b of impurity-doped amorphous silicon.

Next, first source and drain electrodes 233 and 234 are formed on the first semiconductor layer 222, and second source and drain electrodes 235 and 236 are formed on the second semiconductor layer 224. The first source and drain electrodes 233 and 234 are located on the first semiconductor layer 222 and spaced apart from the first gate electrode 214 as the center, and the first ohmic contact layer 222b is a first source and drain electrode. It has the same shape as (233, 234). In addition, the second source and drain electrodes 235 and 236 are located on the second semiconductor layer 224 and spaced apart from the second gate electrode 216 as the center, and the second ohmic contact layer 224b is provided with the second source and It has the same shape as the drain electrodes 235 and 236. The first active layer 222a between the first source and drain electrodes 233 and 234 and the second active layer 224a between the second source and drain electrodes 235 and 236 are exposed.

The first and second drain electrodes 234 and 236 overlap the common wiring 218 to form first and second storage capacitors, respectively. The overlapping portion of the common wiring 218 forms the first capacitor electrode of the first and second storage capacitors, and the overlapping portions of the first and second drain electrodes 234 and 236 are the first and second storage capacitors, respectively. 2 It forms a capacitor electrode. In this case, the overlapping portion of the common wiring 218 may have a wider width than other portions.

The first gate electrode 214, the first semiconductor layer 222, the first source electrode 233, and the first drain electrode 234 constitute a first thin film transistor, and the second gate electrode 216 and the second The semiconductor layer 224, the second source electrode 235, and the second drain electrode 236 form a second thin film transistor. The first active layer 222a exposed between the first source and drain electrodes 233 and 234 becomes a channel of the first thin film transistor, and the second active layer 222a exposed between the second source and drain electrodes 235 and 236 The layer 224a becomes a channel of the second thin film transistor.

Here, the channels of the first and second thin film transistors may have a curved line shape. In more detail, the first and second source electrodes 233 and 235 have a shape in which two or more U-shaped shapes are connected, and the first and second drain electrodes 234 and 236 have a fork shape, The first source and drain electrodes 233 and 234 and the second source and drain electrodes 235 and 236 may be alternately disposed. Accordingly, the channels of the first and second thin film transistors may have a wave shape. Since the channels of the first and second thin film transistors having such a shape have a large channel width-length ratio (W/L), the driving current can be increased, and the liquid crystal capacitor can be quickly charged.

However, the shape of the channels of the first and second thin film transistors is not limited thereto and may vary.

Meanwhile, first and second data lines 231 and 232 are formed on the first and second semiconductor patterns 226, respectively. The first and second data lines 231 and 232 substantially extend along the second direction and cross the gate line 212 to define a pixel region. The first and second data lines 231 and 232 have portions bent with respect to the center of the pixel area.

The first data line 231 is connected to the first source electrode 233, the second data line 232 is connected to the second source electrode 235, and the first source electrode 233 is connected to the first data line It extends from 231, and the second source electrode 235 extends from the second data line 232. Alternatively, the first and second source electrodes 233 and 235 may be formed as part of the first and second data lines 232, respectively.

The first, second and third dummy electrodes 219a, 219b, 219c are located between the first and second data lines 231 and 232 to be spaced apart from the first and second data lines 231 and 232, The first and second dummy electrodes 219a and 219b are parallel to the first and second data lines 231 and 232.

The first and second source electrodes 233 and 235, the first and second drain electrodes 234 and 236, and the first and second data lines 231 and 232 are aluminum or molybdenum. , Nickel, chromium, copper, or an alloy thereof, and may have a single-layer or multi-layer structure.

Here, the first and second semiconductor layers 222 and 224, the first and second source electrodes 233 and 235, the first and second drain electrodes 234 and 236, and the first and second data lines ( 231 and 232 are formed through the same photolithography process using one mask, and accordingly, the first and second semiconductor layers 222 and 224 under the first and second data lines 231 and 232 are the same as those of the first and second semiconductor layers 222 and 224. First and second semiconductor patterns 226 and 228 are formed of a material. At this time, the first source and drain electrodes 233 and 234 and the first data line 231 have a width narrower than that of the first semiconductor layer 222 and the first semiconductor pattern 226, so that the first semiconductor layer 222 And an upper surface of the edge of the first semiconductor pattern 226 may be exposed by the first source and drain electrodes 233 and 234 and the first data line 231. In addition, the second source and drain electrodes 235 and 236 and the second data line 232 have a width narrower than that of the second semiconductor layer 224 and the second semiconductor pattern 228, so that the second semiconductor layer 224 And the upper surface of the edge of the second semiconductor pattern 228 may be exposed by the second source and drain electrodes 235 and 236 and the second data line 232.

In contrast, the first and second semiconductor layers 222 and 224 include first and second source electrodes 233 and 235, first and second drain electrodes 234 and 236, and first and second data. It may be formed through a different photolithography process using a mask different from the wirings 231 and 232. In this case, the side surfaces of the first semiconductor layer 222 are covered with the first source and drain electrodes 233 and 234, 2 The side surfaces of the semiconductor layer 224 are covered with second source and drain electrodes 235 and 236, and the first and second semiconductor patterns 226 and 228 under the first and second data lines 231 and 232 Can be omitted.

Next, the first and second source electrodes 233 and 235, the first and second drain electrodes 234 and 236, and a first passivation layer 240 on the first and second data lines 231 and 232 ) Is formed. The first protective layer 240 may be formed of an inorganic insulating material of silicon _{oxide (SiO 2) or silicon nitride (SiNx).}

A second protective layer 250 is formed on the first protective layer 240. The second passivation layer 250 has a flat surface, and the first contact hole 250a exposing the first drain electrode 234 together with the first passivation layer 240 and the second drain electrode 236 are exposed. It has a second contact hole 250b. The second protective layer 250 may be made of photo acryl.

In addition, the second passivation layer 250 has a third contact hole 250c exposing the second dummy electrode 219b. Although not shown, the third contact hole 250c is also formed in the first protective layer 240 and the gate insulating layer 220.

Here, one of the first and second protective layers 240 and 250 may be omitted.

A first pixel electrode 262 and a second pixel electrode 264 are formed in the pixel area above the second passivation layer 250. Each of the first pixel electrode 262 and the second pixel electrode 264 includes a plurality of patterns substantially extending along the second direction and spaced apart from each other along the first direction. The pattern of the second pixel electrode 264 is alternately disposed to be spaced apart from the pattern of the first pixel electrode 262 along the first direction. Each pattern of the first pixel electrode 262 and the second pixel electrode 264 is bent with respect to the center of the pixel area, so that it has a certain angle with respect to the second direction, and passes through the center of the pixel area along the first direction. It has a structure that is substantially symmetric with respect to an imaginary line. Here, the first pixel electrode 262 and the second pixel electrode 264 may be bent at an angle of 45 degrees or less with respect to the second direction.

The first pixel electrode 262 and the second pixel electrode 264 may be formed of a transparent conductive material such as indium tin oxide or indium zinc oxide.

Meanwhile, the pattern of the second pixel electrode 264 adjacent to the second data line 232 has an extension portion 264a. The extension part 264a overlaps the common wiring 218 and the second drain electrode 236 and contacts the second drain electrode 236 through the second contact hole 250b.

Also, the first pixel connection part 263 and the second pixel connection part 265 are formed of the same material on the same layer as the first pixel electrode 262 and the second pixel electrode 26. The first pixel connection part 263 and the second pixel connection part 265 extend in the first direction and are respectively located on opposite sides of the pixel area. The first pixel connector 263 is connected to one end of the patterns of the first pixel electrode 262, overlaps the common wiring 218 and the first drain electrode 234, and passes through the first contact hole 250a. It contacts the first drain electrode 234.

In addition, the second pixel connector 265 is connected to one end of the patterns of the second pixel electrode 264. The second pixel connector 265 or the second pixel electrode 264 contacts the second dummy electrode 219b through the third contact hole 250c, and the first, second, and third dummy electrodes 219a and 219b are formed. , 219c is applied with the same voltage as the second pixel electrode 264.

Alternatively, the third contact hole 250c may expose the first dummy electrode 219a, and the second pixel connector 265 or the second pixel electrode 264 may be formed through the third contact hole 250c. One dummy electrode 219a may be in contact.

In the array substrate for a liquid crystal display device according to the second embodiment of the present invention, first and second pixel electrodes 262 and 264 are formed in one pixel region, and the first and second pixel electrodes 262 and 264 are formed through the first and second thin film transistors. Liquid crystal molecules are driven by voltages applied to the second pixel electrodes 262 and 264, respectively. Therefore, it is possible to drive the liquid crystal molecules with a high voltage, and the response speed of the liquid crystal molecules can be increased. However, the second embodiment of the present invention is not limited to high voltage driving, and may also be used for low voltage driving. In this case, the voltage difference between the first and second pixel electrodes 262 and 264 is between the conventional pixel electrode and the common electrode. Corresponds to the voltage difference.

Meanwhile, in the array substrate for a liquid crystal display according to the second embodiment of the present invention, a block is defined between the pattern of the adjacent first pixel electrode 262 and the pattern of the second pixel electrode 264, The pixel area includes a plurality of blocks.

Here, one pixel region includes an even number of blocks. For example, the number of blocks may be 4. Therefore, compared to the conventional five blocks, the number of blocks can be reduced to increase the aperture ratio and luminance. The number of patterns of the second pixel electrode 264 may be greater than the number of patterns of the first pixel electrode 262, for example, the number of patterns of the second pixel electrode 264 is 3, and the first pixel electrode 262 The number of patterns of may be 2.

At this time, the first and second dummy electrodes 219a and 219b are formed on the same layer as the common wiring 218, and the first and second dummy electrodes 219a and 219b are provided with the first and second data lines 231, It is spaced apart from 232 and overlaps the second pixel electrode 264. The first and second dummy electrodes 219a and 219b reduce vertical crosstalk between the first and second data lines 231 and 232 and the first and second pixel electrodes 264, and a black matrix (not shown). The margin of (not shown) can be reduced, and thus the aperture ratio can be increased.

The first and second dummy electrodes 219a and 219b are separated from the common wiring 218 and electrically separated, and are electrically connected to the second pixel electrode 264 to receive the same voltage.

Accordingly, a storage capacitor is provided between the first and second dummy electrodes 219a and 219b and the first pixel electrode 262 and between the first and second dummy electrodes 219a and 219b and the first pixel electrode 262. Does not occur. Accordingly, the deviation of the storage capacitor with respect to the first and second pixel electrodes 262 and 264 is eliminated, so that the difference in data charging and holding between the first and second pixel electrodes 262 and 264 is reduced. By preventing, it is possible to prevent image quality defects due to differences in luminance.

Here, the third dummy electrode 219c is formed to pass through the bent portions of the first and second pixel electrodes 262 and 264 to connect the first and second dummy electrodes 219a and 219b without lowering the aperture ratio, In addition, light leakage due to disclination in the bent portions of the first and second pixel electrodes 262 and 264 may be prevented.

7 is a circuit diagram of a liquid crystal display device according to a second embodiment of the present invention.

As shown in FIG. 7, a plurality of gate wirings GL1, GL2, GL3, and GL4 extend in a first direction, and a plurality of data wirings DL1, DL2, and DL3 extend in a second direction. The gate wirings GL1, GL2, GL3, GL4 and the data wirings DL1, DL2, and DL3 cross each other to define a pixel region. At this time, two gate wires GL1, GL2, GL3, GL4 form a pair, and one pixel region is defined by crossing the two data wires DL1, DL2, and DL3, and a pair of gate wires GL1 and GL2 One pixel area is located in an area surrounded by the two data lines DL1, DL2, and DL3 adjacent to each other, GL3 and GL4.

Accordingly, four pixel regions may be defined by two pairs of gate lines GL1, GL2, GL3, and GL4 and three data lines DL1, DL2, and DL3.

First and second thin film transistors T1 and T2 and a liquid crystal capacitor Clc connected thereto are positioned in each pixel region. In addition, first and second storage capacitors Cst1 and Cst2 are connected to each of the first and second thin film transistors T1 and T2.

The liquid crystal capacitor Clc includes a first pixel electrode (not shown) and a second pixel electrode (not shown), and the first and second pixel electrodes are first and second thin film transistors T1 and T2, respectively. Is connected to One end of the first and second storage capacitors Cst1 and Cst2 is connected to the first and second pixel electrodes of the liquid crystal capacitor Clc, respectively, and the other end is connected to the common wiring Vcom.

The first and second thin film transistors T1 and T2 in one pixel area are connected to the same gate lines GL1, GL2, GL3, and GL4. Also, the first and second thin film transistors T1 and T2 in one pixel area are connected to different data lines DL1, DL2, and DL3.

In this case, the thin film transistors T1 and T2 in the pixel region adjacent along the first direction are connected to different gate lines GL1, GL2, GL3, and GL4. That is, among the pixel regions located between the first and second gate wires GL1 and GL2, the first and second thin film transistors T1 and T2 of the first pixel region are connected to the second gate wire GL2. The first and second thin film transistors T1 and T2 in the second pixel region are connected to the first gate line GL1.

Meanwhile, the thin film transistors T1 and T2 of the pixel regions positioned between the third and fourth gate lines GL3 and GL4 are also alternately connected to the third and fourth gate lines GL3 and GL4 for each pixel area. In this case, the order of connection may be the same as that of the thin film transistors T1 and T2 of the pixel regions positioned between the first and second gate lines GL1 and GL2, or may be reversed.

-Third Example-

8 is a plan view of an array substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and has the same structure as the array substrate of the second exemplary embodiment except for dummy electrodes, and descriptions of the same portions are omitted or simplified.

As shown in FIG. 8, a gate wiring 212 is formed along a first direction, first and second data wirings 231 and 232 are formed along a second direction, and the gate wiring 212 and the second The first and second data lines 231 and 232 cross each other to define a pixel area.

In addition, a common wiring 218 is formed along the first direction, and the common wiring 218 is positioned to be spaced apart from the gate wiring 212.

First and second thin film transistors connected thereto are formed at intersections of the gate wiring 212 and the first and second data lines 231 and 232. The first thin film transistor includes a first gate electrode 214, a first semiconductor layer (not shown), a first source electrode 233, and a first drain electrode 234, and the second thin film transistor is a second thin film transistor. A gate electrode 216, a second semiconductor layer (not shown), a second source electrode 235, and a first drain electrode 236 are included.

The first gate electrode 214 and the second gate electrode 216 are connected to the gate wiring 212. The first source electrode 233 is connected to the first data line 231, and the second source electrode 235 is connected to the second data line 232. The first drain electrode 234 is positioned to be spaced apart from the first source electrode 233, and the second drain electrode 236 is positioned to be spaced apart from the second source electrode 235. The first and second drain electrodes 234 and 236 overlap the common wiring 218 to form first and second storage capacitors, respectively.

A first semiconductor layer is positioned between the first gate electrode 214 and the first source and drain electrodes 233 and 234, and a first semiconductor layer is positioned between the second gate electrode 216 and the second source and drain electrodes 235 and 236. 2 The semiconductor layer is located.

A first pixel electrode 262 and a second pixel electrode 264 are positioned in the pixel area. Each of the first pixel electrode 262 and the second pixel electrode 264 includes a plurality of patterns substantially extending along the second direction and spaced apart from each other along the first direction. The pattern of the second pixel electrode 264 is alternately disposed to be spaced apart from the pattern of the first pixel electrode 262 along the first direction. Each pattern of the first pixel electrode 262 and the second pixel electrode 264 is bent with respect to the center of the pixel area, so that it has a certain angle with respect to the second direction, and passes through the center of the pixel area along the first direction. It has a structure that is substantially symmetric with respect to an imaginary line.

The first pixel connection part 264 and the second pixel connection part 265 extend in the first direction and are respectively located on opposite sides of the pixel area. The first pixel connector 264 is connected to one end of the patterns of the first pixel electrode 262 and contacts the first drain electrode 234 through the first contact hole 250a. The second pixel connector 265 is connected to one end of the patterns of the second pixel electrode 264.

In addition, the pattern of the second pixel electrode 264 adjacent to the second data line 232 has an extension portion 264a. The extension part 264a overlaps the common wiring 218 and the second drain electrode 236 and contacts the second drain electrode 236 through the second contact hole 250b.

Meanwhile, in the pixel region, the first, second, and third dummy electrodes 319a, 319b, and 319c are spaced apart from the gate wiring 212 and the common wiring 218, and the first and second data wirings 231 and 232. Located. The first, second, and third dummy electrodes 319a, 319b, and 319c may be formed of the same material on the same layer as the common wiring 218.

The first and second dummy electrodes 319a and 319b extend substantially in the second direction and are parallel to the first and second data lines 231 and 232. The first and second data lines 231 and 232 and the first and second dummy electrodes 319a and 319b may have a bent portion at the center.

Here, the second pixel connector 265 or the second pixel electrode 264 contacts the second dummy electrode 319b through the third contact hole 250c, and the first, second, and third dummy electrodes 219a , 219b and 219c are applied with the same voltage as the second pixel electrode 264.

Meanwhile, the third dummy electrode 319c extends in the first direction to connect the first and second dummy electrodes 319a and 319b. In this case, the third dummy electrode 319c overlaps the second pixel connector 265. The area where the second pixel connector 265 is located corresponds to a black matrix (not shown), and the aperture ratio does not decrease even if the third dummy electrode 319c is overlapped with the second pixel connector 265.

As described above, in the third embodiment of the present invention, the first and second dummy electrodes 318a and 319b can be connected without lowering the aperture ratio by overlapping the third dummy electrode 319c with the second pixel connector 265.

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

210: substrate 212: gate wiring
214, 216: first and second gate electrodes 216: common wiring
219a, 219b, 219c: first, second, and third dummy electrodes
220: gate insulating layers 222, 224: first and second semiconductor layers
226, 228: first and second semiconductor patterns 231, 232: first and second data wiring
233, 235: first and second source electrodes 234, 236: first and second drain electrodes
240: first protective layer 250: second protective layer
250a, 250b, 250c: first, second, and third contact holes
262: first pixel electrode 263: first pixel connector
264: second pixel electrode 264a: extension part
265: second pixel connector

Claims (8)

A substrate;
A gate wire positioned on the substrate and extending in a first direction;
First and second data lines extending in a second direction and crossing the gate lines to define a pixel area;
A common wiring spaced apart from the gate wiring and extending along the first direction;
First and second dummy electrodes adjacent to the first and second data lines, respectively, positioned on the same layer as the common wiring, and spaced apart from the common wiring;
A first thin film transistor connected to the gate line and the first data line;
A second thin film transistor connected to the gate line and the second data line;
A first pixel electrode positioned in the pixel region and connected to the first thin film transistor;
A second pixel electrode located in the pixel region and connected to the second thin film transistor
Including,
The first and second dummy electrodes overlap the second pixel electrode and are applied with the same voltage as the second pixel electrode.
The method of claim 1,
The patterns of the first pixel electrode and the patterns of the second pixel electrode are alternately arranged, a block is defined between the pattern of the adjacent first pixel electrode and the pattern of the second pixel electrode, and the pixel region is An array substrate for a liquid crystal display device comprising a block.
The method of claim 2,
An array substrate for a liquid crystal display device in which the number of patterns of the second pixel electrode is greater than the number of patterns of the first pixel electrode.
The method of claim 1,
Further comprising a third dummy electrode connecting the first and second dummy electrodes,
One of the first and second dummy electrodes is in contact with the second pixel electrode.
The method of claim 4,
The first and second pixel electrodes have bent portions,
The third dummy electrode is an array substrate for a liquid crystal display device passing through a bent portion of the first and second pixel electrodes.
The method of claim 4,
A first pixel connector connecting one end of the patterns of the first pixel electrode;
A second pixel connector connecting one end of the patterns of the second pixel electrode
Including more,
The third dummy electrode is an array substrate for a liquid crystal display device overlapping the second pixel connection part.
The method of claim 1,
The first and second dummy electrodes are spaced apart from the first pixel electrode.
The method of claim 1,
The first and second dummy electrodes are formed on the same layer as the gate wiring.

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