KR101995368B1 - Thin film transistor array panel and liquid crystal display device including the same - Google Patents

Thin film transistor array panel and liquid crystal display device including the same Download PDF

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KR101995368B1
KR101995368B1 KR1020120025560A KR20120025560A KR101995368B1 KR 101995368 B1 KR101995368 B1 KR 101995368B1 KR 1020120025560 A KR1020120025560 A KR 1020120025560A KR 20120025560 A KR20120025560 A KR 20120025560A KR 101995368 B1 KR101995368 B1 KR 101995368B1
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pixel
voltage
electrode
thin film
film transistor
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KR1020120025560A
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Korean (ko)
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KR20130104223A (en
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임용운
김성운
장주녕
박영롱
신동철
신철
홍성환
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삼성디스플레이 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Abstract

The present invention relates to a thin film transistor array panel and a liquid crystal display including the same, which can stably drive the liquid crystal to prevent the generation of foreground lines and improve transmittance. The thin film transistor array panel according to an embodiment of the present invention includes a substrate; A dummy electrode formed on the substrate; A first insulating layer formed on the dummy electrode; And a first pixel electrode and a second pixel electrode which are formed to face each other on the insulating layer.

Description

Thin film transistor array panel and liquid crystal display including the same {THIN FILM TRANSISTOR ARRAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a thin film transistor array panel and a liquid crystal display including the same. More particularly, a thin film transistor array panel and a liquid crystal display including the same may be used to stably drive a liquid crystal to prevent generation of foreground lines and to improve transmittance. It is about.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. It generates an electric field in the liquid crystal layer to determine the orientation of the liquid crystal molecules of the liquid crystal layer and to control the polarization of the incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

The liquid crystal display is classified into various modes according to a driving method, and among them, a liquid crystal display having a vertically aligned mode in which a long axis of the liquid crystal molecules is arranged perpendicular to the display panel without an electric field applied thereto. The contrast ratio is high and the reference viewing angle is wide.

In the vertically aligned liquid crystal display, when two electrodes are applied to different pixels in one pixel on the same substrate, the liquid crystal is unstable at the center between the two electrodes, resulting in a foreground line. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a thin film transistor array panel capable of stably driving liquid crystals and a liquid crystal display device including the same.

Another object of the present invention is to provide a thin film transistor array panel capable of preventing the generation of foreground lines and improving transmittance and a liquid crystal display including the same.

According to the above object, a thin film transistor array panel according to an embodiment of the present invention includes a substrate; A dummy electrode formed on the substrate; An insulating layer formed on the dummy electrode; And a first pixel electrode and a second pixel electrode which are formed to face each other on the insulating layer.

The dummy electrode may include a first dummy electrode formed under the first pixel electrode; And a second dummy electrode formed under the second pixel electrode, wherein the first dummy electrode and the second dummy electrode are spaced apart from each other.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a gate line formed on the substrate to transfer a gate signal; A voltage transfer line formed on the substrate to transfer a first pixel voltage; A data line formed on the substrate to transfer a second pixel voltage; A dummy line formed on the substrate to transfer an auxiliary voltage; A first thin film transistor connected to the gate line and the voltage transfer line; And a second thin film transistor connected to the gate line and the data line, wherein the first pixel electrode is connected to the first thin film transistor, and the second pixel electrode is connected to the second thin film transistor. The first and second dummy electrodes may be connected to the dummy line.

The first pixel voltage and the second pixel voltage may have the same magnitude and opposite polarities.

The auxiliary voltage may swing positively and negatively every frame.

When the auxiliary voltage is the positive polarity, it may be 1V or more and 7V or less.

When the auxiliary voltage is negative, the auxiliary voltage may be -7V or more and -1V or less.

The width of the first dummy electrode may be wider than the width of the first pixel electrode, and the width of the second dummy electrode may be wider than the width of the second pixel electrode.

The gate line and the data line may cross each other to define a pixel area, and the first and second pixel electrodes may be formed in the pixel area.

The pixel area includes a first subpixel area and a second subpixel area, and an interval between the first and second pixel electrodes formed in the first subpixel area is formed in the second subpixel area. The distance between the first and second pixel electrodes may be different.

The auxiliary voltage may be a voltage of a constant magnitude.

The difference between the first pixel voltage and the auxiliary voltage may be greater than or equal to -7.5V and less than or equal to 0V.

The difference between the second pixel voltage and the auxiliary voltage may be 7.5V or more and 15V or less.

Widths of the first and second pixel electrodes may be 2 μm or less.

Widths of the first and second pixel electrodes may be 0.2 μm or less.

The width of the first pixel electrode may be less than or equal to the width of the first dummy electrode.

The width of the second pixel electrode may be less than or equal to the width of the second dummy electrode.

The first pixel voltage may be greater than or equal to −4 V and less than or equal to −2 V, and the maximum value of the second pixel voltage may be greater than or equal to 11 V and less than or equal to 13 V.

A second insulating layer is formed between the substrate and the dummy electrode. The dielectric constant of the first insulating layer may be greater than or equal to the dielectric constant of the second insulating layer.

The display device may further include a third insulating layer formed on the first and second pixel electrodes, and the dielectric constant of the third insulating layer may be greater than or equal to the dielectric constant of the first insulating layer.

The first and second dummy electrodes may be floating.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a gate line formed on the substrate to transfer a gate signal; A voltage transfer line formed on the substrate to transfer a first pixel voltage; A data line formed on the substrate to transfer a second pixel voltage; A dummy line formed on the substrate to transfer an auxiliary voltage; A first thin film transistor connected to the gate line and the voltage transfer line; And a second thin film transistor connected to the gate line and the data line, wherein the first pixel electrode is connected to the first thin film transistor, and the second pixel electrode is connected to the second thin film transistor. The dummy electrode may be connected to the dummy line.

The gate line and the data line may cross each other to define a pixel area, and the dummy electrode may be formed in the entire pixel area.

The first and second pixel voltages, the auxiliary voltage

Figure 112012020236538-pat00001
(Vd1: first pixel voltage, Vd2: second pixel voltage, Va: auxiliary voltage).

According to an aspect of the present invention, a thin film transistor array panel includes a first substrate and a second substrate facing each other; A gate line formed on the first substrate to transfer a gate signal; A voltage transfer line formed on the first substrate to transfer a first pixel voltage; A data line formed on the first substrate to transfer a second pixel voltage; A dummy line formed on the first substrate to transfer an auxiliary voltage; A first thin film transistor connected to the gate line and the voltage transfer line; A second thin film transistor connected to the gate line and the data line; A first pixel electrode connected to the first thin film transistor; A second pixel electrode connected to the second thin film transistor so as to face the first pixel electrode; A dummy electrode connected to the dummy line and formed under the first and second pixel electrodes; And a liquid crystal layer formed between the first substrate and the second substrate, having a positive dielectric anisotropy and vertically aligned.

The first pixel voltage and the second pixel voltage have the same magnitude, opposite polarities, and the auxiliary voltage swings positively and negatively every frame, and is 1V or more when the auxiliary voltage is positive. , 7V or less, and when the auxiliary voltage is negative, -7V or more and -1V or less.

The auxiliary voltage may be a voltage having a constant magnitude, and the difference between the first pixel voltage and the auxiliary voltage is greater than or equal to -7.5V and less than or equal to 0V, and the difference between the second pixel voltage and the auxiliary voltage is greater than or equal to 7.5V and less than or equal to 15V. have.

The thin film transistor array panel and the liquid crystal display including the same according to the exemplary embodiment of the present invention as described above have the following effects.

A thin film transistor array panel and a liquid crystal display including the same according to an exemplary embodiment of the present invention form a dummy electrode under a first pixel electrode and a second pixel electrode, thereby forming a thin film at a central portion between the first pixel electrode and the second pixel electrode. There is an effect that can prevent the liquid crystal is driven unstable.

In addition, the thin film transistor array panel and the liquid crystal display including the same according to an exemplary embodiment of the present invention limit the range of the auxiliary voltage or the relationship between the auxiliary voltage and the first and second pixel voltages, thereby preventing the generation of foreground lines and transmitting the transmittance. There is an effect to improve.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram illustrating one pixel together with the structure of a liquid crystal display according to an exemplary embodiment of the present invention.
3 is a schematic cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.
4 is a layout view illustrating one pixel of the liquid crystal display according to the first exemplary embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating one pixel of the liquid crystal display according to the first exemplary embodiment of the present invention, taken along the line VV of FIG. 4.
6 is a layout view illustrating one pixel of the liquid crystal display according to the second exemplary embodiment of the present invention.
7 is a layout view illustrating one pixel of the liquid crystal display according to the third exemplary embodiment of the present invention.
8 is a cross-sectional view illustrating one pixel of the liquid crystal display according to the third exemplary embodiment of the present invention, taken along the line VIII-VIII of FIG. 7.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram illustrating one pixel together with the structure of the liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, and a data driver 500. And a gray voltage generator 800 and a signal controller 600.

The liquid crystal panel assembly 300 includes a plurality of signal lines (not shown) and a plurality of pixels PX connected thereto and arranged in a substantially matrix form. In contrast, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The plurality of signal lines includes a plurality of gate lines for transmitting a gate signal (also referred to as a "scan signal"), a plurality of data lines for transmitting a data signal, and a voltage transmission line for transmitting a constant voltage or a swinging voltage. The gate lines extend approximately in the row direction and are substantially parallel to each other, and the data lines and the voltage transfer lines extend substantially in the column direction and are substantially parallel to each other.

Referring to FIG. 2, each pixel PX includes a liquid crystal capacitor Clc. The liquid crystal capacitor Clc includes a first pixel electrode PEa and a second pixel electrode PEb of the lower panel 100. As a terminal, the liquid crystal layer 3 between the first and second pixel electrodes PEa and PEb functions as a dielectric.

The liquid crystal layer 3 has dielectric anisotropy, and the liquid crystal molecules of the liquid crystal layer 3 may be aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field.

The pixel electrode PE including the first and second pixel electrodes PEa and PEb may be formed on different layers or on the same layer.

In the first and second storage capacitors Csta and Cstb, which serve as an auxiliary role of the liquid crystal capacitor Clc, a separate electrode (not shown) provided in the lower display panel 100 includes the first and second pixel electrodes PEa. , PEb) may be formed to overlap each other with an insulator interposed therebetween.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue, or yellow, cyan, magenta, and the like. In addition, each pixel may further display a mixed color of the primary colors or white in addition to the primary colors. 2 illustrates a color filter CF in which each pixel PX represents one of the primary colors in an area of the upper panel 200 corresponding to the first and second pixel electrodes PEa and PEb. It shows the equilibrium. Unlike FIG. 2, the color filter CF may be disposed above or below the first and second pixel electrodes PEa and PEb of the lower panel 100.

The liquid crystal panel assembly 300 is provided with at least one polarizer (not shown).

Next, the driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2 along with FIG. 3.

3 is a schematic cross-sectional view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a data voltage may be applied to one of the first pixel electrode PEa and the second pixel electrode PEb, and a predetermined voltage or two swinging voltages may be alternately applied to the other. Alternatively, two voltages having the same size and opposite polarities may be applied to the first pixel electrode PEa and the second pixel electrode PEb.

The difference between the two voltages applied to the first pixel electrode PEa and the second pixel electrode PEb is represented as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. When a potential difference occurs between both ends of the liquid crystal capacitor Clc, as shown in FIG. 3, an electric field parallel to the surfaces of the two display panels 100 and 200 may cause a liquid crystal between the first pixel electrode PEa and the second pixel electrode PEb. Is produced in layer (3).

When the liquid crystal molecules 31 have positive dielectric anisotropy, the liquid crystal molecules 31 are inclined such that their major axis is parallel to the direction of the electric field, and the degree of inclination depends on the magnitude of the pixel voltage. This liquid crystal layer 3 is referred to as an electrically-induced optical compensation (EOC) mode. In addition, the degree of change in polarization of light passing through the liquid crystal layer 3 varies according to the degree of inclination of the liquid crystal molecules 31. This change in polarization is represented by a change in the transmittance of light by the polarizer, whereby the pixel PX displays a desired luminance.

Hereinafter, a liquid crystal display according to a first exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a layout view of one pixel of the liquid crystal display according to the first exemplary embodiment of the present invention, and FIG. 5 is a view of one pixel of the liquid crystal display according to the first exemplary embodiment of the present invention shown along the line VV of FIG. It is sectional drawing shown.

The liquid crystal display according to the first exemplary embodiment of the present invention includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200. .

The lower panel 100 intersects the first substrate 110 made of glass or plastic, the gate line 121, the dummy line 181, and the gate line 121 formed in one direction on the first substrate 110. The first thin film transistor TFT1, the gate line 121, and the data line 171 connected to the voltage transfer line 170 and the data line 171, the gate line 121, and the voltage transfer line 170 formed. The second thin film transistor TFT2 connected to each other, the first pixel electrode 191a connected to the first thin film transistor TFT1, the second pixel electrode 191b connected to the second thin film transistor TFT2, and the dummy line 181. The dummy electrode 182 is connected thereto.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. A first gate electrode 124a and a second gate electrode 124b protruding from the gate line 121 are formed on the first substrate 110. The first and second gate electrodes 124a and 124b are formed. ) Is applied to the gate signal through the gate line 121.

Although not shown, a storage electrode line and a storage electrode protruding from the storage electrode line may be further formed on the same layer as the gate line 121.

A gate insulating layer 140 is formed on the entire surface of the first substrate 110 including the gate line 121, the first gate electrode 124a, and the second gate electrode 124b. The gate insulating layer 140 may be made of silicon nitride (SiNx), silicon oxide (SiOx), or the like.

A first semiconductor 154a and a second semiconductor 154b made of hydrogenated amorphous or polycrystalline silicon are formed on the gate insulating layer 140. The first semiconductor 154a and the second semiconductor 154b are positioned on the first gate electrode 124a and the second gate electrode 124b, respectively.

A pair of first ohmic contacts 163a and 165a are formed on the first semiconductor 154a, and a pair of second ohmic contacts 163b and 165b are formed on the second semiconductor 154b. Formed. The second ohmic contacts 163b and 165b may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide.

The voltage transmission line 170 transmits the first pixel voltage and mainly extends in the vertical direction to cross the gate line 121. The data line 171 transfers the second pixel voltage, extends in parallel with the voltage transfer line 170, and crosses the gate line 121.

The first pixel voltage may be a voltage having a constant magnitude or a swinging voltage, and the second pixel voltage may be a data voltage. Alternatively, the first pixel voltage and the second pixel electrode may be two voltages having the same magnitude and opposite polarities.

Although not shown, the liquid crystal display according to the present exemplary embodiment may include a plurality of pixels, and the voltage transmission line 170 may be disposed for each of at least three pixels arranged adjacent to each other in the row direction of the pixels. . In this case, at least two first source electrodes 173a of the three pixels may be connected to the voltage transmission line 172 through a connection member (not shown) to receive a signal from the voltage transmission line 172. Therefore, one voltage transfer line 172 may transfer voltage to at least three pixel columns.

The first source electrode 175a protruding from the voltage transmission line 170 and the first drain electrode 175a spaced apart from the first source electrode 173a are disposed on the first ohmic contacts 163a and 165a. Formed. In this case, the first source electrode 173a may be formed to be bent in a U shape. In addition, the first semiconductor 154a may be formed under the voltage transmission line 170 as well as under the first source electrode 173a and the first drain electrode 175a.

A second source electrode 173b protruding from the data line 171 and a second drain electrode 175b spaced apart from the second source electrode 173b are formed on the second ohmic contacts 163b and 165b. In this case, the second source electrode 173b may be formed to be bent in a U shape. In addition, the second semiconductor 154b may be formed under the data line 171 as well as under the second source electrode 173b and the second drain electrode 175b.

The first gate electrode 124a, the first source electrode 173a, and the first drain electrode 175a form the first thin film transistor TFT1 together with the first semiconductor 154a and form the first thin film transistor TFT1. A channel is formed in the first semiconductor 154a between the first source electrode 173a and the first drain electrode 175a.

The second gate electrode 124b, the second source electrode 173b, and the second drain electrode 175b form a second thin film transistor TFT2 together with the second semiconductor 154b and form a second thin film transistor TFT2. The channel is formed in the second semiconductor 154b between the second source electrode 173b and the second drain electrode 175b.

A second insulating layer 180 is formed on the entire surface of the first substrate 110 including the first thin film transistor TFT1 and the second thin film transistor TFT2. The second insulating layer 180 may be made of an inorganic insulating material or an organic insulating material.

The dummy line 181 is formed on the second insulating layer 180. The dummy line 181 transmits an auxiliary voltage, and is mainly formed to extend in a horizontal direction and have a direction parallel to the gate line 121. The auxiliary voltage may be a voltage swinging positively and negatively every frame. Alternatively, the auxiliary voltage may be a voltage of a constant magnitude.

The dummy electrode 182 is connected to the dummy line 181 and protrudes from the dummy line 181 to have a long rod shape. The gate line 121 and the data line 171 may cross each other to define a plurality of pixel regions, and the dummy electrode 182 may be formed in the pixel region. A plurality of dummy electrodes 182 protruding from the dummy line 181 may be formed, and the dummy electrodes 182 may be formed of the first dummy electrode 182a and the second dummy electrode 182b. The first dummy electrode 182a and the second dummy electrode 182b are alternately arranged and spaced apart from each other at regular intervals.

The first insulating layer 184 is formed on the entire surface of the first substrate 110 including the dummy electrode 182. The first insulating layer 184 may be made of an inorganic insulating material or an organic insulating material.

The first contact hole 185a is formed in the second insulating layer 180 and the first insulating layer 184 so that a part of the first drain electrode 175a is exposed, and a part of the second drain electrode 175b is formed. The second contact hole 185b is formed to be exposed.

A first pixel electrode 191a connected to the first drain electrode 175a through the first contact hole 185a and the second contact hole 185b are disposed on the first insulating layer 184. A second pixel electrode 191b connected to the second drain electrode 175b is formed.

The first and second pixel electrodes 191a and 191b are formed in the pixel area. The first pixel electrode 191a may be positioned on the first dummy electrode 182a, and the second pixel electrode 191b may be positioned on the second dummy electrode 182b. The width w 2 of the first dummy electrode 182a may be wider than the width w 1 of the first pixel electrode 191a. In addition, the width w 4 of the second dummy electrode 182b may be wider than the width w 3 of the second pixel electrode 191b.

The first pixel electrode 191a and the second pixel electrode 191b are formed to face each other in a long bar shape. The first pixel electrode 191a and the second pixel electrode 191b may be formed in plural in one pixel area, and the first pixel electrode 191a and the second pixel electrode 191b are alternately disposed. In FIG. 3, two first pixel electrodes 191a and two second pixel electrodes 191b are formed and alternately arranged. Two first pixel electrodes 191a are connected to each other and two second pixels are connected to each other. The electrodes 191b are connected to each other. The number of the first pixel electrode 191a and the second pixel electrode 191b formed in one pixel area is appropriate in consideration of the size of the pixel area, the width of the first and second pixel electrodes 191a and 191b, and the transmittance. You can choose to.

Referring to Table 1 below, the narrower the width of the first pixel electrode 191a and the second pixel electrode 191b, the higher the transmittance.

Table 1 shows the transmittance according to the width of the first and second pixel electrodes 191a and 191b. The relative transmittance when the width of the first and second pixel electrodes 191a and 191b is 3 μm is 100%.

Width (um) of the first and second pixel electrodes 0.2 One 2 3 5 Transmittance (%) 150 122.2 110 100 84.6

The transmittance can be greatly improved by setting the width of the first and second pixel electrodes 191a and 191b to 0.2 μm or less. Therefore, it is preferable to form the width of the first and second pixel electrodes 191a and 191b to 0.2um or less.

However, in consideration of process difficulties in implementing the first and second pixel electrodes 191a and 191b of 0.2 μm or less, the thickness may be 0.2 μm or more and 2 μm or less.

That is, the widths of the first and second pixel electrodes 191a and 191b are preferably 2 μm or less, and more preferably 0.2 μm or less.

The width of the first and second pixel electrodes 191a and 191b may be implemented only in the process, but the narrower width is more advantageous in terms of transmittance, so the lower limit thereof is not limited.

Next, referring to Table 2, it can be seen that the transmittance becomes higher when the widths of the first and second pixel electrodes 191a and 191b are smaller than the widths of the first and second dummy electrodes 182a and 182b. .

Table 2 shows the transmittance according to the ratio of the widths of the first and second pixel electrodes 191a and 191b to the widths of the first and second dummy electrodes 182a and 182b. The relative transmittance when the width of the first and second pixel electrodes 191a and 191b and the width of the first and second dummy electrodes 182a and 182b are the same is shown as 100%.

Width of the first and second pixel electrodes / width of the first and second dummy electrodes 3/5 3/4 One 3/2 Transmittance (%) 106.2 104.7 100 97.7

The smaller the ratio of the widths of the first and second pixel electrodes 191a and 191b to the widths of the first and second dummy electrodes 182a and 182b is, the higher the transmittance is. Therefore, the width of the first and second pixel electrodes 191a and 191b is preferably smaller than or equal to the width of the first and second dummy electrodes 182a and 182b.

In the description of Tables 1 and 2 above, the width of the first pixel electrode 191a and the width of the second pixel electrode 191b are the same, and the width of the first dummy electrode 182a and the second dummy electrode are the same. Although described as forming the width of the same (182b), the present invention is not limited thereto. That is, the width of the first pixel electrode 191a may be different from the width of the second pixel electrode 191b, and the width of the first dummy electrode 182a may be different from the width of the second dummy electrode 182b. have.

The first and second pixel electrodes 191a and 191b may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a reflective metal such as aluminum, silver, chromium, or an alloy thereof.

Since the first pixel electrode 191a is electrically connected to the first drain electrode 175a, when the first thin film transistor TFT1 is turned on, the first pixel electrode 191a receives the first pixel voltage transmitted by the voltage transfer line 170. In addition, since the second pixel electrode 191b is electrically connected to the second drain electrode 175b, when the second thin film transistor TFT2 is turned on, the second pixel electrode 191b receives the second pixel voltage transmitted from the data line 171. . The first pixel electrode 191a and the second pixel electrode 191b form a liquid crystal capacitor Clc together with a portion of the liquid crystal layer 3 therebetween so that the first thin film transistor TFT1 and the second thin film transistor TFT2 are formed. The applied voltage is maintained even after it is turned off.

The first pixel voltage and the second pixel voltage may be voltages having the same magnitude and opposite polarities. For example, when the first pixel voltage is 7.5V, the second pixel voltage is -7.5V, and when the first pixel voltage is -7.5V, the second pixel voltage may be 7.5V.

In this case, an auxiliary voltage is applied to the dummy electrodes 182 formed under the first and second pixel electrodes 191a and 191b to be formed between the first pixel electrode 191a and the second pixel electrode 191b. The symmetry of the electric field is broken, which can prevent the generation of foreground lines. The auxiliary voltage may be a voltage swinging in the positive and negative polarities. It is most advantageous to improve the transmittance when the auxiliary voltage is in the range of 1 V or more and 7 V or less when the auxiliary voltage is positive, and in the range of -7 V or more and -1 V or less when the auxiliary voltage is negative.

In contrast, the first pixel voltage may be a voltage having a constant magnitude or a swinging voltage, and the second pixel voltage may be a data voltage. For example, when the first pixel voltage is -3V, the second pixel voltage is 12V, and when the first pixel voltage is 3V, the second pixel voltage may be -12V.

Referring to Table 3 below, it can be seen that the transmittance changes according to the setting of the first pixel voltage and the second pixel voltage.

Table 3 is a table showing transmittance according to the first and second pixel voltages. The relative transmittance when the first pixel voltage is -7.5V and the second pixel voltage is 7.5V is shown as 100%. The second pixel voltage is a value representing a white gray level in a normally black mode, and a different voltage may be used according to the gray level to be displayed.

First pixel voltage V -7.5 -5 -4 -3 -2 -One Second pixel voltage V 7.5 10 11 12 13 14 Transmittance (%) 100 101.4 103.0 103.4 103.2 102.4

The transmittance is high when the first pixel voltage has a value between -4V and -2V, and the second pixel voltage has a value between 11V and 13V. Therefore, it is preferable that the first pixel voltage is at least -4V and has a value of at most -2V, and the maximum value of the second pixel voltage is at least 11V and at most 13V.

In this case, the auxiliary voltage may be a voltage of a constant magnitude. The difference between the first pixel voltage and the auxiliary voltage is greater than or equal to -7.5 V and less than or equal to 0 V, and the difference between the second pixel voltage and the auxiliary voltage is greater than or equal to 7.5 V and less than or equal to 15 V is most advantageous to improve the transmittance.

In FIGS. 4 and 5, the plurality of first pixel electrodes 191a and the second pixel electrodes 191b are formed to have a predetermined interval, but the present invention is not limited thereto, and the plurality of first pixel electrodes 191a is not limited thereto. ) And the second pixel electrode 191b may be formed at different intervals.

For example, one pixel area may include a first subpixel area and a second subpixel area. The distance between the first pixel electrode 191a and the second pixel electrode 191b formed in the first subpixel area is defined by the first pixel electrode 191a and the second pixel electrode formed in the second subpixel area ( It may be formed narrower than the interval between 191b). In contrast, the distance between the first pixel electrode 191a and the second pixel electrode 191b formed in the first subpixel area is the first pixel electrode 191a and the second formed in the second subpixel area. It may be formed to be wider than the gap between the pixel electrodes 191b. In addition, one pixel area may be formed of three or more subpixel areas, and a gap between the first pixel electrode 191a and the second pixel electrode 191b may be formed differently in each subpixel area.

A third insulating layer 186 is formed on the entire surface of the first substrate 110 including the first and second pixel electrodes 191a and 191b. The third insulating layer 186 may be made of an inorganic insulating material or an organic insulating material.

Referring to Tables 3 and 4 below, the ratio of the dielectric constant of the first insulating layer 184 and the second insulating layer 180 and the ratio of the dielectric constant of the first insulating layer 184 and the third insulating layer 186. It can be seen that the transmittance is changed according to.

Table 3 is a table showing the transmittance according to the ratio of the dielectric constant of the third insulating layer 186 to the dielectric constant of the first insulating layer 184. The relative transmittance when the transmittance when the dielectric constant of the first insulating layer 184 and the third insulating layer 186 are the same is 100% is shown.

Table 4 is a table showing the transmittance according to the ratio of the dielectric constant of the first insulating layer 184 to the dielectric constant of the second insulating layer 180. The relative transmittance when the transmittance when the dielectric constant of the second insulating layer 180 and the first insulating layer 184 are equal to each other is 100% is shown.

Dielectric constant of third insulating layer / dielectric constant of first insulating layer 10 / 3.3 4 / 3.3 One 3.3 / 4 3.3 / 10 Transmittance (%) 101.3 100.2 100 99.8 98.7

As shown in Table 3, the larger the ratio of the dielectric constant of the third insulating layer 186 to the dielectric constant of the first insulating layer 184, the higher the transmittance. Therefore, it is preferable to form the dielectric constant of the third insulating layer 184 to be greater than or equal to the dielectric constant of the first insulating layer 184.

Dielectric constant of the first insulating layer / dielectric constant of the second insulating layer 100 / 3.3 10 / 3.3 4 / 3.3 One 3.3 / 4 3.3 / 10 Transmittance (%) 113.2 104.3 101 100 99 95.9

As shown in Table 4, as the ratio of the dielectric constant of the first insulating layer 184 to the dielectric constant of the second insulating layer 180 increases, the transmittance becomes higher. Therefore, it is preferable to form the dielectric constant of the first insulating layer 184 to be greater than or equal to the dielectric constant of the second insulating layer 180.

Although not illustrated, a lower alignment layer may be applied to an inner surface of the lower panel 100, and the lower alignment layer may be a vertical alignment layer. The polymer layer may be formed on the lower alignment layer, and the polymer layer may include polymer branches formed along the initial alignment direction of the liquid crystal molecules. The polymer layer may be formed by polymerizing by exposing a prepolymer such as a monomer, which is cured by a polymerization reaction by light such as ultraviolet light, to light. Can be adjusted.

The upper panel 200 includes a second substrate 210 made of glass, plastic, or the like, a light blocking member 220 and a color filter 230 formed on the second substrate 210. .

The light blocking member 220 is formed between two adjacent pixels and corresponding to a portion where the first and second thin film transistors TFT1 and TFT2 are formed, and serves to prevent light leakage.

The color filter 230 is mostly present in the area surrounded by the light blocking member 220, and may extend in the column direction of the plurality of pixel areas. Each color filter 230 may display one of three primary colors of red, green, and blue, or primary colors such as yellow, cyan, and magenta, and a plurality of other colors. Can be displayed. In addition, each pixel may further display a mixed color of the primary colors or white in addition to the primary colors.

The color filter 230 and the light blocking member 220 are formed on the upper panel 200, but at least one of the color filter 230 and the light blocking member 220 may be formed on the lower panel 100.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be formed of an organic insulating material, and prevents the color filter 230 from being exposed and provides a flat surface. In this case, the overcoat 250 may be omitted.

Although not illustrated, an upper alignment layer may be coated on an inner surface of the upper panel 200, and the upper alignment layer may be a vertical alignment layer. The polymer layer may also be formed on the upper alignment layer, and the polymer layer may include a polymer branch formed along the initial alignment direction of the liquid crystal molecules. The polymer layer may be formed by exposing a prepolymer such as a monomer that is cured by a polymerization reaction by light such as ultraviolet light to light, and may adjust the alignment force of the liquid crystal molecules according to the polymer branch.

Although not shown, polarizers may be provided on the outer surfaces of the lower and upper display panels 100 and 200.

The liquid crystal layer 3 interposed between the lower panel 100 and the upper panel 200 includes liquid crystal molecules 31 having positive dielectric anisotropy, and the liquid crystal molecules 31 have a long axis in the absence of an electric field. The display panels may be oriented perpendicular to the surfaces of the two display panels 100 and 200.

When voltages having different magnitudes are applied to the first pixel electrode 191a and the second pixel electrode 191b, an electric field that is substantially horizontal is generated on the surfaces of the lower and upper display panels 100 and 200. Then, the liquid crystal molecules of the liquid crystal layer 3 which were initially oriented perpendicular to the surfaces of the lower and upper display panels 100 and 200 are inclined in a direction horizontal to the direction of the electric field in response to the electric field. The degree of change in polarization of incident light in the liquid crystal layer 3 varies depending on the degree of inclination. This change in polarization is represented by a change in transmittance by the polarizer, through which the liquid crystal display displays an image.

Using the vertically aligned liquid crystal molecules 31 may increase the contrast ratio of the liquid crystal display and implement a wide viewing angle. In addition, the liquid crystal molecule 31 having positive dielectric anisotropy has a high dielectric constant anisotropy and a low rotational viscosity compared to the liquid crystal molecule having negative dielectric anisotropy, thereby obtaining a fast response speed.

Hereinafter, a liquid crystal display according to a second exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

The liquid crystal display according to the second embodiment is substantially the same as the liquid crystal display according to the first embodiment, and there is a difference in some portions. In this case, the biggest difference is that no dummy line is formed and no auxiliary voltage is applied, which will be described in more detail below.

6 is a layout view illustrating one pixel of the liquid crystal display according to the second exemplary embodiment of the present invention. A cross-sectional view of one pixel of the liquid crystal display according to the second exemplary embodiment of the present invention is similar to that of the first exemplary embodiment.

The liquid crystal display according to the second exemplary embodiment of the present invention includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200. Since the upper panel 200 and the liquid crystal layer 3 are the same as the liquid crystal display according to the first embodiment, description thereof will be omitted and the liquid crystal display according to the first embodiment of the components of the lower panel 100 may be omitted. Only the differences are described below.

The dummy electrode 182 is formed in a long bar shape in the pixel area. The dummy electrode 182 may include a first dummy electrode 182a and a second dummy electrode 182b. The first dummy electrode 182a and the second dummy electrode 182b are alternately arranged and spaced apart from each other at regular intervals. The first dummy electrode 182a and the second dummy electrode 182b are not connected to each other. In addition, the dummy electrode 182 may include a plurality of first dummy electrodes 182a and a plurality of second dummy electrodes 182b, and the plurality of first and second dummy electrodes 182a and 182b are connected to each other. It is not. That is, the first dummy electrode 182a and the second dummy electrode 182b are floating.

Since a separate dummy line is not formed and the plurality of dummy electrodes 182 are floating, no voltage is applied to the dummy electrode 182. The first insulating layer 184 is formed between the first dummy electrode 182a and the first pixel electrode 191a and between the second dummy electrode 182b and the second pixel electrode 191b.

In this case, the same effect as the predetermined voltage is applied to the first dummy electrode 182a according to the thickness of the first pixel voltage applied to the first pixel electrode 191a and the first insulating layer 184. In addition, the same effect as the predetermined voltage is applied to the second dummy electrode 182b according to the thickness of the second pixel voltage applied to the second pixel electrode 191b and the first insulating layer 184.

Accordingly, the thickness of the first insulating layer 184 may be adjusted to have the same effect as the voltage applied to the first and second dummy electrodes 182a and 182b, and the first pixel electrode 191a and the second pixel may be used. The symmetry of the electric field formed between the electrodes 191b is broken, thereby preventing the generation of foreground lines.

Hereinafter, a liquid crystal display according to a third exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

The liquid crystal display according to the third embodiment is substantially the same as the liquid crystal display according to the first embodiment, and there is a difference in some portions. In this case, the biggest difference is that the dummy electrode is formed in the entire pixel area, which will be described in more detail below.

FIG. 7 is a layout view illustrating one pixel of the liquid crystal display according to the third exemplary embodiment of the present invention, and FIG. 8 is a view of the liquid crystal display according to the third exemplary embodiment of the present invention shown along the line VIII-VIII of FIG. 7. It is sectional drawing which showed the pixel.

The liquid crystal display according to the third exemplary embodiment of the present invention includes a lower panel 100 and an upper panel 200 facing each other, and a liquid crystal layer 3 interposed between the two display panels 100 and 200. Since the upper panel 200 and the liquid crystal layer 3 are the same as the liquid crystal display according to the first embodiment, description thereof will be omitted and the liquid crystal display according to the first embodiment of the components of the lower panel 100 may be omitted. Only the differences are described below.

The dummy electrode 182 is formed in the entire pixel area. The pixel area may be defined as a quadrangular shape by the gate line 121 and the data line 171, and thus the dummy electrode 182 may also be formed as a substantially rectangular shape.

The dummy electrode 182 is formed under the first pixel electrode 191a and the second pixel electrode 191b, and is also formed in an area between the first pixel electrode 191a and the second pixel electrode 191b. That is, the first dummy electrode and the second dummy electrode are not separately formed, but are integrally formed.

The dummy line 181 is formed in a direction parallel to the gate line 121, and an auxiliary voltage is applied to the dummy line 181. Accordingly, an auxiliary voltage is applied to the dummy electrode 182 to break the symmetry of the electric field formed between the first pixel electrode 191a and the second pixel electrode 191b, thereby preventing the generation of foreground lines.

In this case, the first pixel voltage, the second pixel voltage, and the auxiliary voltage satisfying the condition of Equation 1 below are most advantageous for improving the transmittance.

Figure 112012020236538-pat00002

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

3: liquid crystal layer 31: liquid crystal molecules
100: lower display panel 110: first substrate
121: gate line 124a: first gate electrode
124b: second gate electrode 140: gate insulating film
154a: first semiconductor 154b: second semiconductor
163a and 165a: first ohmic contact 163b and 165b: second ohmic contact
170: voltage transmission line 171: data line
173a: first source electrode 173b: second source electrode
175a: first drain electrode 175b: second drain electrode
180: second insulating layer 181: dummy line
182: dummy electrode 182a: first dummy electrode
182b: second dummy electrode 184: first insulating layer
185a: first contact hole 185b: second contact hole
191a: first pixel electrode 191b: second pixel electrode
200: upper display panel 210: second substrate
220: light blocking member 230: color filter
250: overcoat 300: liquid crystal panel assembly
400: gate driver 500: data driver
800: gray voltage generator 600: signal controller
TFT1: first thin film transistor TFT2: second thin film transistor

Claims (27)

Board;
A dummy electrode formed on the substrate;
A first insulating layer formed on the dummy electrode; And
A first pixel electrode and a second pixel electrode formed to face each other on the first insulating layer;
The first pixel electrode and the second pixel electrode are located on the same layer,
The first pixel electrode receives a first pixel voltage, the second pixel electrode receives a second pixel voltage,
Generate an electric field parallel to the substrate by a potential difference between the first pixel voltage and the second pixel voltage,
The dummy electrode,
A first dummy electrode disposed below the first pixel electrode; And
A second dummy electrode positioned below the second pixel electrode;
The first dummy electrode, the second dummy electrode, the first pixel electrode and the second pixel electrode have an elongated bar shape.
The first dummy electrode and the second dummy electrode are spaced apart from each other,
The width of the first pixel electrode is less than or equal to the width of the first dummy electrode,
The width of the second pixel electrode is less than or equal to the width of the second dummy electrode,
Thin film transistor display panel.
delete According to claim 1,
A gate line formed on the substrate to transfer a gate signal;
A voltage transfer line formed on the substrate to transfer the first pixel voltage;
A data line formed on the substrate to transfer the second pixel voltage;
A dummy line formed on the substrate to transfer an auxiliary voltage;
A first thin film transistor connected to the gate line and the voltage transfer line; And
A second thin film transistor connected to the gate line and the data line;
The first pixel electrode is connected to the first thin film transistor,
The second pixel electrode is connected to the second thin film transistor,
The first and second dummy electrodes are connected to the dummy line,
Thin film transistor display panel.
The method of claim 3, wherein
Wherein the first pixel voltage and the second pixel voltage have the same magnitude and opposite polarities.
Thin film transistor display panel.
The method of claim 4, wherein
The auxiliary voltage swings positively and negatively every frame,
Thin film transistor display panel.
The method of claim 5,
1 V or more and 7 V or less when the auxiliary voltage is positive
Thin film transistor display panel.
The method of claim 6,
When the auxiliary voltage is the negative polarity is -7V or more, -1V or less,
Thin film transistor display panel.
delete The method of claim 3, wherein
The gate line and the data line cross each other to define a pixel area;
Wherein the first and second pixel electrodes are formed in the pixel region,
Thin film transistor display panel.
The method of claim 9,
The pixel area includes a first subpixel area and a second subpixel area,
The spacing between the first and second pixel electrodes formed in the first subpixel region is different from the spacing between the first and second pixel electrodes formed in the second subpixel region,
Thin film transistor display panel.
The method of claim 3, wherein
The auxiliary voltage is a voltage of a constant magnitude,
Thin film transistor display panel.
The method of claim 11, wherein
The difference between the first pixel voltage and the auxiliary voltage is greater than or equal to -7.5 V and less than or equal to 0 V,
Thin film transistor display panel.
The method of claim 12,
The difference between the second pixel voltage and the auxiliary voltage is greater than 7.5V, less than 15V,
Thin film transistor display panel.
The method of claim 1,
The width of the first and second pixel electrodes is less than 2um,
Thin film transistor display panel.
The method of claim 14,
The width of the first and second pixel electrodes is 0.2um or less,
Thin film transistor display panel.
delete delete The method of claim 1,
The first pixel voltage is greater than or equal to −4 V and less than or equal to −2 V,
The maximum value of the second pixel voltage is 11V or more and 13V or less,
Thin film transistor display panel.
The method of claim 1,
Further comprising a second insulating layer formed between the substrate and the dummy electrode,
The dielectric constant of the first insulating layer is greater than or equal to the dielectric constant of the second insulating layer,
Thin film transistor display panel.
The method of claim 19,
And a third insulating layer formed on the first and second pixel electrodes.
The dielectric constant of the third insulating layer is greater than or equal to the dielectric constant of the first insulating layer,
Thin film transistor display panel.
The method of claim 1,
The first and second dummy electrodes are floated and do not receive a voltage.
Thin film transistor display panel.
The method of claim 1,
A gate line formed on the substrate to transfer a gate signal;
A voltage transfer line formed on the substrate to transfer the first pixel voltage;
A data line formed on the substrate to transfer the second pixel voltage;
A dummy line formed on the substrate to transfer an auxiliary voltage;
A first thin film transistor connected to the gate line and the voltage transfer line; And,
A second thin film transistor connected to the gate line and the data line;
The first pixel electrode is connected to the first thin film transistor,
The second pixel electrode is connected to the second thin film transistor,
The dummy electrode is connected to the dummy line,
Thin film transistor display panel.
The method of claim 22,
The gate line and the data line cross each other to define a pixel area;
The dummy electrode is formed in the entire pixel region,
Thin film transistor display panel.
The method of claim 23, wherein
The first and second pixel voltages, the auxiliary voltage
Figure 112012020236538-pat00003
(Vd1: first pixel voltage, Vd2: second pixel voltage, Va: auxiliary voltage)
Satisfying,
Thin film transistor display panel.
A first substrate and a second substrate facing each other;
A gate line formed on the first substrate to transfer a gate signal;
A voltage transfer line formed on the first substrate to transfer a first pixel voltage;
A data line formed on the first substrate to transfer a second pixel voltage;
A dummy line formed on the first substrate to transfer an auxiliary voltage;
A first thin film transistor connected to the gate line and the voltage transfer line;
A second thin film transistor connected to the gate line and the data line;
A first pixel electrode connected to the first thin film transistor and receiving the first pixel voltage;
A second pixel electrode connected to the second thin film transistor to receive the second pixel voltage;
A dummy electrode connected to the dummy line and formed under the first and second pixel electrodes; And
A liquid crystal layer formed between the first substrate and the second substrate and vertically aligned;
The first pixel electrode and the second pixel electrode are located on the same layer,
Generate an electric field parallel to the substrate by a potential difference between the first pixel voltage and the second pixel voltage,
The dummy electrode,
A first dummy electrode disposed below the first pixel electrode; And
A second dummy electrode positioned below the second pixel electrode;
The first dummy electrode, the second dummy electrode, the first pixel electrode and the second pixel electrode have an elongated bar shape.
The first dummy electrode and the second dummy electrode are spaced apart from each other,
The width of the first pixel electrode is less than or equal to the width of the first dummy electrode,
The width of the second pixel electrode is less than or equal to the width of the second dummy electrode,
The liquid crystal molecules of the liquid crystal layer have positive dielectric anisotropy, and the long axes of the liquid crystal molecules are inclined to be parallel to the electric field direction.
Liquid crystal display.
The method of claim 25,
The first pixel voltage and the second pixel voltage have the same magnitude and opposite polarities,
The auxiliary voltage swings positively and negatively every frame,
1 V or more and 7 V or less when the auxiliary voltage is positive
When the auxiliary voltage is the negative polarity is -7V or more, -1V or less,
Liquid crystal display.
The method of claim 25,
The auxiliary voltage is a voltage of a constant magnitude,
The difference between the first pixel voltage and the auxiliary voltage is -7.5 V or more, 0 V or less,
The difference between the second pixel voltage and the auxiliary voltage is greater than 7.5V, less than 15V,
Liquid crystal display.
KR1020120025560A 2012-03-13 2012-03-13 Thin film transistor array panel and liquid crystal display device including the same KR101995368B1 (en)

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