KR20070075801A - Liquid crystal dispaly apparatus of line on glass type and fabricating method thereof - Google Patents

Abstract

An LOG(Line On Glass) type LCD and a method for manufacturing the same are provided to prevent the short defect within an LOG type signal line group, thereby minimizing brightness difference between horizontal blocs. Pixels, which are formed at crossings of gate lines and data lines, are arranged in a matrix type within an image display area. Gate ICs for driving gate lines are respectively mounted on a plurality of tape carrier packages. Data ICs for driving data lines are respectively mounted on a plurality of tape carrier packages. An LOG signal line group is formed in an outside area of the display area, wherein the LOG signal lines supply gate driving signals and control signals to the gate drive ICs. The LOG signal line group includes driving signal supply lines(31) for supplying gate driving signals to the gate ICs and control signal supply lines(33) for gate controlling signals to the gate ICs. The driving signal supply lines and the control signal supply lines overlap with an insulating layer(44) therebetween.

Description

Line on glass type liquid crystal display device and manufacturing method therefor {LIQUID CRYSTAL DISPALY APPARATUS OF LINE ON GLASS TYPE AND FABRICATING METHOD THEREOF}

1 is a plan view schematically showing the configuration of a conventional line on glass type liquid crystal display device.

FIG. 2 is a plan view specifically showing region A of FIG. 1. FIG.

3 is a plan view illustrating a part of a line on glass liquid crystal display according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along line II ′ of FIG. 3;

5A and 5B are plan views illustrating a method of manufacturing a line on glass liquid crystal display device according to an exemplary embodiment of the present invention.

6A and 6B are cross-sectional views illustrating a method of manufacturing a line on glass liquid crystal display device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1: liquid crystal panel 2: lower substrate

4: Upper board 8: Data TCP

10: data drive IC 12: data PCB

14: gate TCP 16: gate drive IC

18: data line 20: gate line

22, 28: gate drive signal transmission group

24: data TCP input pads 25: data TCP output pads

26: LOG signal line group 30: gate TCP output pads

31 driving signal supply lines 33 control signal supply lines

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and in particular, to prevent short defects in the LOG signal line group, and to reduce the line resistance of the LOG signal line group to minimize the luminance difference between the horizontal line blocks. A liquid crystal display device and a manufacturing method thereof.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the liquid crystal display device. It has a supply part. The timing controller controls the driving timing of the gate driver and the data driver and supplies the pixel data signal to the data driver. The power supply unit generates driving voltages, such as a common voltage Vcom, a gate high voltage Vgh, and a gate low voltage Vgl, which are required in the liquid crystal display using the input power. The gate driver sequentially supplies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, a data driver and a gate driver directly connected to the liquid crystal display panel are integrated into a plurality of integrated circuits (ICs). Each of the integrated data drive IC and the gate drive IC is mounted on a tape carrier package (TCP) and connected to a liquid crystal display panel by a tape automated bonding (TAB) method or mounted on a liquid crystal display panel by a chip on glass (COG) method. .

Here, the drive ICs connected to the liquid crystal display panel in a TAB manner through TCP receive control signals and DC voltages inputted from the outside through signal lines mounted on a PCB (Printed Circuit Board) connected to TCP, and interconnect with each other. do. In detail, the data drive ICs are connected in series through signal lines mounted on the data PCB, and are commonly supplied with control signals from the timing controller, pixel data signals, and driving voltages from the power supply unit. The gate drive ICs are connected in series through signal lines mounted on the gate PCB, and are commonly supplied with control signals from the timing controller and driving voltages from the power supply.

The drive ICs mounted on the liquid crystal display panel in the COG method are interconnected in a line on glass (hereinafter, LOG) method in which signal lines are mounted on the liquid crystal display panel, that is, the lower glass. Control signals and driving voltages are supplied.

Recently, even when the drive ICs are connected to the liquid crystal display panel by the TAB method, the liquid crystal display device can be further thinned by adopting the LOG method and removing the PCB. In particular, the gate PCB is removed by forming the signal lines connected to the gate drive ICs requiring relatively few signal lines on the liquid crystal display panel in a LOG method. In other words, TAB-type gate drive ICs are connected in series through signal lines mounted on the lower substrate of the liquid crystal display panel, and supply control signals and driving voltage signals (hereinafter, referred to as gate driving signals) in common. Will receive.

FIG. 1 is a plan view illustrating a conventional LOG type liquid crystal display device in which a gate PCB is removed, and FIG. 2 is a view specifically showing an area A of FIG. 1. FIG. 2 is a thin film transistor array substrate in a liquid crystal display panel for convenience of description. Only the plane of is shown)

The LOG type liquid crystal display device shown in FIGS. 1 and 2 includes a liquid crystal display panel 1, a plurality of data TCPs 8 connected between the liquid crystal display panel 1 and the data PCB 12, and a liquid crystal display. A plurality of gate TCPs 14 connected to the other side of the panel 1, data drive ICs 10 mounted on each of the data TCPs 8, and gates mounted on the gates TCP 14, respectively. Drive ICs 16.

The liquid crystal display panel 1 includes a lower substrate 2 having a thin film transistor array together with various signal lines, an upper substrate 4 having a color filter array formed therebetween, and a lower substrate 2 and an upper substrate 4. The injected liquid crystal is used as the configuration. The liquid crystal display panel 1 is provided with an image display area P1 composed of pixel cells Pixel formed at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads extended from the data line 18 and gate pads extended from the gate line 20 are positioned in the outer region of the lower substrate 2 positioned at the outer portion of the image display area P1. In addition, the LOG-type signal line group 26 for transmitting the gate driving and control signals supplied to the gate drive ICs 16 is located in the outer region of the lower substrate 2.

A data drive IC 10 is mounted on the data TCP 8, and input pads 24 and output pads 25 electrically connected to the data drive IC 10 are formed. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12, and the output pads 25 are electrically connected to the data pads on the lower substrate 2. In particular, the first data TCP 8 is further formed with a gate drive signal transmission group 22 electrically connected to the LOG signal line group 26 on the lower substrate 2. The gate driving signal transmission group 22 supplies the gate driving signals supplied from the timing controller and the power supply unit to the LOG type signal line group 26 via the data PCB 12.

The data drive ICs 10 convert a pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 18 on the liquid crystal display panel 1.

A gate drive IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28 and output pads 30 electrically connected to the gate drive IC 16 are formed. The gate driving signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the thin film transistor array substrate 2, and the output pads 30 are connected to the gate pads on the thin film transistor array substrate 2. Electrically connected.

The gate drive ICs 16 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines 20 in response to the input control signals. In addition, the gate drive ICs 16 supply the gate low voltage signal VGL to the gate lines 20 in the remaining period except for the period in which the gate high voltage signal VGH is supplied.

As shown in FIG. 2, the LOG signal line group 26 includes LOG signal lines 26a to 26h and a LOG signal line pad in contact with the gate driving signal transmission line group 28 of the gate TCP 14. As shown in FIG. LOG-type signal links, which are parallel to the gate lines 27 and the gate lines Gn and Gn + 1 and 20, and are positioned between the LOG-type signal lines 26a to 26h and the LOG-type signal line pads 27. 29).

The LOG signal lines 26a to 26h may include a gate high voltage signal supply line 26c for supplying a gate high voltage signal VGH to the gate drive IC 16, and a gate low voltage signal for the gate drive IC 16. A gate low voltage signal supply line 26a for supplying VGL, a common voltage signal VCOM supply line 26h for supplying a reference voltage to the pixel cell Pixel, and a ground voltage voltage signal GND supply line 26d. ), Drive signal supply lines supplied from the power supply unit such as the power supply voltage signal (VCC) supply line 26b, the gate start pulse (GSP) supply line 26g, and the gate shift clock signal (GSC) supply line 26f. And control signal supply lines for supplying each of the gate control signals supplied from the timing controller, such as a gate enable signal (GOE) supply line 26e.

The LOG signal line group 26 is formed of the same material as the gate line 20 and the like, and is formed side by side in a fine pattern in a limited narrow space of the outer region of the image display area P1. In particular, the LOG signal lines 26a to 26h have a relatively smaller spacing between the signal line 26a to 26h than the LOG signal line pads 27 and the LOG signal links 29 so that the process deviation is relatively small. The occurrence of a short occurs due to the like. In particular, in the bending area that separates the signal links 29 and the signal lines 26a to 26h, a short occurs frequently due to foreign matter during the process.

In addition, the line resistance is increased by forming the long signal lines 26a to 26h in a limited narrow space. That is, as the resistance value of the LOG signal line group 26 is proportional to the line length, the line resistance value increases as the distance from the data PCB 12 increases, thereby attenuating the gate driving signal. As a result, the gate driving signals transmitted through the LOG signal line group 26 are distorted by their line resistance values, thereby degrading the quality of the image displayed on the image display section 21.

In particular, as a difference occurs in the gate low voltage VGL supplied to the gate lines for each gate drive IC 16, a luminance difference occurs between horizontal regions connected to different gate drive ICs 16. As a result, a deterioration in image quality such as a horizontal line or a divided screen may appear in a boundary area between regions corresponding to each of the gate drive ICs 16.

Accordingly, an object of the present invention is to provide a LOG type liquid crystal display device capable of minimizing a luminance difference between horizontal line blocks by preventing short defects in the LOG type signal line group and reducing line resistance of the LOG type signal line group. It is to provide a manufacturing method.

In order to achieve the above object, a LOG liquid crystal display device according to the present invention includes an image display unit in which pixel cells formed at intersections of gate lines and data lines are arranged in a matrix form; A plurality of gate tape carrier packages each having a gate integrated circuit driving the gate lines; A plurality of data tape carrier packages each having data integrated circuits driving the data lines; And a line on glass type signal line group formed in an outer region of the image display unit to supply gate driving and control signals to the gate drive integrated circuits, wherein the line on glass type signal line group includes the line on glass type signal line group. Drive signal supply lines for supplying gate driving signals to gate integrated circuits and control signal supply lines for supplying gate control signals to the gate integrated circuits are formed to overlap each other with an insulating layer therebetween.

Each of the control signal supply lines overlaps with at least one of the driving signal supply lines.

The line on glass type signal line group is stacked on the substrate in order of the driving signal supply lines, the insulating film, and the control signal supply lines.

The driving signal supply lines are simultaneously formed of the same material as the gate line.

The control signal supply lines are simultaneously formed of the same material as the data line.

The driving signal supply lines include a gate high signal supply line, a gate low signal supply line, a common voltage signal supply line, a base voltage signal supply line, and a power supply voltage signal supply line.

The control signal supply lines include a gate start pulse supply line, a gate shift clock signal supply line, and a gate enable signal supply line.

The driving signal supply lines include at least one metal of chromium (Cr), molybdenum (Mo), and aluminum-based metal.

The control signal lines are characterized in that it comprises at least one metal of molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), aluminum-based metal.

The present invention provides a line-on-glass type signal line group for supplying gate driving and control signals to gate drive integrated circuits, which are located in an outer region of an image display unit in which pixel cells defined by gate lines and data lines are arranged in a matrix. A method of manufacturing a line-on-glass type liquid crystal display device comprising forming the line-on-glass type signal line group, wherein the forming of the line-on-glass type signal line group includes: a driving signal supply line for supplying a gate driving signal to the gate drive integrated circuits; Forming them; And forming control signal supply lines overlapping the driving signal supply lines with an insulating layer interposed therebetween and supplying a gate control signal to the gate drain integrated circuit.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6B.

1, 3, and 4 (the liquid crystal display of the present invention has the same plan view as that of the conventional liquid crystal display, and thus, the embodiment of the present invention will be described with reference to FIG. 1 which is a conventional plan view). The liquid crystal display device according to the embodiment of the present invention includes a liquid crystal display panel 1, a plurality of data TCPs 8 connected between the liquid crystal display panel 1 and the data PCB 12, and a liquid crystal display panel. A plurality of gate TCPs 14 connected to the other side of (1), data drive ICs 10 mounted on each of the data TCPs 8, and gate drives mounted on each of the gate TCPs 14; ICs 16 are provided.

The liquid crystal display panel 1 includes a thin film transistor array substrate 2 on which a thin film transistor array is formed together with various signal lines, a color filter array substrate 4 on which a color filter array is formed, a thin film transistor array substrate 2 and a color. The liquid crystal injected between the filter array substrate 4 is comprised. The liquid crystal display panel 1 is provided with an image display area P1 composed of pixel cells Pixel formed at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads extended from the data line 18 and gate pads extended from the gate line 20 are positioned in the outer region of the lower substrate 2 positioned at the outer portion of the image display area P1. Also, in the outer region of the lower substrate 2, a LOG type signal line group 26 for transmitting gate driving signals supplied to the gate drive ICs 16 is positioned.

A data drive IC 10 is mounted on the data TCP 8, and input pads 24 and output pads 25 electrically connected to the data drive IC 10 are formed. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12, and the output pads 25 are electrically connected to the data pads on the lower substrate 2. . In particular, the first data TCP 8 is further formed with a gate drive signal transmission group 22 electrically connected to the LOG signal line group 26 on the lower substrate 2. The gate driving signal transmission group 22 supplies the gate driving signals supplied from the timing controller and the power supply unit to the LOG type signal line group 26 via the data PCB 12.

The data drive ICs 10 convert a pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 18 on the liquid crystal display panel 1.

A gate drive IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28 and output pads 30 electrically connected to the gate drive IC 16 are formed. The gate driving signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the thin film transistor array substrate 2, and the output pads 30 are connected to the gate pads on the thin film transistor array substrate 2. Electrically connected.

The gate drive ICs 16 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines 20 in response to the input control signals. In addition, the gate drive ICs 16 supply the gate low voltage signal VGL to the gate lines 20 in a period other than the period in which the gate high voltage signal VGH is supplied.

The LOG signal line group 26 includes LOG signal lines 26a to 26h, LOG signal line pads 27 and gate lines in contact with the gate driving signal transmission line group 28 of the gate TCP 14. It is composed of LOG type signal links 29 which are parallel to (20) and located between LOG type signal lines 26a to 26h and LOG type signal line pads 27.

The LOG signal lines 26a to 26h may include a gate high voltage signal supply line 26c for supplying a gate high voltage signal VGH to the gate drive IC 16, and a gate low voltage signal for the gate drive IC 16. A gate low voltage signal supply line 26a for supplying VGL, a common voltage signal VCOM supply line 26h for supplying a reference voltage to the pixel cell Pixel, and a ground voltage voltage signal GND supply line 26d. ), The drive signal supply lines 31 supplied from the power supply unit, the gate start pulse (GSP) supply line 26g, and the gate shift clock signal (GSC) supply line, such as the power supply voltage signal (VCC) supply line 26b. 26f, control signal supply lines 33 for supplying each of the gate control signals supplied from the timing controller, such as the gate enable signal GOE supply line 26e.

Here, the driving signal supply lines 31 are formed of the same material as the gate line 20, and are formed with a relatively larger area than the driving signal supply lines of FIG. 2. Compared with FIG. 2, the space is relatively wider than the related art. At the same time, the control signal supply lines 33 are formed to overlap the driving signal supply lines 31 with the gate insulating layer 44 therebetween. Accordingly, the control signal supply lines 33 are also formed with a relatively large area as compared with the control signal supply lines 33 in FIG. 2, and the spacing therebetween is relatively wide.

Accordingly, it is possible to prevent the short defect in the LOG signal line group 26 and to reduce the line resistance of the LOG signal line group 26 to minimize the luminance difference between the horizontal line blocks.

This will be described in more detail as follows.

Conventionally, the LOG signal lines 26a to 26h are all formed at the same time as the gate line 20 with the same material as the gate line 20, and have a fine pattern in a limited narrow space of the outer region of the image display area P1. Formed side by side. Accordingly, short defects are frequently generated in the bending area that separates the signal links 29 and the signal lines 26a to 26h and the area of the signal lines 26a to 26h is reduced, resulting in an increase in line resistance. The display quality degradation problem occurred.

In order to solve such a conventional problem, in the present invention, when the image is implemented in the LOG signal line group 26, the control signal supply lines 33 which have less influence on image quality are regarded as data lines 18. It is formed from a source / drain metal such as. Accordingly, the LOG driving signal supply lines 31 and the control signal supply lines 33 may be overlapped.

As a result, the area occupied by the control signal supply lines 33 can be provided as the formation area of the drive signal supply lines 31, thereby making it possible to form a larger area of the drive signal supply lines 31 than in the prior art. In addition, the distance between the driving signal supply lines 31 can also be sufficiently spaced apart. As a result, short defects in the LOG signal line group 26 can be prevented.

At the same time, the area of the signal lines 26a to 26h of the LOG signal line group 26 is widened, so that the line resistance of the LOG signal line group 26 is reduced, so that each gate drive IC 16 is applied. The luminance difference between the corresponding horizontal regions can be minimized. As a result, image quality deterioration due to the luminance difference is minimized.

3 and 4, the gate low voltage signal supply line 26a and the gate enable signal GOE supply line 26e overlap each other with the gate insulating film 44 interposed therebetween to supply the power voltage signal VCC. The line 26b and the gate shift clock signal GSC supply line 26f overlap with the gate insulating film 44 interposed therebetween, and the gate high voltage signal supply line 26c and the gate start pulse GSP supply line 26g. ) Is overlapped with the gate insulating film 44 interposed therebetween. However, this is only one example.

That is, each of the control signal supply lines 33 overlaps any one of the drive signal supply lines 31 such that the control signal supply lines 33 and the drive signal supply lines 31 are on different planes. Once positioned, the effect will be sufficient. In addition, the widths of the control signal supply lines 33 and the drive signal supply lines 31 do not have to be exactly the same and do not need to be exactly overlapped. However, the entire line widths of the control signal supply lines 33 are formed so as not to leave the formation region of the drive signal supply lines 31.

Here, the driving signal supply lines 31 may be made of the same metal as the gate line 20. For example, the gate line metal may include aluminum-based metals such as chromium (Cr), molybdenum (Mo), and aluminum neodium (AlNd). And the like are used in a single layer or double layer structure.

As the material of the gate insulating film 44, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

The control signal supply lines 33 are made of the same metal as the data line 18, for example, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu) and aluminum as the source / drain metals. System metals and the like are used.

Hereinafter, the LOG type liquid crystal display and a manufacturing method thereof according to the present invention will be described with reference to FIGS. 5A to 6B.

First, the pixel cells Pix shown in FIG. 3 are formed in a matrix form on the lower substrate 2, and a LOG type signal line group 26 is formed in the outer region of the image display area P1.

5A and 6B illustrate a method of forming the LOG signal line group 26 in detail.

5A and 6A, after the gate metal layer is deposited on the lower substrate 2, the gate metal layer is patterned by a photolithography process and an etching process to simultaneously form the gate line 20 in the image display area P1. The drive signal supply lines 31 are formed in the outer region of the image display area P1. At the same time, LOG type drive signal signal links 29a are bent to be connected to the drive signal supply lines 31.

The drive signal supply lines 31 include a gate high voltage signal supply line 26c, a gate low voltage signal supply line 26a, a common voltage signal VCOM supply line 26h, and a ground voltage voltage signal GND supply line. 26d, a power supply voltage signal VCC supply line 26b is included.

The gate line 20 and the driving signal supply lines 31 include at least one of aluminum-based metals such as chromium (Cr), molybdenum (Mo), and aluminum neodium (AlNd).

A gate insulating film 44 is formed on the lower substrate 2 on which the gate line 20 and the driving signal supply lines 31 are formed.

Subsequently, referring to FIGS. 5B and 6B, after the source / drain metal layer is deposited on the lower substrate 2 on which the gate insulating layer 44 is formed, the source / drain metal layer is patterned by a photolithography process and an etching process. The data line 18 is formed in the display area P1 and the control signal supply lines 33 are formed in the outer area of the image display area P1. At the same time, LOG type control signal signal links 29b which are bent to the control signal supply lines 33 are also formed.

The control signal supply lines 33 include a gate start pulse (GSP) supply line 26g, a gate shift clock signal (GSC) supply line 26f, and a gate enable signal (GOE) supply line 26e.

 The source / drain metal may include at least one metal of molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), and aluminum-based metal.

Thereafter, a thin film transistor, a pixel electrode, and the like forming a pixel cell are formed, an upper substrate 4 having a color filter array is provided, and a bonding process of the upper substrate 4 and the lower substrate 2 is performed. The display panel 1 is formed.

Thereafter, the data TCP 8 mounted with the data drive IC 10 and the gate TCP 14 mounted with the gate drive IC 16 are attached to the liquid crystal display panel 1.

Accordingly, a LOG type liquid crystal display device as shown in Figs. 1 and 3 is formed.

As described above, the LOG type liquid crystal display device and the manufacturing method thereof according to the present invention form the control signal lines and the voltage signal lines of the LOG type signal line group so as to be sandwiched with a gate insulating film interposed therebetween. As a result, the area occupied by the control signal line can be provided as the formation region of the voltage signal lines, so that the area of the voltage signal lines can be formed wider than the conventional one, and the distance between the voltage signal lines can be sufficiently spaced. It becomes possible. As a result, short defects between the signal lines are prevented, and line resistance of the LOG signal line group is reduced, thereby minimizing the luminance difference between the horizontal line blocks.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (16)

An image display unit in which pixel cells formed at intersections of gate lines and data lines are arranged in a matrix; A plurality of gate tape carrier packages each having a gate integrated circuit driving the gate lines; A plurality of data tape carrier packages each having data integrated circuits driving the data lines; And a line-on-glass type signal line group formed in an outer region of the image display unit to supply gate driving and control signals to the gate drive integrated circuits. The line on glass type signal line group Line on, wherein the driving signal supply lines for supplying the gate driving signals to the gate integrated circuits and the control signal supply line for supplying the gate control signals to the gate integrated circuits overlap each other with an insulating film interposed therebetween. Glass type liquid crystal display device. The method of claim 1, And each of the control signal supply lines overlaps at least one of the driving signal supply lines. The method of claim 1, The line on glass type signal line group And a driving signal supplying line, an insulating film, and a control signal supplying line on the substrate. The method of claim 1, And the driving signal supply lines are formed of the same material as the gate line at the same time. The method of claim 1, And the control signal supply lines are formed of the same material as the data line at the same time. The method of claim 1, The drive signal supply lines A line on glass type liquid crystal display device comprising a gate high signal supply line, a gate low signal supply line, a common voltage signal supply line, a base voltage signal supply line, and a power supply voltage signal supply line. The method of claim 1, The control signal supply lines A line on glass type liquid crystal display device comprising a gate start pulse supply line, a gate shift clock signal supply line, and a gate enable signal supply line. The method of claim 6, And the driving signal supply lines include at least one of chromium (Cr), molybdenum (Mo), and aluminum-based metals. The method of claim 7, wherein The control signal lines may include at least one metal of molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), and aluminum-based metals. LCD display device. Forming a line-on-glass type signal line group for supplying gate driving and control signals to the gate drive integrated circuits by placing pixel cells defined by the gate line and the data line in an outer region of the image display unit arranged in a matrix form. In the method of manufacturing a line-on glass liquid crystal display device comprising: Forming the line on glass type signal line group Forming driving signal supply lines for supplying a gate driving signal to the gate drive integrated circuits; And forming control signal supply lines overlapping the driving signal supply lines with an insulating layer interposed therebetween and supplying a gate control signal to the gate drain integrated circuit. Manufacturing method. The method of claim 10, And the driving signal supply lines are formed of the same material as the gate line at the same time. The method of claim 10, And the control signal supply lines are formed of the same material as the data line at the same time. The method of claim 10, Forming the driving signal supply lines Forming a gate high signal line, a gate low signal line, a common voltage signal line, a ground voltage signal line, and a power supply voltage signal line. The method of claim 10, Forming the control signal supply lines Forming a gate start pulse supply line, a gate shift clock signal supply line, and a gate enable signal supply line. The method of claim 13, The driving signal supply lines may include at least one metal of chromium (Cr), molybdenum (Mo), and aluminum-based metal. The method of claim 14, The control signal supply lines may include at least one metal of molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy), copper (Cu), and aluminum-based metals. Method of manufacturing a type liquid crystal display device.

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