CN110689836A - GOA circuit and display panel - Google Patents
GOA circuit and display panel Download PDFInfo
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- CN110689836A CN110689836A CN201911008166.7A CN201911008166A CN110689836A CN 110689836 A CN110689836 A CN 110689836A CN 201911008166 A CN201911008166 A CN 201911008166A CN 110689836 A CN110689836 A CN 110689836A
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- 239000000463 material Substances 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 229910021654 trace metal Inorganic materials 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a GOA circuit and a display panel, wherein the GOA circuit comprises: a plurality of cascaded GOA units; a plurality of signal lines; and the connecting lines are used for connecting the GOA units and the corresponding signal lines to transmit signals, wherein equivalent resistance values of all the connecting lines are the same. According to the invention, through designing the equivalent resistance values of the connecting wires between all the GOA units and the corresponding signal wires to be the same, the input panel signals are prevented from being different when in optical alignment due to different resistance values of the connecting wires, the signal difference of the input panel when in optical alignment is effectively improved, the line defect in the horizontal direction is avoided, and the product yield of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a GOA circuit and a display panel.
Background
The GOA (Gate On Array, Array substrate row driver) circuit is fabricated On an Array substrate by using an Array substrate process of a display device. Because the GOA circuit replaces an external chip, the manufacturing procedure of the display device can be reduced, and the cost is reduced; meanwhile, grid chips can be saved, and the integration level of the display device is improved.
In the GOA display technology, a GOA circuit receives a start Signal (STV) and a clock signal (CK) from a driving circuit board, the GOA circuit is formed by a plurality of cascaded GOA units, each GOA unit sends a scanning signal to a display panel line by line through a gate line to turn on thin film transistors on an array substrate of the display panel line by line, thereby driving pixel units of the display panel to display gray scales.
In the GOA display technology, the progressive scanning process needs to output high levels to the gate lines in sequence, however, the lengths of the connection lines between the clock signal and the corresponding GOA units are different, which may cause the equivalent resistance to be different, and this resistance difference may cause the input panel signal to have a difference, and in severe cases, may cause horizontal line defects.
Referring to fig. 1, a signal circuit diagram of a conventional GOA circuit is shown. The GOA circuit of the conventional TV panel includes a plurality of GOA units 11, and is designed using a plurality of signal lines 12. In this embodiment, taking 8 clock signals CK 1-CK 8 as an example, the first-stage GOA unit generates the first-stage scanning signal G (1) according to the start signal STV and the clock signal CK1, the second-stage GOA unit generates the second-stage scanning signal G (2) according to the previous-stage scanning signal G (1) and the clock signal CK2, and so on, each 8 GOA units form a group, and the (8n +1) th-stage GOA unit generates the (8n +1) th-stage scanning signal G (8n +1) according to the previous-stage scanning signal G (8n) and the clock signal CK 1. The gate driving timing signals of the GOA circuit of this embodiment further include a Reset signal Reset, a power driving signal VSS, and control signals LC 1-LC 2.
Since the connection lines 19 between the signal lines 12 and the corresponding GOA cells 11 have equivalent resistance values, and the lengths of the connection lines 19 of the clock signals CK 1-CK 8 are different, the difference in resistance values may cause, for example, when performing optical alignment (HVA curing), the input panel signals have difference, and a horizontal line defect may be formed in a serious case.
Therefore, it is desirable to provide a GOA circuit to improve the optical alignment abnormality caused by the difference of the equivalent resistance of the traces transmitting the clock signals.
Disclosure of Invention
The present invention is directed to provide a GOA circuit and a display panel, which can improve the optical alignment abnormality caused by the different equivalent resistances of the routing lines for transmitting clock signals, in order to solve the problems of the existing routing structure of the GOA circuit.
To achieve the above object, the present invention provides a GOA circuit, including: a plurality of cascaded GOA units; a plurality of signal lines; and the connecting lines are used for connecting the GOA units and the corresponding signal lines to transmit signals, wherein equivalent resistance values of all the connecting lines are the same.
In order to achieve the above object, the present invention also provides a display panel, comprising; a display area; and the non-display area is provided with a GOA circuit, the GOA circuit is connected to the display area, and the GOA circuit adopts the GOA circuit provided by the invention.
The invention has the advantages that: by designing the equivalent resistance values of the connecting wires between all the GOA units and the corresponding signal wires to be the same, the condition that the input panel signals are different when in optical alignment due to different resistance values of the connecting wires is avoided, the difference of the input panel signals when in optical alignment (HVA curing) is effectively improved, the line defect in the horizontal direction is avoided, and the product yield of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a signal line of a conventional GOA circuit;
FIG. 2 is a schematic diagram of an embodiment of a signal line of a GOA circuit according to the present invention;
fig. 3 is a schematic diagram of a display panel according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The directional phrases used in this disclosure include, for example: up, down, left, right, front, rear, inner, outer, lateral, etc., are simply directions with reference to the drawings. The embodiments described below by referring to the drawings and directional terms used are exemplary only, are used for explaining the present invention, and are not construed as limiting the present invention.
The GOA circuit of the invention comprises: the GOA units are connected with the corresponding signal lines through the connecting lines, and the equivalent resistance values of all the connecting lines are the same. By designing the GOA circuit with the resistances of the connecting wires for transmitting signals, the situation that the input panel signals are different when the connecting wires are different in resistance is avoided, the difference of the input panel signals when the optical alignment (HVA curing) is effectively improved, the line defect in the horizontal direction is avoided, and the product yield of the display panel is improved.
Referring to fig. 2, a schematic diagram of a signal line of a GOA circuit according to an embodiment of the present invention is shown. The GOA circuit 20 of this embodiment includes a plurality of cascaded GOA units 21, a plurality of signal lines 22 and a plurality of connection lines 29; the connecting lines 29 are used to connect the GOA units 21 and the corresponding signal lines 22, and the equivalent resistance values of all the connecting lines 29 are the same. Since all the connecting lines 29 have the same equivalent resistance value, the equivalent resistance values are not different due to different lengths of the connecting lines 29, so that the input panel signals are not different during optical alignment, the input panel signal difference during optical alignment is effectively improved, the line defect in the horizontal direction is avoided, and the product yield of the display panel is improved.
In a further embodiment, the signal line 22 comprises a clock signal line for transmitting a clock signal. In the present embodiment, 4 clock signals CK1 to CK4 are taken as an example, that is, a design using a plurality of clock signals is adopted. The GOA unit of the first stage generates the scan signal G (1) of the first stage according to the start signal STV and the clock signal CK1, the GOA unit of the second stage generates the scan signal G (2) of the second stage according to the scan signal G (1) of the previous stage and the clock signal CK2, and so on, each 4 GOA units form a group, and the GOA unit of the (4n +1) th stage generates the scan signal G (4n +1) of the (4n +1) th stage according to the scan signal G (4n) of the previous stage and the clock signal CK 1. In other embodiments, the number of the signal lines 22 for transmitting the clock signal may also be 8, and the driving capability of the display panel can be adjusted for different GOAs, and the higher the driving capability is, the larger the number of the clock signals CK is.
The gate driving timing signals of the GOA circuit of this embodiment further include a Reset signal Reset, a power driving signal VSS, and control signals LC1 to LC 2. The control signals LC 1-LC 2 are used for controlling the GOA units to selectively output clock signals CK 1-CK 4 as gate driving signals. After the clock signals CK 1-CK 4, the control signals LC 1-LC 2 and the power driving signal VSS are input to the array substrate of the display panel from the driving circuit board, the GOA unit can be reached through the signal lines, so that the accurate control of each scanning line of the array substrate is realized.
In a further embodiment, the material used for all the connecting lines 29 is the same, for example, copper (Cu) or aluminum (Al).
In a further embodiment, all the connecting lines 29 are disposed in the same layer and have the same thickness. Since the signal line 22 far from the GOA unit 21 needs to cross over other signal lines 22 to transmit the corresponding clock signal to the corresponding GOA unit 21, the signal line 22 and the connection line 29 can be arranged in different layers, and the signal line 22 is connected to the corresponding GOA unit 21 through the connection line 29 by using a through hole, which is relatively simple and easy to implement, and the thickness of the display panel can be reduced.
In a further embodiment, the width of all the connecting lines 29 is proportional to the length thereof, so that the equivalent resistance of all the connecting lines 29 is the same under the condition of the same material and thickness.
Specifically, according to a resistance calculation formula: and R is rho L/S, wherein rho is the resistivity of the trace metal, L is the length of the trace, S is the cross section area of the trace metal, and S is D H (D is the width of the trace and H is the thickness of the trace metal). When the material (such as Cu or Al) of the wiring and the thickness of the film layer are determined, the resistivity rho of the wiring metal and the thickness H of the wiring metal are fixed; if the equivalent resistance of the wiring needs to be designed to be the same, the corresponding wiring width D needs to be designed according to the wiring length L, and the calculation formula of the wiring width D is as follows: d ═ ρ × L/(R × H).
As shown in fig. 2, from the clock signal CK1 to CK4, the trace lengths L1 to L4 of the connecting lines 29 are gradually shortened, so that the trace widths D1 to D4 of the corresponding connecting lines 29 are designed to be gradually narrowed, and therefore, under the condition of the same material and thickness, the equivalent resistance of all the connecting lines 29 is the same, so that there is no difference in the clock signals input to the panel during optical alignment, thereby avoiding the formation of horizontal line defects and improving the yield of the display panel.
Based on the same inventive concept, the invention also provides a display panel. Referring to fig. 2 to fig. 3, fig. 3 is a schematic diagram of a display panel according to an embodiment of the invention. The display panel includes; a display area 31; and a non-display area 32; the non-display area 32 is provided with a GOA circuit 20, the GOA circuit 20 is connected to the display area 31, and the GOA circuit 20 adopts the GOA circuit 20 shown in fig. 2. Specifically, the structure and the advantageous effects of the GOA circuit 20 are described in detail in the embodiment shown in fig. 2, and are not described herein again.
In a further embodiment, all the GOA units 21 are distributed on the same side of the display area 31, and all the signal lines 22 are disposed on a side of the GOA units 21 away from the display area 31 and are uniformly distributed along a direction away from the GOA units 21.
In a further embodiment, all the connection lines 29 are disposed in the same layer and are disposed in different layers from the signal lines 22. Since the signal line 22 far from the GOA unit 21 needs to cross over other signal lines 22 to transmit the corresponding clock signal to the corresponding GOA unit 21, the signal line 22 and the connection line 29 can be arranged in different layers, and the signal line 22 is connected to the corresponding GOA unit 21 through the connection line 29 by using a through hole, which is relatively simple and easy to implement, and the thickness of the display panel can be reduced.
The display panel adopting the GOA circuit avoids the difference of input panel signals during optical alignment caused by the different resistances of the connecting wires by designing the GOA circuit with the resistances of the connecting wires for transmitting signals and the like, effectively improves the difference of the input panel signals during optical alignment (HVA curing), avoids the line defect in the horizontal direction and improves the product yield of the display panel.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A GOA circuit, comprising:
a plurality of cascaded GOA units;
a plurality of signal lines; and
the connecting lines are used for connecting the GOA units and the corresponding signal lines to transmit signals, and the equivalent resistance values of all the connecting lines are the same.
2. The GOA circuit of claim 1, wherein all the GOA units are distributed on the same side of a display area of a display panel, and all the signal lines are disposed on a side of the GOA units away from the display area and are uniformly distributed along a direction away from the GOA units.
3. The GOA circuit of claim 1, wherein the signal lines comprise a clock signal line to transmit a clock signal.
4. A GOA circuit in accordance with claim 3, wherein the number of clock signal lines is 4 or 8.
5. A GOA circuit according to claim 1, characterized in that the material used for all the connection lines is the same.
6. A GOA circuit according to claim 1, characterized in that the material used for all the connection lines is copper or aluminum.
7. The GOA circuit of claim 1, wherein all the connecting lines are disposed in a same layer and have the same thickness.
8. The GOA circuit of claim 1, wherein the width of all of the connecting lines is proportional to their length.
9. A display panel, comprising;
a display area; and
the non-display area is provided with a GOA circuit, the GOA circuit is connected to the display area, and the GOA circuit adopts the GOA circuit as claimed in any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911008166.7A CN110689836A (en) | 2019-10-22 | 2019-10-22 | GOA circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911008166.7A CN110689836A (en) | 2019-10-22 | 2019-10-22 | GOA circuit and display panel |
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| Publication Number | Publication Date |
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| CN110689836A true CN110689836A (en) | 2020-01-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201911008166.7A Pending CN110689836A (en) | 2019-10-22 | 2019-10-22 | GOA circuit and display panel |
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| CN (1) | CN110689836A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111240114A (en) * | 2020-03-16 | 2020-06-05 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111584500A (en) * | 2020-04-27 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN112582431A (en) * | 2020-12-08 | 2021-03-30 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102393587A (en) * | 2011-11-10 | 2012-03-28 | 友达光电股份有限公司 | Signal wiring structure in GOA (gate driver on array) circuit of liquid crystal display |
| CN104793820A (en) * | 2015-03-31 | 2015-07-22 | 深圳市华星光电技术有限公司 | Self-capacitive touch screen structure, embedded touch screen and liquid crystal display |
| CN106991949A (en) * | 2015-12-30 | 2017-07-28 | 三星显示有限公司 | Display device |
| CN109243392A (en) * | 2018-10-22 | 2019-01-18 | 深圳市华星光电技术有限公司 | Horizontal drive circuit structure and display device |
-
2019
- 2019-10-22 CN CN201911008166.7A patent/CN110689836A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102393587A (en) * | 2011-11-10 | 2012-03-28 | 友达光电股份有限公司 | Signal wiring structure in GOA (gate driver on array) circuit of liquid crystal display |
| CN104793820A (en) * | 2015-03-31 | 2015-07-22 | 深圳市华星光电技术有限公司 | Self-capacitive touch screen structure, embedded touch screen and liquid crystal display |
| CN106991949A (en) * | 2015-12-30 | 2017-07-28 | 三星显示有限公司 | Display device |
| CN109243392A (en) * | 2018-10-22 | 2019-01-18 | 深圳市华星光电技术有限公司 | Horizontal drive circuit structure and display device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111240114A (en) * | 2020-03-16 | 2020-06-05 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111240114B (en) * | 2020-03-16 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111584500A (en) * | 2020-04-27 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN112582431A (en) * | 2020-12-08 | 2021-03-30 | 深圳市华星光电半导体显示技术有限公司 | GOA circuit and preparation method thereof |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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Application publication date: 20200114 |
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