CN103412427A - Liquid crystal display panel - Google Patents
Liquid crystal display panel Download PDFInfo
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- CN103412427A CN103412427A CN2013103513781A CN201310351378A CN103412427A CN 103412427 A CN103412427 A CN 103412427A CN 2013103513781 A CN2013103513781 A CN 2013103513781A CN 201310351378 A CN201310351378 A CN 201310351378A CN 103412427 A CN103412427 A CN 103412427A
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Abstract
The invention provides a liquid crystal display panel. A plurality of second thin film transistors TFT are arranged on a non-display area away from the side of a grid driver, and each second thin film transistor TFT corresponds to each scanning line of a display area. Second source electrodes of the second thin film transistors TFT are connected with the corresponding scanning lines of the display area, second grid electrodes of the second thin film transistors TFT are connected with corresponding second drain electrodes, and the second grid electrode ends of all the second thin film transistors TFT are connected. A circuit board is externally connected with the liquid crystal display panel, the second grid electrode ends of all the second thin film transistors are connected onto the circuit board through wires. By means of the liquid crystal display panel, the plurality of thin film transistors are added in the non-display area, the circuit board is externally connected with liquid crystal display panel, a circuit is arranged on the circuit board, signals on the circuit are input into an inner thin film transistor, and the thin film transistors controlling opening or closing of the non-display area is opened, so that pixel voltage of the display area can be discharged fast, and the problem of residual image in shutdown can be solved.
Description
Technical field
The present invention relates to a kind of be used to solving when liquid crystal display is shut down the display panels of storing image retention.
Background technology
When the dump of display panels, because all external voltages all make zero rapidly, source electrode and gate drivers stop action, the pixel voltage of display panels only depends on the Ioff(leakage current of TFT) discharge, because Ioff is very little, so pixel voltage can't fully discharge, and residual a large amount of electric charge is in pixel, and this phenomenon is referred to as the image retention that shuts down.
Fig. 1 is the drives schematic diagram of available liquid crystal display panel, display panels comprise array base palte and the color membrane substrates be oppositely arranged and be located in array base palte and color membrane substrates between liquid crystal, color membrane substrates is provided with color membrane electrode; Suppose that the array base palte horizontal direction has m bar sweep trace G(to be respectively G1, G2, G3 ... Gm), vertical direction has n bar data line S(S1, S2, S3 ... Sn) and the public electrode wire (not shown), be combined into the liquid crystal display of a n*m pixel.Sweep trace all is connected to gate drivers 10, data line S all is connected to source electrode driver 20; And sweep trace G intersects and limits a plurality of pixel cells with data line S, in each pixel cell, is equipped with pixel electrode and film crystal pipe unit TFT.
Public electrode wire is by forming memory capacitance Cs between fixed voltage Vcom and corresponding pixel cell; Between color membrane electrode and corresponding pixel electrode, form liquid crystal capacitance Clc.
When the power supply of display panels disconnects (Power off), can produce a control signal XAO, this control signal XAO is as the input signal of gate drivers 10.When gate drivers 10 receives the XAO signal, as shown in Figure 2, when if XAO is low level (Low), the all passages of gate drivers 10 (channel) will be exported high levle (VGH), VGH voltage can be opened (turn on) by all TFT in display panels, now pixel voltage just can, by the TFT externally electric discharge fast be opened, reach the purpose of improving the shutdown image retention.
When the LCD board size more and more large, resolution is more and more high, power supply turn off after in display panels each pixel want rapid discharge more and more difficult, be easy to cause the pixel electric discharge of the interior IC side away from gate drivers of display panels incomplete, even output HIGH voltage (VGH) is to all grid passages when shutdown, still can there is so-called shutdown image retention, be illustrated in figure 3 display panels shutdown image retention schematic diagram.
Have now and solve the shutdown image retention problem by control signal XAO, the XAO signal is high levle under normal circumstances, and when circuit detecting shuts down to power supply, the XAO signal can transfer low level to by high levle, this XAO signal by circuit board via COF(Chip On Flex, or, Chip On Film, normal claim to cover brilliant film) and the glass cabling be connected to the IC of gate drivers, after the IC of gate drivers receives the XAO signal, XAO must be converted to more high levle, and then export a high voltage (VGH) to all grid passages (Gate channels), the process that so transmits and change, exist the regular hour to postpone, be unfavorable for solving the shutdown image retention.
Therefore need a kind of new driving circuit of design to solve the shutdown image retention problem.
Summary of the invention
The object of the invention is to solve the display panels of shutdown image retention.
The invention provides a kind of display panels, comprise the array base palte that is oppositely arranged and the liquid crystal during color membrane substrates and sandwiched, described array base palte is provided with viewing area and non-display area, crisscross some sweep traces are set array base palte and data line, sweep trace intersect and limit a plurality of pixel cells with data line, in each pixel cell, be equipped with pixel electrode and the first film transistor T FT, this first film transistor T FT is positioned at viewing area; The side of display panels also is provided with the gate drivers be connected with sweep trace, the source electrode driver be connected with data line; On the non-display area away from the gate drivers side, also be provided with a plurality of the second thin film transistor (TFT) TFT, and each second thin film transistor (TFT) TFT is corresponding with each sweep trace of viewing area; The second thin film transistor (TFT) TFT is provided with second grid, the second source electrode and the second drain electrode, the second source electrode of the second thin film transistor (TFT) TFT is connected to the corresponding sweep trace of viewing area, the second grid of the second thin film transistor (TFT) TFT is connected to each other and is in the same place with corresponding the second drain electrode, and the second gate of the second all thin film transistor (TFT) TFT is extremely connected.
Wherein, display panels is an external circuit board also, and the second gate of all the second thin film transistor (TFT) TFT extremely is connected on this circuit board via cabling.
Wherein, on described gate drivers, input has control signal XAO.
Wherein, described circuit board is provided with voltage conversion circuit, and it is extreme that the output signal end of this voltage conversion circuit is connected to the second gate of the second thin film transistor (TFT) TFT.
Wherein, when input control signal was high levle, the output signal of voltage conversion circuit was low level, and the second thin film transistor (TFT) TFT all closes, and display panels maintains regular event; When power supply shuts down, input control signal is low level, and the output signal of voltage conversion circuit is high levle, and the second thin film transistor (TFT) TFT all opens, and high levle voltage inputs on the sweep trace of viewing area, and the first film transistor T FT is opened.
Wherein, described voltage conversion circuit comprises supply voltage VDD, high voltage VGH, the first low-voltage VGL1, the second low-voltage VGL2, input signal XAO, input signal
XAO, output signal OUT, four P-MOS pipe, four N-MOS pipes, be respectively: P-MOS1, P-MOS2, P-MOS3, P-MOS4, N-MOS1, N-MOS2, N-MOS3, N-MOS4, wherein, input signal XAO and input signal
XAOFor two opposite signals, P-MOS1 with
XAOSignal connects, and P-MOS2 is connected with the XAO signal; After P-MOS1 and P-MOS2 parallel connection, be connected with supply voltage VDD, P-MOS3 with and the P-MOS4 parallel connection after with high voltage VGH, be connected, after N-MOS1 and N-MOS2 parallel connection, be connected with the first low-voltage VGL1, N-MOS3 is connected with the second low-voltage VGL2 after the N-MOS4 parallel connection, P-MOS1 also is connected in series with N-MOS1, N-MOS2 and N-MOS4 respectively, P-MOS2 also is connected in series with N-MOS1, N-MOS2 and N-MOS3 respectively, and P-MOS3 and N-MOS4 are connected in series, and P-MOS4 and N-MOS3 are connected in series; And P-MOS3, P-MOS4, N-MOS4 all are connected to output signal OUT.
Wherein, when XAO is high levle High, P-MOS1, N-MOS2, P-MOS3, N-MOS4 conducting, output signal OUT is low-voltage VGL; When XAO is low level LOW, P-MOS2, N-MOS1, P-MOS4, N-MOS3 conducting, output signal OUT is high voltage VGH.
The present invention is by increasing a plurality of thin film transistor (TFT)s and an external circuit board at non-display area, circuit is set on circuit board, on thin film transistor (TFT) in the input of the signal on circuit, open closing or opening of the thin film transistor (TFT) of controlling non-display area, thereby make the pixel voltage rapid discharge of viewing area, solve the shutdown image retention problem.
The accompanying drawing explanation
Figure 1 shows that the drives schematic diagram for the available liquid crystal display panel;
Figure 2 shows that the waveform schematic diagram of sweep trace of the display panels of Fig. 1;
Figure 3 shows that display panels shutdown image retention schematic diagram;
Figure 4 shows that the drives schematic diagram of display panels of the present invention;
Figure 5 shows that Nverter circuit figure;
Figure 6 shows that the voltage conversion circuit figure of display panels of the present invention;
Figure 7 shows that the present invention be the XAO signal,
XAOSignal and output signal OUT waveform schematic diagram.
Embodiment
Below in conjunction with the drawings and specific embodiments, further illustrate the present invention, should understand these embodiment only is not used in and limits the scope of the invention be used to the present invention is described, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.
Figure 4 shows that the drives schematic diagram of display panels of the present invention, display panels comprise array base palte and the color membrane substrates be oppositely arranged and be located in array base palte and color membrane substrates between liquid crystal, color membrane substrates is provided with color membrane electrode; Array base palte is provided with viewing area and non-display area, suppose that the array base palte horizontal direction has m bar sweep trace G11(to be respectively G1, G2, G3 ... Gm), vertical direction has n bar data line S21(S1, S2, S3 ... Sn) and the public electrode wire (not shown), be combined into the liquid crystal display of a n*m pixel, and sweep trace 11 and data line 21 crisscross.The side of display panels also is provided with the gate drivers 10 be connected with sweep trace G, the source electrode driver 20 be connected with data line S; And sweep trace G intersects and limits a plurality of pixel cells with data line S, in each pixel cell, is equipped with pixel electrode and the first film transistor T FT30, and described the first film transistor T FT30 is positioned at viewing area.
Public electrode wire is by forming memory capacitance Cs between fixed voltage Vcom and corresponding pixel cell; Between color membrane electrode and corresponding pixel electrode, form liquid crystal capacitance Clc.
Display panels also is provided with a plurality of the second thin film transistor (TFT) TFT (Thin Film Transistor) on the non-display area away from gate drivers 10 sides (Non-Active Area), and is equipped with one second thin film transistor (TFT) TFT40 on each root sweep trace 11 of non-display area.
If the resolution of this display panels is 1920RGB*1080, represent that this display panels has 1080 sweep traces 11, need all increase by one second thin film transistor (TFT) TFT40 at these 1080 sweep traces 11, also namely: the second thin film transistor (TFT) TFT40 has 1080.
Newly-increased the second thin film transistor (TFT) TFT40 that is positioned at non-display area and the first film transistor T FT30 of viewing area are used same process and parameter, therefore the second newly-increased thin film transistor (TFT) TFT40 can't cause the complicated of processing procedure also can not increase cost.
Described first, second thin film transistor (TFT) TFT is three terminal components, and it includes grid (Gate), source electrode (Source) and drain electrode (Drain).The first source electrode that the first grid of described the first film transistor T FT30 connects corresponding sweep trace 11, described the first film transistor T FT30 connects corresponding data line 21, and the first drain electrode of described the first film transistor T FT30 connects corresponding pixel electrode; The second source electrode of the second thin film transistor (TFT) TFT40 is connected to the corresponding sweep trace 11 of viewing area, the second grid of the second thin film transistor (TFT) TFT40 is connected to each other and is in the same place with corresponding the second drain electrode, and the second gate of the second all thin film transistor (TFT) TFT40 is extremely connected, and the second gate of all the second thin film transistor (TFT) TFT40 extremely is connected on external circuit board 100 via cabling.
The drives schematic diagram of the display panels shown in Figure 1 of prior art, the control signal XAO inputted, by after a reverser, can obtain the signal opposite with control signal XAO, becomes
XAO.As shown in Figure 5, Nverter circuit is provided with a P type metal-oxide-semiconductor (P-MOS) and a N-type metal-oxide-semiconductor (N-MOS) to this Nverter circuit, and P-MOS is connected with supply voltage VDD, and N-MOS is connected with ground voltage GND.
When
XAODuring for Low (low level), XAO is High (high levle), and works as
XAODuring for High (high levle), XAO is Low (low level).
By XAO,
XAOWith 4 P-MOS, 4 N-MOS, be combined to form a voltage conversion circuit, this voltage conversion circuit as shown in Figure 6, can, by the XAO signal by the level of original GND to VDD, be transformed into the VGL(low-voltage) to the VGH(high voltage) level.
Described voltage conversion circuit is arranged on external circuit board 100, and voltage conversion circuit output OUT signal has the second grid of the second thin film transistor (TFT) TFT40 to display panels.
Voltage conversion circuit comprises supply voltage VDD, high voltage VGH, the first low-voltage VGL1, the second low-voltage VGL2, input signal XAO, input signal
XAO, output signal OUT, four P-MOS pipe, four N-MOS pipes, be respectively: P-MOS1, P-MOS2, P-MOS3 and P-MOS4; N-MOS1, N-MOS2, N-MOS3 and N-MOS4, wherein, after P-MOS1 and P-MOS2 parallel connection, be connected with supply voltage VDD, P-MOS3 with and the P-MOS4 parallel connection after with high voltage VGH, be connected, after N-MOS1 and N-MOS2 parallel connection, be connected with the first low-voltage VGL1, N-MOS3 is connected with the second low-voltage VGL2 after the N-MOS4 parallel connection, P-MOS1 also is connected in series with N-MOS1, N-MOS2 and N-MOS4 respectively, P-MOS2 also is connected in series with N-MOS1, N-MOS2 and N-MOS3 respectively, P-MOS3 and N-MOS4 are connected in series, and P-MOS4 and N-MOS3 are connected in series.And P-MOS3, P-MOS4, N-MOS4 all are connected to output signal OUT.
P-MOS1 with
XAOSignal connects, and P-MOS2 is connected with the XAO signal.
When XAO is High (high levle), P-MOS1, N-MOS2, P-MOS3, N-MOS4 conducting, output OUT is VGL (low-voltage).And when XAO is LOW, P-MOS2, N-MOS1, P-MOS4, N-MOS3 conducting, output OUT is VGH (high voltage), Figure 7 shows that the XAO signal,
XAOSignal and output signal OUT waveform schematic diagram.
Under driven, when the XAO signal is High, output OUT signal while being VGL, the second thin film transistor (TFT) TFT40 shown in Figure 4, because gate electrode side all is connected to minimum voltage (VGL), therefore all the second thin film transistor (TFT) TFT40 all close, display panels maintains regular event; And when power supply shuts down, because XAO transfers Low to, so output OUT signal becomes VGH, now the gate electrode side due to the second thin film transistor (TFT) TFT40 is ceiling voltage (VGH), therefore all the second thin film transistor (TFT) TFT40 all open, VGH voltage can input on the grid cabling of viewing area (Active Area), and viewing area (Active Area) upper all the first film transistor T FT30 are opened, now pixel voltage rapid discharge, solve the shutdown image retention problem.
The present invention is by increasing a plurality of thin film transistor (TFT)s and an external circuit board at non-display area, circuit is set on circuit board, on thin film transistor (TFT) in the input of the signal on circuit, open closing or opening of the thin film transistor (TFT) of controlling non-display area, thereby make the pixel voltage rapid discharge of viewing area, solve the shutdown image retention problem.
Claims (7)
1. display panels, comprise the array base palte that is oppositely arranged and the liquid crystal during color membrane substrates and sandwiched, described array base palte is provided with viewing area and non-display area, crisscross some sweep traces are set array base palte and data line, sweep trace intersect and limit a plurality of pixel cells with data line, in each pixel cell, be equipped with pixel electrode and the first film transistor T FT, this first film transistor T FT is positioned at viewing area; The side of display panels also is provided with the gate drivers be connected with sweep trace, the source electrode driver be connected with data line; It is characterized in that: on the non-display area away from the gate drivers side, also be provided with a plurality of the second thin film transistor (TFT) TFT, and each second thin film transistor (TFT) TFT is corresponding with each sweep trace of viewing area; The second thin film transistor (TFT) TFT is provided with second grid, the second source electrode and the second drain electrode, the second source electrode of the second thin film transistor (TFT) TFT is connected to the corresponding sweep trace of viewing area, the second grid of the second thin film transistor (TFT) TFT is connected to each other and is in the same place with corresponding the second drain electrode, and the second gate of the second all thin film transistor (TFT) TFT is extremely connected.
2. display panels according to claim 1, it is characterized in that: display panels is an external circuit board also, and the second gate of all the second thin film transistor (TFT) TFT extremely is connected on this circuit board via cabling.
3. display panels according to claim 2, is characterized in that: input control signal XAO is arranged on described gate drivers.
4. display panels according to claim 3, it is characterized in that: described circuit board is provided with voltage conversion circuit, and it is extreme that the output signal end of this voltage conversion circuit is connected to the second gate of the second thin film transistor (TFT) TFT.
5. display panels according to claim 4, it is characterized in that: when input control signal was high levle, the output signal of voltage conversion circuit was low level, and the second thin film transistor (TFT) TFT all closes, and display panels maintains regular event; When power supply shuts down, input control signal is low level, and the output signal of voltage conversion circuit is high levle, and the second thin film transistor (TFT) TFT all opens, and high levle voltage inputs on the sweep trace of viewing area, and the first film transistor T FT is opened.
6. according to the described display panels of claim 4-5, it is characterized in that: described voltage conversion circuit comprises supply voltage VDD, high voltage VGH, the first low-voltage VGL1, the second low-voltage VGL2, input signal XAO, input signal
XAO, output signal OUT, four P-MOS pipe, four N-MOS pipes, be respectively: P-MOS1, P-MOS2, P-MOS3, P-MOS4, N-MOS1, N-MOS2, N-MOS3, N-MOS4, wherein, input signal XAO and input signal
XAOFor two opposite signals, P-MOS1 with
X AOSignal connects, and P-MOS2 is connected with the XAO signal; After P-MOS1 and P-MOS2 parallel connection, be connected with supply voltage VDD, P-MOS3 with and the P-MOS4 parallel connection after with high voltage VGH, be connected, after N-MOS1 and N-MOS2 parallel connection, be connected with the first low-voltage VGL1, N-MOS3 is connected with the second low-voltage VGL2 after the N-MOS4 parallel connection, P-MOS1 also is connected in series with N-MOS1, N-MOS2 and N-MOS4 respectively, P-MOS2 also is connected in series with N-MOS1, N-MOS2 and N-MOS3 respectively, and P-MOS3 and N-MOS4 are connected in series, and P-MOS4 and N-MOS3 are connected in series; And P-MOS3, P-MOS4, N-MOS4 all are connected to output signal OUT.
7. display panels according to claim 6 is characterized in that: when XAO is high levle High, and P-MOS1, N-MOS2, P-MOS3, N-MOS4 conducting, output signal OUT is low-voltage VGL; When XAO is low level LOW, P-MOS2, N-MOS1, P-MOS4, N-MOS3 conducting, output signal OUT is high voltage VGH.
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| CN103869516A (en) * | 2014-03-12 | 2014-06-18 | 京东方科技集团股份有限公司 | Display panel discharge circuit and display device |
| CN105096888A (en) * | 2015-08-28 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate, and display panel and driving method thereof |
| WO2018126785A1 (en) * | 2017-01-03 | 2018-07-12 | 京东方科技集团股份有限公司 | Charge release circuit, display substrate, display device, and charge release method thereof |
| CN108281118A (en) * | 2018-01-09 | 2018-07-13 | 昆山龙腾光电有限公司 | Display panel and liquid crystal display device |
| CN110068970A (en) * | 2019-04-18 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Tft array substrate and display panel |
| CN113257134A (en) * | 2021-05-28 | 2021-08-13 | 武汉华星光电技术有限公司 | Display panel and display device |
| WO2022141183A1 (en) * | 2020-12-28 | 2022-07-07 | Tcl华星光电技术有限公司 | Drive circuit of display panel, and display apparatus |
| CN115240583A (en) * | 2022-09-23 | 2022-10-25 | 广州华星光电半导体显示技术有限公司 | Residual charge releasing circuit and display panel |
| US11774818B2 (en) | 2020-11-10 | 2023-10-03 | Hefei Boe Optoelectronics Technology Co., Ltd. | Display panel and electronic apparatus |
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| CN103869516A (en) * | 2014-03-12 | 2014-06-18 | 京东方科技集团股份有限公司 | Display panel discharge circuit and display device |
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| CN110068970A (en) * | 2019-04-18 | 2019-07-30 | 深圳市华星光电半导体显示技术有限公司 | Tft array substrate and display panel |
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| US11774818B2 (en) | 2020-11-10 | 2023-10-03 | Hefei Boe Optoelectronics Technology Co., Ltd. | Display panel and electronic apparatus |
| WO2022141183A1 (en) * | 2020-12-28 | 2022-07-07 | Tcl华星光电技术有限公司 | Drive circuit of display panel, and display apparatus |
| US11699410B2 (en) | 2020-12-28 | 2023-07-11 | Tcl China Star Optoelectronics Technology Co., Ltd. | Driving circuit of display panel and display device |
| CN113257134A (en) * | 2021-05-28 | 2021-08-13 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN115240583A (en) * | 2022-09-23 | 2022-10-25 | 广州华星光电半导体显示技术有限公司 | Residual charge releasing circuit and display panel |
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| Publication number | Publication date |
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| CN103412427B (en) | 2016-03-16 |
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