CN101191922B - LCD display panel - Google Patents
LCD display panel Download PDFInfo
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- CN101191922B CN101191922B CN2006101573152A CN200610157315A CN101191922B CN 101191922 B CN101191922 B CN 101191922B CN 2006101573152 A CN2006101573152 A CN 2006101573152A CN 200610157315 A CN200610157315 A CN 200610157315A CN 101191922 B CN101191922 B CN 101191922B
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Abstract
The present invention relates to a liquid crystal display panel and the driving method thereof. The liquid crystal display panel comprises a plurality of scan lines, a plurality of control lines, a plurality of first pixel units, a plurality of second pixel units and a plurality of data driving chips. The data driving chips comprise a plurality of output ends. Under the control of the scan lines and the control lines, during the period of applying signals to one row of scan lines, the output ends firstly output a first gray-scale voltage to the first pixel units and the second pixel units, and then output a second gray-scale voltage to the second pixel units. The present invention also provides a driving method for the liquid crystal display panel.
Description
Technical field
The present invention relates to a kind of display panels and driving method thereof.
Background technology
Display panels has been widely used in electronic equipments such as TV, notebook computer, mobile phone, personal digital assistant because of having characteristics such as low radiation, thin thickness and power consumption be low.
Seeing also Fig. 1, is a kind of schematic equivalent circuit of prior art display panels.This display panels 10 comprise a plurality of data driving chip 110, a plurality of scanning drive chip 112, many sweep traces that are parallel to each other 142, many data lines 141 that are parallel to each other and intersect vertically with these sweep trace 142 insulation, a plurality of thin film transistor (TFT) that is positioned at this sweep trace 142 and this data line 141 intersections (thin film transistor, TFT) 101, a plurality of pixel electrode 102, a plurality of public electrode 103 and a plurality of memory capacitance 104.This pixel electrode 102, this public electrode 103 and therebetween liquid crystal molecule (not indicating) constitute a plurality of liquid crystal capacitances (not indicating).This memory capacitance 104 is in parallel with this liquid crystal capacitance.This scanning drive chip 112 is used for driving this sweep trace 142.This data driving chip 110 is used for driving this data line 141, and it comprises a plurality of output terminals 111, and each output terminal 111 connects a data line 141.
The grid of this thin film transistor (TFT) 101 (not indicating) is connected to this sweep trace 142, and source electrode (not indicating) is connected to this data line 141, and drain electrode (not indicating) is connected to this pixel electrode 102.The Minimum Area that this sweep trace 142 and this data line 141 are enclosed is defined as a pixel cell 106.
The driving method of this display panels 10 is as follows:
As these scanning drive chip 112 outputs one high voltage scanning voltage signal V
gDuring to this sweep trace 142, the thin film transistor (TFT) 101 that this sweep trace 142 is connected is opened, simultaneously, the output terminal of this data driving chip 110 is exported a gray scale voltage signal to this data line 141, this gray scale voltage signal is sent to this pixel electrode 102 via this thin film transistor (TFT) 101, and this pixel cell 106 is shown.
As these scanning drive chip 112 outputs one low-voltage scanning voltage signal V
0During to this sweep trace 142, the thin film transistor (TFT) 101 that this sweep trace 142 is connected cuts out, and this moment, this memory capacitance 104 and this liquid crystal capacitance kept the voltage of this pixel electrode 102, to keep the demonstration of this pixel cell 106.
From the above, each output terminal 111 of this data driving chip 110 correspondence during one scan line 142 is applied in signal is exported a gray scale voltage to this pixel electrode 102, thereby realize the demonstration of this pixel cell 106, so an output terminal 111 of this data driving chip 110 only drives a pixel cell 106.Usually pixel cell 106 numbers of this display panels 10 are very big, and output terminal 111 numbers of this data driving chip 110 are certain, thereby this display panels 10 needs more data driving chip 110 to realize showing, thereby the data driving chip cost of this display panels 10 is higher.
Summary of the invention
For solving the cost problem of higher of display panels data driving chip in the prior art, be necessary to provide a kind of data driving chip lower-cost display panels.
A kind of display panels, it comprises multi-strip scanning line, many control lines, a plurality of first pixel cell, a plurality of second pixel cell and a plurality of data driving chip.This data driving chip comprises a plurality of output terminals.Under the control of this sweep trace and this control line, this output terminal is exported first gray scale voltage earlier to this first pixel cell and this second pixel cell during a horizontal scanning line is applied in signal, export second gray scale voltage again to this second pixel cell, this display panels also comprises many first data lines and many second data lines, each output terminal is controlled one first data line and one second data line, each output terminal provides gray scale voltage via this first data line for this first pixel cell, provide gray scale voltage via this second data line for this second pixel cell, this first pixel cell comprises a first film transistor, one second thin film transistor (TFT) and one first pixel electrode, the transistorized grid of this first film is connected to this sweep trace, source electrode is connected to this first data line, drain electrode is connected to the source electrode of this second thin film transistor (TFT), the grid of this second thin film transistor (TFT) is connected to this control line, drain electrode is connected to this first pixel electrode, during a horizontal scanning line is applied in signal, this the first film transistor is opened, this control line is used for controlling the opening and closing of this second thin film transistor (TFT), whether the signal on this first data line is sent to this first pixel electrode with control; This second pixel cell comprises one the 3rd thin film transistor (TFT) and one second pixel electrode, the grid of the 3rd thin film transistor (TFT) is connected to this sweep trace, source electrode is connected to this second data line, drain electrode connects this second pixel electrode, during a horizontal scanning line is applied in signal, the 3rd thin film transistor (TFT) is opened, and the signal of this second data line is sent to this second pixel electrode.
A kind of display panels, it comprises the multi-strip scanning line, a plurality of first pixel cells, a plurality of second pixel cells and at least one data driving chip, this data driving chip comprises a plurality of output terminals, it is characterized in that: this display panels also comprises many control lines, under the control of this sweep trace and this control line, each output terminal is exported first gray scale voltage earlier to this first pixel cell and this second pixel cell during a horizontal scanning line is applied in signal, export second gray scale voltage again to this second pixel cell, this display panels also comprises a plurality of data lines, this first pixel cell and shared this data line of this second pixel cell, each output terminal is controlled a data line, provide gray scale voltage by this data line for this first pixel cell and second pixel cell, this first pixel cell comprises a first film transistor, one second thin film transistor (TFT) and one first pixel electrode, the transistorized grid of this first film is connected to this sweep trace, source electrode is connected to this data line, drain electrode is connected to the source electrode of this second thin film transistor (TFT), the grid of this second thin film transistor (TFT) is connected to this control line, drain electrode is connected to this first pixel electrode, during a horizontal scanning line is applied in signal, this the first film transistor is opened, this control line is used for controlling the opening and closing of this second thin film transistor (TFT), whether the signal on this data line is sent to this first pixel electrode with control; This second pixel cell comprises one the 3rd thin film transistor (TFT) and one second pixel electrode, the grid of the 3rd thin film transistor (TFT) is connected to this sweep trace, source electrode is connected to this data line, drain electrode connects this second pixel electrode, during a horizontal scanning line is applied in signal, the 3rd thin film transistor (TFT) is opened, and the signal on this data line is sent to this second pixel electrode.
With respect to prior art, in this display panels, the output terminal of this data driving chip is exported first gray scale voltage earlier to this first pixel cell and this second pixel cell during a horizontal scanning line is applied in signal, export second gray scale voltage again to this second pixel cell, therefore, one output terminal drives two pixel cells, the decreased number that makes output terminal is half of prior art, thereby the decreased number that makes this data driving chip is prior art half, and then reduces the cost of the data driving chip of this display panels.
Description of drawings
Fig. 1 is a kind of synoptic diagram of equivalent electrical circuit of prior art display panels.
Fig. 2 is the structural representation of display panels first embodiment of the present invention.
Fig. 3 is the schematic equivalent circuit of display panels shown in Figure 2.
Fig. 4 is the drive signal waveform figure of display panels shown in Figure 3.
Fig. 5 is a line translation type of drive synoptic diagram.
Fig. 6 is a point transformation type of drive synoptic diagram.
Fig. 7 is the schematic equivalent circuit of display panels second embodiment of the present invention.
Fig. 8 is the synoptic diagram of duplicate rows conversion type of drive.
Embodiment
Seeing also Fig. 2, is the structural representation of display panels first embodiment of the present invention.This display panels 20 comprises one first substrate 50, one and the liquid crystal layer 70 of second substrate 60 and between this first substrate 50 and this second substrate 60 that be oppositely arranged of this first substrate 50.
Seeing also Fig. 3, is the schematic equivalent circuit of this display panels 20.This display panels 20 comprises a plurality of data driving chip 210, a plurality of scanning drive chips 212, one signal generator 214, many first data lines 241 that are parallel to each other, many are parallel to each other and second also parallel with this first data line 241 data line 242, many with this first data line 241 and these second data line, 242 vertically insulated crossing sweep traces 243, many with this first data line 241 and these second data line, 242 vertically insulated crossing control lines 244, a plurality of the first film transistors 201, a plurality of second thin film transistor (TFT)s 202, a plurality of the 3rd thin film transistor (TFT)s 221, a plurality of first pixel electrodes 203, a plurality of second pixel electrodes 222, a plurality of public electrodes 204, a plurality of first memory capacitance 205 and a plurality of second memory capacitance 224.This scanning drive chip 212 is used for exporting a plurality of sweep signals to this sweep trace 243.This signal generator 214 is used for exporting one and controls signal to this control line 244.
This data driving chip 210 comprises a plurality of output terminals 211, and each output terminal 211 connects one first data line 241 and one second data line 242.First data line 241 that this 2n (n is a natural number) output terminal 211 connects is adjacent with first data line 241 that this 2n-1 output terminal is connected, and its second data line 242 that also is connected with this 2n-1 output terminal 211 is adjacent, and second data line 242 that this 2n-1 output terminal 211 connects is adjacent with second data line 242 that this 2n output terminal 211 is connected.
The grid of this first film transistor 201 (not indicating) is connected to this sweep trace 243, and source electrode (not indicating) is connected to this first data line 241, and drain electrode (not indicating) is connected to the source electrode (not indicating) of this second thin film transistor (TFT) 202.The grid of this second thin film transistor (TFT) 202 (not indicating) is connected to this control line 244, and drain electrode (not indicating) is connected to this first pixel electrode 203.This first pixel electrode 203, this public electrode 204 and therebetween liquid crystal molecule (not indicating) constitute a plurality of first liquid crystal capacitances (not indicating).This first storage capacitors 205 is in parallel with this first liquid crystal capacitance.One the first film transistor 201, one second thin film transistor (TFT) 202, one first liquid crystal capacitance and one first memory capacitance 205 are defined as one first pixel cell 206.206 one-tenth row of this first pixel cell are arranged.
The grid of the 3rd thin film transistor (TFT) 221 (not indicating) is connected to this sweep trace 243, and source electrode (not indicating) is connected to this second data line 242, and drain electrode (not indicating) is connected to this second pixel electrode 222.This second pixel electrode 222, this public electrode 204 and therebetween liquid crystal molecule (not indicating) constitute a plurality of second liquid crystal capacitances (not indicating).This second storage capacitors 224 is in parallel with this second liquid crystal capacitance.One the 3rd thin film transistor (TFT) 221, one second liquid crystal capacitance and one second memory capacitance 224 are defined as one second pixel cell 225.225 one-tenth row of this second pixel cell are arranged.
See also Fig. 4, Fig. 4 is the drive signal waveform figure of this display panels 20.Wherein, V
ConControl signal oscillogram for signal generator output; G
1-G
nBe a plurality of sweep signal oscillograms; V
dGray scale voltage oscillogram for these data driving chip 210 outputs.
The driving method of this display panels 20 is as follows:
t
0-t
1During this time, promptly first horizontal scanning line 243 is applied in the time of the first two branch of sweep signal, and this signal generator 214 outputs one high voltage opens second thin film transistor (TFT) 202 that is connected to this control line 244 to this control line 244; Simultaneously, because this scanning drive chip 212 outputs one high voltage sweep signal to the first horizontal scanning line 243 is opened the first film transistor 201 and the 3rd thin film transistor (TFT) 221 on first horizontal scanning line 243; At this moment, the first gray scale voltage V of a plurality of first pixel cell, 206 correspondences of these data driving chip 210 outputs
D1To this first data line 241 and this second data line 242, then, this first gray scale voltage V
D1Source electrode and drain electrode via the source electrode of this first film transistor 201 and drain electrode, this second thin film transistor (TFT) 202 write this first pixel electrode 203, also source electrode and the drain electrode via the 3rd thin film transistor (TFT) 221 writes this second pixel electrode 222, realizing the being positioned at normal demonstration of first pixel cell 206 on this first horizontal scanning line 243, show the picture data corresponding 225 this moments with this first pixel cell 206 and be positioned at second pixel cell on this first sweep trace 243.First memory capacitance 205 and this second memory capacitance 224 on this column scan line 243 is in charged state simultaneously, thereby this first memory capacitance 205 and this second memory capacitance 224 keep this first gray scale voltage V
D1
t
1-t
2During this time, promptly first horizontal scanning line 243 is applied in back 1/2nd times of sweep signal, this signal generator 214 outputs one low-voltage controls signal to this control line 244, second thin film transistor (TFT) 202 that is connected to this control line 244 cuts out, the first gray scale voltage V that this moment, this first pixel cell 206 kept by this first memory capacitance 205
D1Keep demonstration; And the sweep signal on this first horizontal scanning line 243 still is a high voltage, and therefore, the first film transistor 201 on this first horizontal scanning line 243 and the 3rd thin film transistor (TFT) 221 are opened; At this moment, the second gray scale voltage V of a plurality of second pixel cell, 225 correspondences of these data driving chip 210 outputs
D2To this first data line 241 and this second data line 242, because this second thin film transistor (TFT) 202 cuts out this second gray scale voltage V
D2Can not write this first pixel electrode 203, but its source electrode and drain electrode via the 3rd thin film transistor (TFT) 221 writes this second pixel electrode 222, realization is positioned at the normal demonstration of second pixel cell 225 on this column scan line 243, and adjusts this second memory capacitance 224 this second gray scale voltage of maintenance V
D2
t
2During scanning first horizontal scanning line 243 once more to this data driving chip 210 later on, this scanning drive chip 212 is successively to secondary series, the 3rd row, the 4th row ... sweep trace 243 scans, progressively to realize being positioned at this secondary series, the 3rd row, the 4th row ... the normal demonstration of first, second pixel cell 206,225 on the sweep trace 243, and the first gray scale voltage V that first pixel cell 206 on first horizontal scanning line 243 still keeps by this first memory capacitance 205
D1Keep demonstration, the second gray scale voltage V that second pixel cell 225 of this first horizontal scanning line 243 keeps by this second memory capacitance 224
D2Keep demonstration.
In this display panels 20, each output terminal 211 of this data driving chip 210 during a horizontal scanning line 243 is applied in sweep signal in the first first gray scale voltage V of these first pixel cell, 206 correspondences of output
D1To this first pixel electrode 203 and this second pixel electrode 222, to realize the normal demonstration of this first pixel cell 206; And then export the second gray scale voltage V of these second pixel cell, 225 correspondences
D2To this second pixel electrode 222, to adjust the demonstration of this second pixel cell 225.If this first gray scale voltage V
D1With this second gray scale voltage V
D2The polarity of voltage difference, it is excessive to cause the voltage of this second pixel electrode 222 to change in the single pass signal time, thereby makes the demonstration of this second pixel cell 225 not accurate enough.Therefore, for reaching display quality preferably, this display panels 20 can adopt line translation type of drive or point transformation type of drive, to guarantee this first gray scale voltage V
D1With this second gray scale voltage V
D2Polarity of voltage identical.See also Fig. 5 and Fig. 6, Fig. 5 is a line translation type of drive synoptic diagram, and Fig. 6 is a point transformation type of drive synoptic diagram.
Because in this display panels 20, each output terminal 211 of this data driving chip 210 is exported this first gray scale voltage V earlier during a horizontal scanning line 243 is applied in signal
D1To this first pixel cell 206 and this second pixel cell 225, export this second gray scale voltage V again
D2To this second pixel cell 225, therefore an output terminal 211 drives one first pixel cell 206 and one second pixel cell 225, the decreased number of this output terminal 211 is half of prior art, thereby make that the decreased number of this data driving chip 210 is half of prior art, and then reduced the cost of the data driving chip 210 of this display panels 20.
Seeing also Fig. 7, is the schematic equivalent circuit of display panels second embodiment of the present invention.This display panels 30 comprises a plurality of data driving chip 310, a plurality of scanning drive chips 312, one signal generator 314, many the data lines 341 that are parallel to each other, many with these data line 341 vertically insulated crossing sweep traces 343, many with these data line 341 vertically insulated crossing control lines 344, a plurality of the first film transistors 301, a plurality of second thin film transistor (TFT)s 302, a plurality of the 3rd thin film transistor (TFT)s 321, a plurality of first pixel electrodes 303, a plurality of second pixel electrodes 322, a plurality of public electrodes 304, a plurality of first memory capacitance 305 and a plurality of second memory capacitance 324.This scanning drive chip 312 is used for exporting a plurality of sweep signals to this sweep trace 343.This signal generator 314 is used for exporting one and controls signal to this control line 344.One of this data driving chip 310 output terminal 311 connects a data line 341.
The grid of this first film transistor 301 (not indicating) is connected to this sweep trace 343, and source electrode (not indicating) is connected to this data line 341, and drain electrode (not indicating) is connected to the source electrode (not indicating) of this second thin film transistor (TFT) 302.The grid of this transistor seconds 302 (not indicating) is connected to this control line 344, and drain electrode (not indicating) is connected to this first pixel electrode 303.This first pixel electrode 303, this public electrode 304 and therebetween liquid crystal molecule (not indicating) constitute a plurality of first liquid crystal capacitances (not indicating).This first storage capacitors 305 is in parallel with this first liquid crystal capacitance.One the first film transistor 301, one second thin film transistor (TFT) 302, one first liquid crystal capacitance and one first memory capacitance 305 are defined as one first pixel cell 306.306 one-tenth row of this first pixel cell are arranged.
The grid of the 3rd thin film transistor (TFT) 321 (not indicating) connects this sweep trace 343, and source electrode (not indicating) is connected to this data line 341, and drain electrode (not indicating) is connected to this second pixel electrode 322.This second pixel electrode 322, this public electrode 304 and therebetween liquid crystal molecule (not indicating) constitute a plurality of second liquid crystal capacitances (not indicating).This second storage capacitors 324 is in parallel with this second liquid crystal capacitance.One the 3rd thin film transistor (TFT) 321, one second liquid crystal capacitance and one second memory capacitance 324 are defined as one second pixel cell 325.325 one-tenth row of this second pixel cell are arranged.
This first pixel cell 306 and this second pixel cell 325 lay respectively at the both sides of this data line 341, its shared data line 341.
The driving method of this display panels 30 is as follows:
In one time of the first two branch during a horizontal scanning line 343 is applied in the high voltage sweep signal, the first, the 3rd thin film transistor (TFT) 301,321 on this row is opened, the unlatching of second thin film transistor (TFT) 302 on these control line 344 these row of control simultaneously, this moment, this output terminal 311 was exported a plurality of first gray scale voltage V of first pixel cell, 306 correspondences on these row
D1, the first gray scale voltage V
D1Write this first pixel electrode 303 and this second pixel electrode 322 via this data line 341, to realize the normal demonstration of this first pixel cell 306, and this second pixel cell 325 also shows the picture identical with this first pixel cell 306, also at this moment, this first memory capacitance 305 and this second memory capacitance 324 store this first gray scale voltage V
D1
In back 1/2nd times during a horizontal scanning line 343 is applied in the high voltage sweep signal, the first, the 3rd thin film transistor (TFT) 301,321 on this row is still opened, closing of second thin film transistor (TFT) 302 on this control line 344 these row of control simultaneously, this moment these output terminal 311 these second pixel cell, 325 correspondences of output a plurality of second gray scale voltage V
D2, this second gray scale voltage V
D2Only can write this second pixel electrode 322 via this data line 341, serve as normal the demonstration to adjust this second pixel cell 325, and adjust this second memory capacitance 324 this second gray scale voltage of storage V
D2, and these first pixel cell, 306 nationalitys are kept demonstration by the voltage that this first memory capacitance 305 keeps.
During a horizontal scanning line 343 was not applied to the high voltage sweep signal, this first pixel cell 306 was kept demonstration by this first memory capacitance 305, and this second pixel cell 325 is kept demonstration by this second memory capacitance 324.
One output terminal 311 of this data driving chip 310 during a horizontal scanning line 343 is applied in the high voltage sweep signal in the first first gray scale voltage V of these first pixel cell, 306 correspondences of output
D1Write this first pixel electrode 303 and this second pixel electrode 322 by this data line 341, to realize the normal demonstration of this first pixel cell 306; And then export the second gray scale voltage V of these second pixel cell, 325 correspondences
D2Also write this second pixel electrode 322, to adjust the demonstration of this second pixel cell 325, if this first gray scale voltage V by this data line 341
D1With this second gray scale voltage V
D2The polarity of voltage difference, can cause the voltage of this second pixel electrode 322 in the single pass signal time, to change excessive, thereby the demonstration of this second pixel cell 325 is not accurate enough, therefore, for reaching display quality preferably, this display panels 30 can adopt duplicate rows conversion type of drive, to guarantee this first gray scale voltage V
D1With this second gray scale voltage V
D2Polarity of voltage identical.Seeing also Fig. 8, is the synoptic diagram of duplicate rows conversion type of drive.
Because in this display panels 30, each output terminal 311 of this data driving chip 310 is exported the first gray scale voltage V earlier during a horizontal scanning line 343 is applied in signal
D1To this first pixel cell 306 and this second pixel cell 325, export the second gray scale voltage V again
D2To this second pixel cell 325, therefore an output terminal 311 drives one first pixel cell 306 and one second pixel cell 325, the decreased number of this output terminal 311 is half of prior art, thereby make that the decreased number of this data driving chip 310 is half of prior art, and then reduced the cost of the data driving chip 310 of this display panels 30.
Again, because first pixel cell 306 and second pixel cell, 325 shared data lines 341 of these data line 341 both sides, these display panels 30 desired data lines 341 also reduce half, and then have simplified the wiring of this display panels 30.
It is described that display panels of the present invention is not limited to above-mentioned embodiment, as: in first embodiment, this control line 244 can be connected directly to this scanning drive chip 212, when driving this sweep trace 243, also export a series of scanning voltage signals by this scanning drive chip 212 to this control line 244.
Claims (5)
1. display panels, it comprises the multi-strip scanning line, a plurality of first pixel cells, a plurality of second pixel cells and at least one data driving chip, this data driving chip comprises a plurality of output terminals, it is characterized in that: this display panels also comprises many control lines, under the control of this sweep trace and this control line, each output terminal is exported first gray scale voltage earlier to this first pixel cell and this second pixel cell during a horizontal scanning line is applied in signal, export second gray scale voltage again to this second pixel cell, this display panels also comprises many first data lines and many second data lines, each output terminal is controlled one first data line and one second data line, each output terminal provides gray scale voltage via this first data line for this first pixel cell, provide gray scale voltage via this second data line for this second pixel cell, this first pixel cell comprises a first film transistor, one second thin film transistor (TFT) and one first pixel electrode, the transistorized grid of this first film is connected to this sweep trace, source electrode is connected to this first data line, drain electrode is connected to the source electrode of this second thin film transistor (TFT), the grid of this second thin film transistor (TFT) is connected to this control line, drain electrode is connected to this first pixel electrode, during a horizontal scanning line is applied in signal, this the first film transistor is opened, this control line is used for controlling the opening and closing of this second thin film transistor (TFT), whether the signal on this first data line is sent to this first pixel electrode with control; This second pixel cell comprises one the 3rd thin film transistor (TFT) and one second pixel electrode, the grid of the 3rd thin film transistor (TFT) is connected to this sweep trace, source electrode is connected to this second data line, drain electrode connects this second pixel electrode, during a horizontal scanning line is applied in signal, the 3rd thin film transistor (TFT) is opened, and the signal of this second data line is sent to this second pixel electrode.
2. display panels as claimed in claim 1, it is characterized in that: first data line that the 2n output terminal of this data driving chip connects is adjacent with first data line that this 2n-1 output terminal is connected, and it is also adjacent with second data line that this 2n-1 output terminal is connected, second data line that this 2n-1 output terminal connects is adjacent with second data line that this 2n output terminal is connected, and n is a natural number.
3. display panels as claimed in claim 2 is characterized in that: this display panels adopts line translation type of drive or point transformation type of drive.
4. display panels, it comprises the multi-strip scanning line, a plurality of first pixel cells, a plurality of second pixel cells and at least one data driving chip, this data driving chip comprises a plurality of output terminals, it is characterized in that: this display panels also comprises many control lines, under the control of this sweep trace and this control line, each output terminal is exported first gray scale voltage earlier to this first pixel cell and this second pixel cell during a horizontal scanning line is applied in signal, export second gray scale voltage again to this second pixel cell, this display panels also comprises a plurality of data lines, this first pixel cell and shared this data line of this second pixel cell, each output terminal is controlled a data line, provide gray scale voltage by this data line for this first pixel cell and second pixel cell, this first pixel cell comprises a first film transistor, one second thin film transistor (TFT) and one first pixel electrode, the transistorized grid of this first film is connected to this sweep trace, source electrode is connected to this data line, drain electrode is connected to the source electrode of this second thin film transistor (TFT), the grid of this second thin film transistor (TFT) is connected to this control line, drain electrode is connected to this first pixel electrode, during a horizontal scanning line is applied in signal, this the first film transistor is opened, this control line is used for controlling the opening and closing of this second thin film transistor (TFT), whether the signal on this data line is sent to this first pixel electrode with control; This second pixel cell comprises one the 3rd thin film transistor (TFT) and one second pixel electrode, the grid of the 3rd thin film transistor (TFT) is connected to this sweep trace, source electrode is connected to this data line, drain electrode connects this second pixel electrode, during a horizontal scanning line is applied in signal, the 3rd thin film transistor (TFT) is opened, and the signal on this data line is sent to this second pixel electrode.
5. display panels as claimed in claim 4 is characterized in that: this display panels adopts duplicate rows conversion type of drive.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101573152A CN101191922B (en) | 2006-12-01 | 2006-12-01 | LCD display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006101573152A CN101191922B (en) | 2006-12-01 | 2006-12-01 | LCD display panel |
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| CN101191922A CN101191922A (en) | 2008-06-04 |
| CN101191922B true CN101191922B (en) | 2010-04-14 |
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| CN2006101573152A Expired - Fee Related CN101191922B (en) | 2006-12-01 | 2006-12-01 | LCD display panel |
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| CN102881256B (en) * | 2012-10-12 | 2015-04-29 | 京东方科技集团股份有限公司 | Pixel drive circuit, display panel, display device and pixel driving method |
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| CN111261123A (en) * | 2020-03-06 | 2020-06-09 | Tcl华星光电技术有限公司 | Display panel and driving method thereof |
| CN115113446B (en) * | 2022-06-13 | 2023-08-08 | 武汉华星光电技术有限公司 | Display module, driving method and display device |
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|---|---|---|---|---|
| US5528163A (en) * | 1995-03-23 | 1996-06-18 | Tohken Industries Co., Ltd. | Method of inspecting cells of liquid crystal display |
| CN1278073A (en) * | 1999-06-04 | 2000-12-27 | 权五敬 | Liquid crystal display |
| CN1619400A (en) * | 2004-05-24 | 2005-05-25 | 友达光电股份有限公司 | Film transistor liquid crystal display and driving method thereof |
| CN1637497A (en) * | 2004-01-08 | 2005-07-13 | 恩益禧电子股份有限公司 | Liquid crystal display and driving method thereof |
-
2006
- 2006-12-01 CN CN2006101573152A patent/CN101191922B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528163A (en) * | 1995-03-23 | 1996-06-18 | Tohken Industries Co., Ltd. | Method of inspecting cells of liquid crystal display |
| CN1278073A (en) * | 1999-06-04 | 2000-12-27 | 权五敬 | Liquid crystal display |
| CN1637497A (en) * | 2004-01-08 | 2005-07-13 | 恩益禧电子股份有限公司 | Liquid crystal display and driving method thereof |
| CN1619400A (en) * | 2004-05-24 | 2005-05-25 | 友达光电股份有限公司 | Film transistor liquid crystal display and driving method thereof |
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| Publication number | Publication date |
|---|---|
| CN101191922A (en) | 2008-06-04 |
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