CN114677986A

CN114677986A - Display device

Info

Publication number: CN114677986A
Application number: CN202210423493.4A
Authority: CN
Inventors: 古涛; 扶伟; 袁海江
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-04-21
Filing date: 2022-04-21
Publication date: 2022-06-28

Abstract

The application provides a display, which comprises N scanning lines, M data lines, N multiplied by M pixel units and at least one switch module. And N scanning lines are started line by line. Each switch module is connected in series with a data line and is electrically connected between the corresponding data line and two connection points of two adjacent pixel units, two scanning lines electrically connected with the two pixel units in a one-to-one correspondence mode are defined as a first scanning line and a second scanning line, the first scanning line is started before the second scanning line, and in a frame image display period, the switch modules are in a first state when the first scanning line and the scanning line started before the first scanning line are started and in a second state when the second scanning line and the scanning line started after the second scanning line are started. According to the display, the partial section of the data line electrically connected with the switch module does not continuously receive the data voltage in the whole frame display period, and the energy consumption of the display can be reduced.

Description

Display device

Technical Field

The application relates to the field of displays, in particular to a display.

Background

At present, an LCD (Liquid Crystal Display) is the most widely used Display in various industries, and has the advantages of thin appearance, light weight, and the like. However, as the demand for endurance of electronic products (especially small-sized LCD products such as mobile phones and notebooks) is higher, reducing power consumption of the display becomes an important research topic in the field of display panels.

There are many methods for reducing power consumption of the existing display, such as Charge Sharing (Charge Sharing), Seamless Dynamic Refresh Rate Support (SDRRS), self-Refresh (PSR), and so on. However, the methods all need to implement the secondary frequency and the screen self-refresh by a Timing Controller (TCON) or a functional module of a driver to reduce power consumption, and can be implemented only in a specific mode, for example, to implement the secondary frequency function, the display panel needs to be matched with a System On Chip (SOC) to use the normal frame frequency in the dynamic picture display mode and use the secondary frequency in the static picture display mode. Therefore, the existing method for reducing power consumption of the display has certain limitations.

Disclosure of Invention

In view of the above, a main objective of the present application is to provide a display, which aims to solve the problem that the conventional display has certain limitations in reducing power consumption.

To achieve the above object, the present application provides a display device including a display panel, wherein the display panel includes N scan lines, M data lines, and at least one switch module. Wherein each of the scan lines extends in a row direction. Each of the data lines extends in a column direction. The N scanning lines and the M data lines are arranged in a staggered mode to define N multiplied by M pixel units, and the N scanning lines are opened line by line along a preset direction to scan the N lines of the pixel units line by line. The preset direction is perpendicular to the row direction, and M, N are positive integers. For each switch module, the switch module is connected in series to one data line and is electrically connected between the corresponding data line and two connection points of two adjacent pixel units, two scan lines electrically connected to the two pixel units in one-to-one correspondence are defined as a first scan line and a second scan line, the first scan line is turned on before the second scan line, the switch module is in a first state when the first scan line and the scan line turned on before the first scan line are turned on and is in a second state when the second scan line and the scan line turned on after the second scan line are turned on in a frame display period. Wherein the first state and the second state are both one of an on state and an off state, and the first state is different from the second state.

Optionally, the display further includes a driving circuit, the driving circuit is configured to drive the display panel to display, the driving circuit includes a data driver located at a periphery of a first side of the display panel, and the data driver is electrically connected to the M data lines, respectively. Wherein the first side is perpendicular to the column direction. The preset direction is a direction from being close to the data driver to being far from the data driver. For each switch module, in a frame display period, the switch module is in a disconnected state when a corresponding first scanning line and a scanning line which is started before the first scanning line are started, and is in a connected state when a corresponding second scanning line and a scanning line which is started after the second scanning line are started.

Optionally, the display further includes a driving circuit, the driving circuit is configured to drive the display panel to display, the driving circuit includes a data driver located at a periphery of a first side of the display panel, and the data driver is electrically connected to the M data lines, respectively. Wherein the first side is perpendicular to the column direction. The preset direction is a direction from being far away from the data driver to being close to the data driver. For each switch module, in a frame display period, the switch module is in a conducting state when a corresponding first scanning line and a scanning line which is started before the first scanning line are started, and is in a disconnecting state when a corresponding second scanning line and a scanning line which is started after the second scanning line are started.

Optionally, the at least one switching module comprises at least one row of switching modules. Each row of switch modules comprises M switch modules, and the M switch modules contained in each row are connected in series on the M data lines in a one-to-one correspondence mode. The first scanning lines corresponding to the switch modules in the same row are the same scanning line, and the first scanning lines corresponding to the switch modules in different rows are different scanning lines.

Optionally, the at least one switch module comprises a plurality of rows of the switch modules. In the plurality of switch modules electrically connected to the same data line, x pixel units are spaced between the first scan lines corresponding to any two adjacent switch modules, wherein x is greater than or equal to 1.

Optionally, the at least one switch module includes a row of switch modules, and the first scan line corresponding to each switch module is an ith row of data lines. Wherein i is the integer value of N/2.

Optionally, the driving circuit further includes a control signal generation module, and the control signal generation module is configured to generate a plurality of control signals. The display panel further comprises a plurality of control lines, each control line extends along the row direction, the plurality of control lines correspond to the plurality of rows of switch modules one to one, and the control ends of the M switch modules contained in each row are respectively electrically connected with the corresponding control lines. Each control signal is used for switching the on state and the off state of the switch module of the corresponding row.

Optionally, each of the switch modules includes a transistor.

Optionally, each of the pixel units comprises a scan transistor. The driving circuit further comprises a gate driver positioned at the periphery of the second side edge of the display panel, the gate driver is electrically connected with the control ends of the scanning transistors in the N rows through the N scanning lines respectively, and the gate driver is used for starting the N scanning lines line by line along the preset direction to enable the scanning transistors in the pixel units in the N rows to be conducted line by line, so that the pixel units in the N rows are scanned line by line; wherein the second side edge is perpendicular to the first side edge. The type of the transistor in the switching module is the same as the type of the scan transistor.

Optionally, the driving circuit further includes a timing controller, and the timing controller is further configured to generate a frame start signal, where the frame start signal is used to start the gate driver to open N scan lines row by row along the preset direction, and is used to trigger the control signal generation module to generate a plurality of control signals.

The application provides a display sets up at least one switch module on display panel's data line, and control each switch module switches between conducting state and off-state, under the prerequisite of guaranteeing that the data of each pixel cell is write in duration not influenced, make with the partial section of the data line that the switch module electricity is connected does not continuously receive data voltage in the whole frame display interval, can reduce the parasitic capacitance of data line, thereby reduce the data line is in the transmission the charge-discharge power that consumes during data voltage, and then can reduce the energy consumption of display.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

Fig. 1 is a schematic structural diagram of a display provided in an embodiment of the present application.

Fig. 2 is a schematic circuit diagram of a pixel unit in the display shown in fig. 1.

Fig. 3 is a timing diagram illustrating the operation of the display shown in fig. 1.

Description of the main element symbols:

display 1000

Display panel 100

Drive circuit 200

Timing controller 210

Gate driver 220

Data driver 230

Control signal generation module 240

Scan transistor 111

First side 101

Second side 102

Pixel cell P, P_i，M、P_i+1，M

Scanning line 12

Data line 13

Switch module S

Control line 15

Switch module S, S_M

Storage capacitor C1

Liquid crystal capacitor C2

The following detailed description will further illustrate the present application in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.

In the description of the present application, it should be noted that the terms "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, the present application provides a display 1000, where the display 1000 includes a display panel 100 and a driving circuit 200, and the driving circuit 200 is used for driving the display panel 100 to display. The display 1000 is applied to an electronic device. For example, the electronic device may be a smartphone, a tablet computer, an electronic reader, a vehicle-mounted computer, a navigator, a digital camera, a smart television, a smart wearable device, and other electronic devices of various types, which are not limited herein.

The display panel 100 includes N scan lines 12 and M data lines 13. Wherein M, N are all positive integers. Each of the scan lines 12 extends in a row direction (the OX direction as shown in fig. 1). Each of the data lines 13 extends in a column direction (OY direction shown in fig. 1). The N scan lines 12 and the M data lines 13 are arranged alternately to define N × M pixel units P.

In the embodiment of the present application, the driving circuit 200 includes a Timing Controller (TCON) 210, a gate driver 220, and a data driver 230. The data driver 230 is disposed at the periphery of the first side 101 of the display panel 100. The gate driver 220 is disposed at the periphery of the second side 102 of the display panel 100. The first side 101 is perpendicular to the column direction, and the second side 102 is perpendicular to the first side 101.

The timing controller 210 is electrically connected to the gate driver 220 and the data driver 230, the gate driver 220 is electrically connected to the N scan lines 12, and the data driver 230 is electrically connected to the M data lines 13.

In operation, the timing controller 210 is configured to provide control signals to the gate driver 220 and the data driver 230, control the gate driver 220 to turn on N scan lines in the preset direction (for example, OY direction or YO direction shown in fig. 1) row by row to scan N rows of the pixel units P row by row, and control the data driver 230 to provide a data voltage Vdata to the pixel units P through M data lines 13.

Referring to fig. 2, fig. 2 is a schematic structural diagram of one of the pixel units P in fig. 1. Each of the pixel units P includes a scan transistor 111, a storage capacitor C1, and a liquid crystal capacitor C2. The scan Transistor 111 is a Thin Film Transistor (TFT). A control terminal (i.e., a gate) of the scan transistor 111 is electrically connected to the scan line 12. The source of the scan transistor 111 is electrically connected to the data line 13. First poles of the storage capacitor C1 and the liquid crystal capacitor C2 are electrically connected to the drain of the scan transistor 111, and second poles of the storage capacitor C1 and the liquid crystal capacitor C2 are used for receiving a common voltage VCOM. When a scan line electrically connected to the pixel unit P is turned on, the scan transistor 111 is turned on, so that the storage capacitor C1 and the liquid crystal capacitor C2 receive the data voltage Vdata through the turned-on scan transistor 111 to be charged, thereby completing the scanning of the pixel unit P. It should be noted that, in the present application, the gate driver 220 outputs corresponding scan signals to the N scan lines 12 in response to the control signal provided by the timing controller 210, so that the N scan lines 12 are turned on row by row. Turning on one scan line 12 means that the scan signal received by the scan line 12 is a turn-on signal, such as a high level signal. The transistor 111 in each of the pixel units P electrically connected to the scanning line 12 is turned on in response to the turn-on signal.

However, in the process of writing the data voltage Vdata into the pixel unit P, a parasitic capacitance is easily generated between the data line 13 for transmitting the data voltage and other circuit structures (e.g., the pixel electrode, the scan line 12, etc.), and thus, the power consumption of the display 1000 is increased in the charging process. It is understood that the longer the length of the data line 13, the greater the power consumption of the display 1000.

In view of this, the display panel 100 of the display 1000 provided by the present application further includes at least one switch module S. For each switch module S, the switch module S is connected in series to one data line 13, and is electrically connected between the corresponding data line 13 and two connection points of two adjacent pixel units P, two scan lines 12 electrically connected to the two pixel units P in a one-to-one correspondence are defined as a first scan line 12 and a second scan line 12, the first scan line 12 is turned on before the second scan line 12, and in a frame display period, the switch module S is in a first state when the first scan line 12 and the scan line 12 turned on before the first scan line 12 are turned on, and is in a second state when the second scan line 12 and the scan line 12 turned on after the second scan line 12 are turned on. Wherein the first state and the second state are both one of an on state and an off state, and the first state is different from the second state.

Referring to fig. 1 and fig. 3, the circuit structure and the operation timing of the display 1000 provided in this embodiment will be described in detail by taking an example that the display panel 100 includes a row of switch modules, and the preset direction is a direction from being far away from the data driver 230 to being close to the data driver 230 (e.g., the YO direction shown in fig. 1).

In this embodiment, for each of the switch modules S, in a frame display period, the switch module S is in a conducting state when the corresponding first scan line 12 and the scan line 12 that is turned on before the first scan line 12 are turned on, and is in a disconnecting state when the corresponding second scan line 12 and the scan line 12 that is turned on after the second scan line 12 are turned on.

As shown in fig. 1, the row of switch modules includes M switch modules S, the M switch modules S are connected in series on the M data lines 13 in a one-to-one correspondence manner, and the first scan lines 12 corresponding to the M switch modules S are all the same scan line 12. It can be understood that, since the first scan lines 12 corresponding to the M switch modules S are the same, the operating states of the switch modules S at the same time are the same, and thus, the switch modules S can be controlled by one control signal, which is beneficial to simplifying the circuit structure and reducing the control difficulty.

Further, the driving circuit 200 further includes a control signal generating module 240, where the control signal generating module 240 is configured to generate a control signal CTR, and the control signal CTR is configured to switch the on state and the off state of the switch module S of the row. The display panel 100 further includes control lines 15, the control lines 15 extend along the row direction, and the control ends of the M switch modules S are electrically connected to the control lines 15, respectively. For example, the control signal generating module 240 may be integrated in the gate driver 220, or may be a separate functional module electrically connected to the timing controller 210.

Further, in the embodiment of the present application, the timing controller 210 is further configured to generate a frame start signal STV, where the frame start signal STV is used to start the gate driver 220 to open the N scan lines 12 row by row along the preset direction, and is used to trigger the control signal generating module 240 to generate the control signal CTR.

For convenience of description, the present embodiment marks the switch module S located at the b-th column as S_bThe pixel unit P in the a-th row and the b-th column is marked as P_a,bWherein a is more than or equal to 1 and less than or equal to N, and b is more than or equal to 1 and less than or equal to M. With switch modules S in the Mth column in FIG. 1_MFor example, the switch module S_MElectrically connected to the Mth data line 13 and the pixel unit P_i，MPixel unit P_i+1，MBetween the connection points of, the switch module S_MCorresponding first scanning line S_M1A second scanning line S_M2The scanning line of the ith row and the scanning line of the (i +1) th row are respectively. Obviously, in this embodiment, the first scan lines corresponding to the M switch modules S are all the ith row of scan lines, and the second scan lines corresponding to the M switch modules S are all the ith row of scan lines. Where i is the rounded value of N/2, e.g., N1080 and i 540. Of course, in other embodiments, i may be other values from 1 to N-1. It should be noted that, in this embodiment, the switch module S_MIs arranged on the first scanning line S_M1And the second scanning line S_M2Therefore, the wiring length can be shortened, and the manufacturing difficulty and the manufacturing cost are reduced. Of course, in other embodiments, the switch module S_MOr between two adjacent scan lines 12, as long as the switch module S_MElectrically connected to the Mth data line 13 and the pixel unit P_i，MPixel unit P_i+1，MThe connection point (c) may be, for example, provided between the (i-1) th scanning line 12 and the i-th scanning line 12.

In the embodiment of the present application, the scan transistor 111 may adopt one of a PMOS transistor and an NMOS transistor, and each of the switch modules S includes a transistor. The type of the transistor in the switch module S is the same as that of the scan transistor 111, and both are transistors that are turned on at a high level, for example, NMOS transistors. It can be understood that the same type of transistor is used for the scan transistor 111 and the switch module S, which is beneficial to simplifying the manufacturing process of the display panel 100, reducing the processing difficulty and reducing the production cost. Of course, in other embodiments, different types of transistors can be used for the scan transistor 111 and the switch module S, and are not limited herein.

Referring to fig. 1 and fig. 3 together, as shown in fig. 3, g (a) is a scan signal output by the gate driver 220 to the a-th row scan line 12. When the scan signal received by the scan line 12 is the on signal (e.g., the high signal in fig. 3), the scan line 12 is turned on. In each frame display period T, N scanning lines 12 are started line by line from the scanning line 12 of the 1 st row to the scanning line 12 of the Nth row, wherein a is more than or equal to 1 and less than or equal to N.

In the first half frame display period, the gate driver 220 turns on the scan lines 12 (i.e., the 1 st to i-th row scan lines 12) in the upper half screen of the display panel 100 row by row. During this period, the control signal CTR is in a high state, so that M of the switch modules S are all in a conducting state. The data driver 230 writes the data voltage Vdata into corresponding pixel units P in an open row (i.e., a row of pixel units P electrically connected to the scan line 12 in an on state) in the upper half screen through the M data lines 13 and the turned-on switch module S.

In the second half frame display period, the gate driver 220 turns on the scan lines 12 in the lower half screen of the display panel 100 (i.e., the (i +1) th row scan line 12 to the nth row scan line 12) row by row. The data driver 230 outputs the data voltage Vdata to the corresponding pixel units P in the open row in the lower half panel through the M data lines 13. During this time, the control signal CTR is in a low state, so that M of the switch modules S are all in an off state. It can be understood that, since the pixel units P in the upper half screen of the display panel 100 do not receive the data voltage Vdata any more in the second half frame display period, controlling all M of the switch modules S to be turned off does not affect the writing of the data voltage Vdata. Obviously, during this period, the upper half segment of each data line 13 no longer receives the data voltage Vdata, which is equivalent to that the length of each data line 13 is reduced by half, so that the capacitance value of the parasitic capacitor of each data line 13 is greatly reduced, and the power consumption of the display 1000 can be greatly reduced.

The application provides display 1000 sets up at least one switch module S on display panel 100 ' S data line 13, and control each switch module S switches between conducting state and off-state, under the prerequisite of guaranteeing that the data of each pixel unit P is write in duration not influenced, make with the part section of data line 13 that switch module S is electrically connected does not continuously receive data voltage in whole frame display period, can reduce data line 13 ' S parasitic capacitance, thereby reduce data line 13 is in the transmission the charge-discharge power that data voltage Vdata consumed when, and then can reduce display 1000 ' S energy consumption.

In another embodiment, the predetermined direction is a direction from close to the data driver 230 to far from the data driver 230 (for example, the OY direction shown in fig. 1). At this time, for each of the switch modules S, in a frame display period, the switch module S is in an off state when the corresponding first scan line and the scan line that is turned on before the first scan line are turned on, and is in an on state when the corresponding second scan line and the scan line that is turned on after the second scan line are turned on. Referring to fig. 1 again, in each frame display period T, N scan lines 12 are turned on line by line from the nth row scan line 12 to the 1 st row scan line 12, and in the first half frame display period, the gate driver 220 turns on the scan lines 12 in the lower half screen of the display panel 100 (i.e., the nth row scan line 12 to the (i +1) th row scan line 12) by line. During this period, the control signal CTR is in a low state, so that M switch modules S are all in an off state, and similarly, the power saving effect of the display 1000 is the same as that of the previous embodiment.

In another embodiment, the display panel 100 includes j switch modules S, and the j switch modules S are located in the same row, that is, the first scan lines corresponding to the j switch modules S are the same scan line 12, wherein j is greater than or equal to 1 and is less than or equal to M-1. Obviously, as the number of the switch modules S is reduced, the power saving effect of the display 1000 is gradually reduced. Of course, the j switch modules S may also be located in different rows, so that the control signals corresponding to the j switch modules S are not completely the same, and the control difficulty will increase.

In yet another embodiment, the display panel 100 includes a plurality of control lines 15, a plurality of rows of switch modules S. Specifically, each of the control lines 15 extends along the row direction, the control lines 15 correspond to the plurality of rows of the switch modules S one to one, and the control ends of the M switch modules S included in each row are electrically connected to the corresponding control lines 15, respectively. Each row of switch modules includes M switch modules S, M switch modules S are connected in series to M data lines 13 in a one-to-one correspondence, and the first scan lines 12 corresponding to the switch modules S located in the same row are the same scan line 12, and the first scan lines 12 corresponding to the switch modules S located in different rows are different scan lines 12. Accordingly, the control signal generating module 240 is configured to generate a plurality of control signals. Each of the control signals is used to switch the on state and the off state of the switch module S of the corresponding row. Furthermore, in the plurality of switch modules S electrically connected to the same data line 13, x pixel units P are spaced between the first scan lines 12 corresponding to any two adjacent switch modules S, where x is greater than or equal to 1. For example, N1080, the display panel 100 includes 4 rows of the switch modules, and x 270, so that the display 1000 has better energy saving effect. It can be understood that, as the number of rows of the switch modules S increases, the manufacturing cost of the display 1000 gradually increases, but the energy saving effect gradually increases.

While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

Claims

1. A display includes a display panel including N scan lines extending in a row direction and M data lines extending in a column direction; the N scanning lines and the M data lines are arranged in a staggered mode to define N multiplied by M pixel units, and the N scanning lines are opened line by line along a preset direction to scan the N lines of the pixel units line by line; the preset direction is vertical to the row direction, and M, N are positive integers; it is characterized in that the preparation method is characterized in that,

the display panel further comprises at least one switch module, for each switch module, the switch module is connected in series with one data line and is electrically connected between the corresponding data line and two connection points of two adjacent pixel units, two scanning lines which are electrically connected with the two pixel units in a one-to-one correspondence manner are defined as a first scanning line and a second scanning line, the first scanning line is started before the second scanning line, and in a frame picture display period, the switch module is in a first state when the first scanning line and the scanning line which is started before the first scanning line are started, and is in a second state when the second scanning line and the scanning line which is started after the second scanning line are started; wherein the first state and the second state are both one of an on state and an off state, and the first state is different from the second state.

2. The display according to claim 1, further comprising a driving circuit for driving the display panel to display, wherein the driving circuit comprises a data driver located at the periphery of the first side of the display panel, and the data driver is electrically connected to the M data lines, respectively; wherein the first side is perpendicular to the column direction;

the preset direction is a direction from being close to the data driver to being far away from the data driver; for each switch module, in a frame image display period, the switch module is in a disconnected state when a corresponding first scanning line and a scanning line which is started before the first scanning line are started, and is in a connected state when a corresponding second scanning line and a scanning line which is started after the second scanning line are started.

3. The display according to claim 1, further comprising a driving circuit for driving the display panel to display, wherein the driving circuit comprises a data driver located at a periphery of a first side of the display panel, and the data driver is electrically connected to the M data lines, respectively; wherein the first side is perpendicular to the column direction;

the preset direction is a direction from far away from the data driver to close to the data driver; for each switch module, in a frame display period, the switch module is in a conducting state when a corresponding first scanning line and a scanning line which is started before the first scanning line are started, and is in a disconnecting state when a corresponding second scanning line and a scanning line which is started after the second scanning line are started.

4. A display as claimed in claim 2 or 3, characterised in that the at least one switching module comprises at least one row of switching modules; each row of switch modules comprises M switch modules, and the M switch modules contained in each row are connected in series on the M data lines in a one-to-one correspondence manner;

the first scanning lines corresponding to the switch modules in the same row are the same scanning line, and the first scanning lines corresponding to the switch modules in different rows are different scanning lines.

5. The display of claim 4, wherein the at least one switch module comprises a plurality of rows of the switch modules; in the plurality of switch modules electrically connected to the same data line, x pixel units are arranged between the first scanning lines corresponding to any two adjacent switch modules at intervals, wherein x is more than or equal to 1.

6. The display of claim 5, wherein the at least one switch module comprises a row of switch modules, and the first scan line corresponding to each switch module is an ith row of data lines; wherein i is the integer value of N/2.

7. The display of claim 4, wherein the driving circuit further comprises a control signal generation module to generate a plurality of control signals;

the display panel also comprises a plurality of control lines, each control line extends along the row direction, the plurality of control lines correspond to the plurality of rows of switch modules one by one, and the control ends of the M switch modules contained in each row are respectively and electrically connected with the corresponding control lines; each control signal is used for switching the on state and the off state of the switch module of the corresponding row.

8. The display of claim 7, wherein each of the switch modules comprises a transistor.

9. The display of claim 8, wherein each of said pixel cells includes a scan transistor;

the driving circuit further comprises a gate driver positioned at the periphery of the second side edge of the display panel, the gate driver is electrically connected with the control ends of the scanning transistors in the N rows through the N scanning lines respectively, and the gate driver is used for starting the N scanning lines line by line along the preset direction to enable the scanning transistors in the pixel units in the N rows to be conducted line by line, so that the pixel units in the N rows are scanned line by line; wherein the second side edge is perpendicular to the first side edge;

the type of the transistor in the switching module is the same as the type of the scan transistor.

10. The display of claim 9, wherein the driving circuit further comprises a timing controller, the timing controller is further configured to generate a frame start signal, the frame start signal is configured to start the gate driver to turn on N scan lines row by row in the preset direction, and is configured to trigger the control signal generating module to generate a plurality of the control signals.