CN116168656A - Array substrate and display panel - Google Patents
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- CN116168656A CN116168656A CN202211728548.9A CN202211728548A CN116168656A CN 116168656 A CN116168656 A CN 116168656A CN 202211728548 A CN202211728548 A CN 202211728548A CN 116168656 A CN116168656 A CN 116168656A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The application provides an array substrate and a display panel, which comprise n scanning lines, m data lines and a plurality of pixel units which are arranged in an array mode, wherein the pixel units are used for receiving scanning signals from the scanning lines and receiving data signals from the data lines for image display under the control of the scanning signals. The array substrate further comprises a mode conversion circuit, when the mode conversion circuit receives the first mode control signal, the pixel units are controlled to execute a first display mode, wherein two pixel units which are adjacently arranged along the second direction receive data signals with the same polarity for image display, and when the mode conversion circuit receives the second mode control signal, the pixel units are controlled to execute a second display mode, and two pixel units which are adjacently arranged along the second direction receive data signals with opposite polarities for image display. Through the switching of the display modes, the pixel units can be effectively controlled to receive data signals with the same or different polarities, so that different image display modes are compatible, and the image display effect is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
The liquid crystal display panel (Liquid Crystal Display, LCD) has been widely used in electronic devices such as computers, mobile phones and televisions, and most of the liquid crystal display panels can support the mutual conversion between high-frequency refresh and low-frequency refresh, and the common high-frequency and low-frequency conversion method is to control two adjacent rows of pixels to refresh and receive the same data signal simultaneously so as to display an image, thereby improving the refresh rate, but the resolution of the image will be reduced by half at this time, and the precondition of changing the refresh rate by using the method is that the data signals received by the adjacent pixels on the same data line must be the same polarity, but the polarities of the data signals received by the pixels which are usually adjacent to achieve better definition and display effect are opposite.
Therefore, how to adjust the data signals with different polarities received by the pixels to be compatible with the two display modes is a need to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings, the present application provides an array substrate and a display panel capable of effectively adjusting the polarity of data signals received by a pixel unit.
The application provides an array substrate, including n scan lines that extend along the first direction and arrange in proper order along the second direction, m data lines that extend along the second direction and arrange in proper order along the first direction and a plurality of pixel units that are the array and arrange, wherein, n, m are the positive integer that is greater than 1, and pixel unit is used for receiving scanning signal from the scan line and receiving data signal from the data line under scanning signal's control and carries out image display. The array substrate further comprises a mode conversion circuit, wherein the mode conversion circuit is used for controlling the pixel units to execute a first display mode or a second display mode, when the mode conversion circuit receives a first mode control signal, the pixel units are controlled to execute the first display mode, wherein two pixel units which are adjacently arranged along a second direction receive data signals with the same polarity for image display, and when the mode conversion circuit receives a second mode control signal, the pixel units are controlled to execute the second display mode, and two pixel units which are adjacently arranged along the second direction receive data signals with opposite polarities for image display.
Optionally, the mode conversion circuit includes a plurality of conversion units, the ith scan line is connected to the first pixel unit and is used for directly outputting a scan signal to the first pixel unit to control the first pixel unit to receive a data signal of a first polarity, the (i+1) th scan line is connected to the conversion unit and is connected to the second pixel unit through the conversion unit, the conversion unit controls the second pixel unit to receive the data signal of the first polarity according to the first mode control signal, and controls the second pixel unit to receive the data signal of a second polarity according to the second mode control signal; wherein i is more than or equal to 1 and less than or equal to n-1, and the first pixel unit and the second pixel unit are two pixel units which are adjacently arranged along the second direction.
Optionally, the array substrate further includes a scan driving circuit, the scan driving circuit is used for connecting n scan signals and outputting the scan signals correspondingly, the mode conversion circuit further includes a first control line, a second control line, a first signal transmission line and a second signal transmission line, and the conversion unit is connected to the first control line, the second control line and the scan driving circuit and is connected to the second pixel unit through the first signal transmission line and the second signal transmission line. When the conversion unit receives the first mode control signal from the first control line, the conversion unit transmits the scanning signal output by the scanning driving circuit to the second pixel unit through the first transmission line so as to control the second pixel unit to receive the data signal with the first polarity. When the conversion unit receives the second mode control signal from the second control line, the conversion unit transmits the received scanning signal to the second pixel unit through the second transmission line so as to control the second pixel unit to receive the data signal with the second polarity.
Optionally, the second pixel unit is connected to the first data line and the second data line, where the first data line and the second data line are two data lines that are adjacently arranged, and when the second pixel unit receives the scanning signal from the first signal transmission line, the second pixel unit receives the data signal of the first polarity from the first data line. When the second pixel unit receives the scanning signal from the second signal transmission line, the second pixel unit receives the data signal with the second polarity from the second data line.
Optionally, the conversion unit includes a first switching tube and a second switching tube, where a gate of the first switching tube is connected to a first control line and is used to receive a first mode control signal, a source of the first switching tube is connected to the scan driving circuit through a scan line, and a drain of the first switching tube is connected to the second pixel unit through a first signal transmission line and is used to be turned on under control of the first mode control signal to transmit a scan signal output by the scan driving circuit to the second pixel unit so as to control the second pixel unit to receive a data signal of a first polarity from the first data line. The grid electrode of the second switching tube is connected to the second control line and used for receiving a second mode control signal, the source electrode of the second switching tube is connected to the scanning driving circuit through the scanning line, the drain electrode of the second switching tube is connected to the second pixel unit through the second signal line and used for transmitting the scanning signal to the second pixel unit under the control of the second mode control signal so as to control the second pixel unit to receive a data signal with a second polarity from the second data line.
Optionally, the converting unit further includes a third switching tube and a fourth switching tube, a gate of the third switching tube is connected to the first control line and is used for receiving the first mode control signal, a source of the third switching tube is connected to the low voltage end, a drain of the third switching tube is connected to the second signal transmission line and is used for being conducted under the control of the first mode control signal to transmit the low voltage output by the low voltage end to the second pixel unit so as to control the second pixel unit to stop receiving the data signal of the second polarity from the second data line. The grid electrode of the fourth switching tube is connected to the second control line and used for receiving a second mode control signal, the source electrode of the fourth switching tube is connected to the low-voltage end, the drain electrode of the fourth switching tube is connected to the first signal transmission line and used for conducting under the control of the second mode control signal so as to transmit low voltage to the second pixel unit, and the second pixel unit is controlled to stop receiving data signals of the first polarity from the first data line.
Optionally, the second pixel unit includes a first transistor, a second transistor, a storage capacitor and a liquid crystal capacitor, where a gate of the first transistor is connected to the first signal transmission line and is used for receiving the scan signal from the first signal transmission line, a source of the first transistor is connected to the first data line, a drain of the first transistor is connected to the storage capacitor and the liquid crystal capacitor, and when the first transistor is turned on under control of the scan signal, the storage capacitor and the liquid crystal capacitor receive the data signal of the first polarity from the first data line to charge, and perform image display according to the data signal of the first polarity. The grid electrode of the second transistor is connected to the second signal transmission line and used for receiving the scanning signal from the second signal transmission line, the source electrode of the second transistor is connected to the second data line, the drain electrode of the second transistor is connected to the storage capacitor and the liquid crystal capacitor, when the second transistor is conducted under the control of the scanning signal, the storage capacitor and the liquid crystal capacitor receive the data signal with the second polarity from the second data line to charge, and image display is executed according to the data signal with the second polarity.
Optionally, when the first transistor is turned on under the control of the scan signal, the gate of the second transistor is connected to the low voltage terminal via the second signal transmission line and the third switching tube, and is used for receiving the low voltage from the low voltage terminal and is in an off state under the control of the low voltage. When the second transistor is turned on under the control of the scanning signal, the gate of the first transistor is connected to the low voltage end through the first signal transmission line and the fourth switching tube, and is used for receiving low voltage from the low voltage end and is in an off state under the control of the low voltage.
Optionally, when the pixel unit executes the first display mode, the pixel unit in the ith row and the pixel unit in the (i+1) th row are simultaneously turned on under the control of the scanning signal and receive the same data signal to display an image, wherein i is greater than or equal to 1 and less than or equal to n-1.
Optionally, when the pixel unit executes the first display mode, the ith row of pixel units receives the ith data signal for image display, the (i+2) th row of pixel units receives the (i+2) th data signal for image display, and the (i+1) th row of pixel units receives the (i+2) th data signal of the first duration and the (i+2) th data signal of the second duration for image display, wherein the first duration is longer than the second duration.
The application also discloses a display panel, which comprises a data driving circuit and the array substrate, wherein the data driving circuit is used for outputting data signals, and the scanning driving circuit arranged on the array substrate is used for outputting scanning signals to the pixel units so as to control the pixel units to receive the data signals and execute image display.
Compared with the prior art, the polarity of the data signals received by the pixel units can be effectively controlled by controlling the conversion of the display modes of the display panel, so that the corresponding display modes can be set according to specific image display requirements. Through compatible first display mode and second display mode for display panel can change display mode according to user's specific needs, thereby promotes the practicality of product.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic side view of a display terminal according to a first embodiment of the present application;
FIG. 2 is a schematic plan layout of the display panel of FIG. 1;
FIG. 3 is a schematic diagram of an equivalent circuit of the array substrate in FIG. 2;
FIG. 4 is a schematic diagram of polarities of data signals in the first display mode of FIG. 3;
FIG. 5 is a timing diagram of the scan signal output in the first display mode of FIG. 4;
FIG. 6 is a schematic diagram showing the effect of the pixel unit in FIG. 5;
FIG. 7 is a timing diagram of another scan signal output in the first display mode of FIG. 4;
FIG. 8 is a schematic diagram showing the effect of the pixel unit in FIG. 7;
FIG. 9 is a schematic diagram of polarities of data signals in the second display mode of FIG. 3.
Reference numerals illustrate:
the display terminal-100, the display panel-10, the backlight module-20, the display area-10 a, the non-display area-10 b, the array substrate-10 c, the color film substrate-10 d, the liquid crystal layer-10 e, the pixel unit-P, the Data lines-S1-Sm, the scanning lines-G1-Gn, the first direction-F1, the second direction-F2, the time sequence control circuit-11, the Data driving circuit-12, the scanning driving circuit-13, the mode converting circuit-14, the converting unit-141, the first pixel unit-P1, the second pixel unit-P2, the first scanning line-G1, the second scanning line-G2, the first control line-A1, the second control line-A2, the first switching tube-M1 a second switch tube-M2, a third switch tube-M3, a fourth switch tube-M4, a low-voltage end-Vss, a first signal transmission line-L1, a second signal transmission line-L2, a first transistor-T1, a second transistor-T2, a storage capacitor-Cst, a liquid crystal capacitor-Clc, a first common voltage end-Vcom 1, a second common voltage end Vcom2, a first Data line-S1, a second Data line-S2, a first scanning signal-G (1), a second scanning signal-G (2), a third scanning signal-G (3), a fourth scanning signal-G (4), an n-1 scanning signal-G (n-1), an n scanning signal-G (n), a first Data signal-Data (1), third Data signal-Data (3), first duration-t 1, second duration-t 2.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.
Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic side view of a display terminal according to a first embodiment of the present application. As shown in fig. 1, the display terminal 100 includes a display panel 10 and a backlight module 20 (Back light Module, BM), wherein the backlight module 20 is used for providing light for display to the display panel 10.
In an exemplary embodiment, the display terminal 100 further includes a power module for providing a driving power for the functional units in the display terminal 100, a signal processing module for performing parsing processing on the original image signal, and the like. Of course, other functional modules may be included, which the present application does not limit.
The display panel 10 includes a display region 10a for an image and a non-display region 10b. The display area 10a is used for performing image display, and the non-display area 10b is disposed around the display area 10a to dispose other auxiliary components or modules. Specifically, the display panel 10 includes an Array Substrate (AS) 10c, a color film substrate (Color film substrate, CF) 10d, and a liquid crystal layer 10e interposed between the Array substrate 10c and the color film substrate 10 d. The array substrate 10c and the color film substrate 10d are provided with driving elements for generating corresponding electric fields according to the Data signals (Data), so as to drive the rotation angles of the liquid crystal molecules in the liquid crystal layer 10e to emit light rays with corresponding brightness, and image display is performed.
Referring to fig. 2, fig. 2 is a schematic plan layout of the display panel 10 in fig. 1. As shown in fig. 2, the array substrate 10c includes a plurality of m×n Pixel units (pixels) P, m Data lines (Data lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn arranged in a matrix, where m and n are natural numbers greater than 1.
The m data lines S1 to Sm are insulated from each other by a first predetermined distance along the second direction F2 and are arranged in parallel, the n scan lines G1 to Gn are also insulated from each other by a second predetermined distance along the first direction F1 and are arranged in parallel, and the n scan lines G1 to Gn are insulated from the m data lines S1 to Sm, and the first direction F1 and the second direction F2 are perpendicular to each other.
A timing control circuit 11, a data driving circuit 12, a scanning driving circuit 13, and a mode conversion circuit 14 for driving the pixel units P to display an image are provided corresponding to the non-display region 10b of the display panel 10.
The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is configured to generate and output timing control signals to the data driving circuit 12 and the scan driving circuit 13, wherein the data timing signals in the timing control signals are output to the data driving circuit and the scan timing signals in the timing control signals are output to the scan driving circuit 13.
The data driving circuit 12 is electrically connected to the m data lines S1 to Sm, and is configured to output a data signal according to the received data timing signal and transmit the data signal to the plurality of pixel units P in the form of data voltages through the n data lines S1 to Sm so as to drive the pixel units P to display images.
The scan driving circuit 13 is electrically connected to the n scan lines G1 to Gn, and is configured to output a scan signal Gn through the n scan lines G1 to Gn according to the received scan timing signal so as to control when the pixel unit P receives the data signal. The scan driving circuit 13 sequentially outputs scan signals from the n scan lines G1 to Gn in the position arrangement order from the scan lines G1, G2, … …, gn in the scan period.
The mode conversion circuit 14 is connected to the timing control circuit 11, the scan driving circuit 13, and the plurality of pixel units P arranged in an array, and the mode conversion circuit 14 is configured to receive a mode control signal from the timing control circuit 11 and control the plurality of pixel units P to execute the first display mode or the second display mode according to the mode control signal. The mode control signals include a first mode control signal and a second mode control signal, and when the mode conversion circuit 14 receives the first mode control signal, the pixel units are controlled to execute a first display mode, wherein two pixel units P adjacently arranged along the second direction receive data signals with the same polarity for image display, and when the mode conversion circuit 14 receives the second mode control signal, the pixel units P are controlled to execute a second display mode, and two pixel units P adjacently arranged along the second direction receive data signals with opposite polarities for image display.
In the present embodiment, the circuit elements in the scan driving circuit 13 and the mode converting circuit 14 are fabricated in the array substrate 10c by the same process as the pixel units P in the display panel 10, i.e. GOA (Gate Driver on Array) technology.
Referring to fig. 3, fig. 3 is an equivalent circuit schematic diagram of the array substrate in fig. 2.
As shown in fig. 3, the mode conversion circuit 14 includes a plurality of conversion units 141, a first control line A1 and a second control line A2, wherein, among two scan lines disposed adjacently, an ith scan line is connected to the first pixel unit P1 for directly outputting a scan signal to the first pixel unit P1 to control the first pixel unit P1 to receive a data signal of a first polarity. The (i+1) th scan line is connected to the conversion unit 141 and connected to the second pixel unit P2 through the conversion unit 141, the conversion unit 141 controls the second pixel unit P2 to receive the data signal of the first polarity according to the first mode control signal, and controls the second pixel unit P2 to receive the data signal of the second polarity according to the second mode control signal; wherein i is more than or equal to 1 and less than or equal to n-1, the first polarity is opposite to the second polarity, and the first pixel unit P1 and the second pixel unit P2 are two pixel units adjacently arranged along the second direction.
In an exemplary embodiment, the data signal of the first polarity may be a data signal of the positive polarity, and the data signal of the second polarity may be a data signal of the negative polarity, and the data signal of the first polarity may also be a data signal of the negative polarity, and the data signal of the second polarity may be a data signal of the positive polarity.
For example, taking the first scan line G1 and the second scan line G2 as an example, the first scan line G1 is connected to the first pixel unit P1 for directly outputting the scan signal to the first pixel unit P1 to control the first pixel unit P1 to receive the data signal of the first polarity. The 2 nd scan line is connected to the conversion unit 141 and connected to the second pixel unit P2 through the conversion unit 141, and is configured to output a scan signal to the second pixel unit P2, so as to control the second pixel unit P2 to receive the data signal of the first polarity or receive the data signal of the second polarity.
The mode conversion circuit 14 further includes a first control line A1, a second control line A2, a first signal transmission line L1 and a second signal transmission line L2. The conversion unit 141 is connected to the first control line A1 and the second control line A2, when the conversion unit 141 receives the first mode control signal from the first control line A1, the second pixel unit P2 receives the data signal of the first polarity under the control of the scan signal, and when the conversion unit 141 receives the second mode control signal from the second control line A2, the second pixel unit P2 receives the data signal of the second polarity under the control of the scan signal.
Specifically, the converting unit 141 includes a first switching tube M1, a second switching tube M2, a third switching tube M3, and a fourth switching tube M4, where a gate of the first switching tube M1 is connected to a first control line A1, and is configured to receive a first mode control signal from the first control line A1, and is turned on under the control of the first mode control signal, a source of the first switching tube M1 is connected to the scan driving circuit through a scan line, and a drain of the first switching tube M1 is connected to the second pixel unit P2 through a first signal transmission line L1, and is configured to transmit the scan signal output by the scan driving circuit to the second pixel unit P2.
The gate of the second switch M2 is connected to the second control line A2, and is configured to receive a second mode control signal from the second control line A2 and conduct under the control of the second mode control signal. The source electrode of the second switching tube M2 is connected to the scanning driving circuit through a scanning line, and the grid electrode of the second switching tube M2 is connected to the second pixel unit P2 through a second signal transmission line L2 and is used for transmitting a scanning signal output by the scanning driving circuit to the second pixel unit P2.
The gate of the third switching tube M3 is connected to the first control line A1, and is configured to receive the first mode control signal from the first control line A1, the source of the third switching tube M3 is connected to the low voltage terminal Vss, the drain of the third switching tube M3 is connected to the second signal transmission line L2, and when the third switching tube M3 is turned on under the control of the first mode control signal, the low voltage is transmitted to the second pixel unit P2 through the third switching tube M3.
The gate of the fourth switching tube M4 is connected to the second control line A2, and is configured to receive the second mode control signal from the second control line A2, the source of the fourth switching tube M4 is connected to the low voltage terminal Vss, the drain of the fourth switching tube M4 is connected to the first signal transmission line L1, and when the fourth switching tube M4 is turned on under the control of the second mode control signal, the low voltage is transmitted to the second pixel unit P2 through the fourth switching tube M4.
The second pixel unit P2 includes a first transistor T1, a second transistor T2, a storage capacitor Cst and a liquid crystal capacitor Clc, where a gate of the first transistor T1 is connected to the first signal transmission line L1 and is used for receiving a scanning signal from the first signal transmission line L1, a source of the first transistor T1 is connected to the first data line, a drain of the first transistor T1 is connected to the storage capacitor Cst and the liquid crystal capacitor Clc, and when the first transistor T1 is turned on under the control of the scanning signal, the first transistor T1 receives a data signal of a first polarity from the first data line and transmits the data signal to the storage capacitor Cst and the liquid crystal capacitor Clc for storing, and is used for driving liquid crystal molecules to rotate to emit light of a preset gray scale. One end of the storage capacitor Cst is connected to the drain of the first transistor T1, the other end is connected to the first common voltage terminal Vcom1, one end of the liquid crystal capacitor Clc is connected to the drain of the first transistor T1, and the other end is connected to the second common voltage terminal Vcom2. That is, the second pixel unit P2 and the first pixel unit P1 are connected to the same data line for receiving the data signals with the same polarity.
The gate of the second transistor T2 is connected to the second signal transmission line L2, for receiving the scanning signal from the second signal transmission line L2, the source of the second transistor T2 is connected to the second data line, the drain of the second transistor T2 is connected to the storage capacitor Cst and the liquid crystal capacitor Clc, and when the second transistor T2 is turned on under the control of the scanning signal, the second transistor T2 receives the data signal of the second polarity from the second data line and transmits the data signal to the storage capacitor Cst and the liquid crystal capacitor Clc, for driving the liquid crystal molecules to rotate so as to emit the light of the preset gray scale. The first data line and the second data line are two adjacent data lines. That is, the second pixel unit P2 is connected to different data lines for receiving data signals with opposite polarities from the first pixel unit P1.
Due to the arrangement of the third switching transistor M3 and the fourth switching transistor M4, when the first transistor T1 receives the scanning signal from the first signal transmission line L1 and is turned on, the second transistor T2 receives the low voltage from the second signal transmission line L2 and is in an off state, at this time, the source and the drain of the second transistor T2 are electrically disconnected, and when the second transistor T2 receives the scanning signal from the second signal transmission line L2 and is turned on, the first transistor T1 receives the low voltage from the first signal transmission line L1 and is in an off state, at this time, the source and the drain of the first transistor T1 are electrically disconnected.
The first pixel unit P1 includes a third transistor, a storage capacitor Cst and a liquid crystal capacitor Clc, where a gate of the third transistor is connected to the scan line, is used for receiving a scan signal from the scan line and is turned on under the control of the scan signal, a source of the third transistor is connected to the first data line, a drain of the third transistor is connected to the storage capacitor Cst and the liquid crystal capacitor Clc, and when the third transistor is turned on under the control of the scan signal, the third transistor is used for receiving a data signal of a first polarity from the first data line and transmitting the data signal to the storage capacitor Cst and the liquid crystal capacitor Clc, and is used for driving liquid crystal molecules to rotate to emit light of a preset gray scale.
Referring to fig. 4, fig. 4 is a schematic diagram of polarities of data signals in the first display mode in fig. 3. As shown in fig. 4, when the display panel performs the first display mode, two pixel units P adjacently disposed along the second direction receive the data signals having the same polarity, that is, the pixel units P connected to the same data line receive the data signals having the same polarity. Two adjacent data lines transmit data signals with opposite polarities. For example, the plurality of pixel cells P connected to the first data line S1 receive a positive polarity data signal, and the plurality of pixel cells P connected to the second data line S2 receive a negative polarity data signal.
Referring to fig. 5, fig. 5 is a timing diagram of the scan signal output in the first display mode in fig. 4.
As shown in fig. 5, the first scan signal G (1) and the second scan signal G (2) are simultaneously output, for controlling the first row of pixel units and the second row of pixel units to be simultaneously turned on to receive the same data signal, the third scan signal G (3) and the fourth scan signal G (4) are simultaneously output, for controlling the third row of pixel units and the fourth row of pixel units to be simultaneously turned on to receive the same data signal, and so on, the n-1 th scan signal G (n-1) and the n-th scan signal G (n) are simultaneously output, for controlling the n-1 th row of pixel units and the n-th row of pixel units to be simultaneously turned on and to receive the same data signal. The scanning signals in the two adjacent scanning lines are controlled to be output simultaneously, so that the two adjacent rows of pixel units are simultaneously opened to receive the same data signals for image display, the time for displaying one frame of image by the display panel is reduced by half due to the fact that the two adjacent rows of pixel units are simultaneously opened, and if the refresh rate of the original display panel is 60Hz, namely 60 frames of image are displayed in one second, the refresh rate of the display panel is 120Hz, namely 120 frames of image can be displayed in one second, and the refresh rate of the display panel is effectively improved.
Referring to fig. 6, fig. 6 is a schematic diagram showing the effect of the pixel unit shown in fig. 5.
As shown in fig. 6, the i+1th row pixel unit and the i+2th row pixel unit are turned on at the same time and receive the same data signal for image display, and the i+2th row pixel unit and the i+3rd row pixel unit are turned on at the same time and receive the same data signal for image display, so that two adjacent rows of pixels display the same image. For example, the first row pixel units and the second row pixel units are simultaneously turned on and receive the same data signal to display as white, and the third row pixel units and the fourth row pixel units are simultaneously turned on and receive the same data signal to display as black.
Referring to fig. 7, fig. 7 is a timing chart of another scan signal output in the first display mode in fig. 4.
As shown in fig. 7, the ith row of pixel units receives the ith data signal for image display, the (i+2) th row of pixel units receives the (i+2) th data signal for image display, and the (i+1) th row of pixel units receives the (i+2) th data signal for a first time period t1 and the (i+2) th data signal for a second time period t2 for image display, wherein the first time period t1 is longer than the second time period t2. Namely, the opening time of the second row of pixel units is delayed on the basis of controlling the simultaneous opening of the two adjacent rows of pixel units, so that the second row of pixel units receive the data signals corresponding to the first row of pixel units and simultaneously receive the data signals corresponding to the third row of pixel units with a certain time length.
For example, the first scan signal G (1) controls the first row of pixel cells to receive the first Data signal Data (1), the third scan signal G (3) controls the third row of pixel cells to receive the third Data signal Data (3), and the second scan signal G (2) controls the second row of pixel cells to receive the first Data signal Data (1) for the first period t1 and the third Data signal Data (3) for the second period. The gray scale displayed by the second row of pixel units is between the first row of pixel units and the third row of pixel units, so that when the image is displayed, the boundary with the difference of picture contrast is blurred, and the picture is smoother. And so on, the fourth row of pixel units receives the third Data signal Data (3) of the first time period t1 and the fifth Data signal of the fifth row of pixel units of the second time period t2 for image display to display images.
When the first row of pixel units and the second row of pixel units receive the first Data signal Data (1), the third row of pixel units are opened under the control of the third scanning signal to receive the first Data signal Data (1) with preset duration and used for pre-charging the third row of pixel units, when the third Data signal Data (3) is output to the third row of pixel units, the third row of pixel units receive the third Data signal Data (3) to charge, and the third row of pixel units continuously receive the third Data signal Data (3) with a certain duration after receiving the first Data signal Data (1) with preset duration, so that the third Data signal Data (3) covers the first Data signal Data (1), and the third row of pixel units perform image display according to the third Data signal Data (3).
Referring to fig. 8, fig. 8 is a schematic diagram illustrating an effect of the pixel unit shown in fig. 7.
As shown in fig. 8, the first row of pixel units is configured to receive the first Data signal Data (1) for image display, the third row of pixel units is configured to receive the third Data signal Data (3) for image display, so that the first row of pixel units is displayed as white according to the first Data signal Data (1), and the third row of pixel units is displayed as black according to the third Data signal Data (3), wherein the second row of pixel units receives the first Data signal Data (1) for a first time period t1 and the third Data signal Data (3) for a second time period t2, and the second row of pixel units is displayed as gray between white and black according to the first Data signal Data (1) and the third Data signal Data (3), so that the gray level displayed by the second row of pixel units is between the gray level displayed by the first row of pixel units and the gray level displayed by the third row of pixel units, and the boundary difference between the first row of pixel units and the third row of pixel units is neutralized, so that the image boundary is smoother.
Referring to fig. 9, fig. 9 is a schematic diagram of polarities of data signals in the second display mode in fig. 3.
As shown in fig. 9, when the display panel performs the second display mode, two pixel units disposed adjacent in the second direction receive data signals of opposite polarities from different data lines, respectively. For example, the first pixel unit P1 receives a data signal of a first polarity from the first data line S1, and the second pixel unit P2 receives a data signal of a second polarity from the second data line S2.
The polarity of the data signals received by the pixel units can be effectively controlled by controlling the conversion of the display modes of the display panel, so that the corresponding display modes can be set according to specific image display requirements, when the display panel is controlled to execute the first display mode, the image refresh rate can be effectively improved, and when the display panel is controlled to execute the second display mode, the definition of image display can be effectively improved, so that the picture is finer. Through compatible first display mode and second display mode for display panel can change display mode according to user's specific needs, thereby promotes the practicality of product.
It is to be understood that the application of the present application is not limited to the examples described above, but that modifications and variations can be made by a person skilled in the art from the above description, all of which modifications and variations are intended to fall within the scope of the claims appended hereto.
Claims (10)
1. An array substrate comprises n scanning lines extending along a first direction and sequentially arranged along a second direction, m data lines extending along the second direction and sequentially arranged along the first direction, and a plurality of pixel units arranged in an array, wherein n and m are positive integers larger than 1, and the pixel units are used for receiving scanning signals from the scanning lines and receiving data signals from the data lines for image display under the control of the scanning signals;
the array substrate is characterized by further comprising a mode conversion circuit, wherein the mode conversion circuit is used for controlling the pixel units to execute a first display mode or a second display mode, when the mode conversion circuit receives a first mode control signal, the pixel units are controlled to execute the first display mode, wherein two pixel units which are adjacently arranged along the second direction receive data signals with the same polarity for image display, when the mode conversion circuit receives a second mode control signal, the pixel units are controlled to execute the second display mode, and two pixel units which are adjacently arranged along the second direction receive data signals with opposite polarities for image display.
2. The array substrate of claim 1, wherein the mode conversion circuit comprises a plurality of conversion units, an i-th scan line is connected to a first pixel unit and is used for directly outputting the scan signal to the first pixel unit to control the first pixel unit to receive a data signal of a first polarity, an i+1-th scan line is connected to the conversion unit and is connected to a second pixel unit through the conversion unit, the conversion unit controls the second pixel unit to receive the data signal of the first polarity according to the first mode control signal, and controls the second pixel unit to receive the data signal of the second polarity according to the second mode control signal; wherein i is more than or equal to 1 and less than or equal to n-1, and the first pixel unit and the second pixel unit are two pixel units adjacently arranged along the second direction.
3. The array substrate of claim 2, further comprising a scan driving circuit for connecting the n scan signals and outputting the scan signals correspondingly,
the mode conversion circuit further comprises a first control line, a second control line, a first signal transmission line and a second signal transmission line, wherein the conversion unit is connected to the first control line, the second control line and the scanning driving circuit and is connected to the second pixel unit through the first signal transmission line and the second signal transmission line;
when the conversion unit receives a first mode control signal from the first control line, the conversion unit transmits the scanning signal output by the scanning driving circuit to the second pixel unit through the first transmission line so as to control the second pixel unit to receive the data signal of the first polarity;
when the conversion unit receives a second mode control signal from the second control line, the conversion unit transmits the received scanning signal to the second pixel unit through the second transmission line so as to control the second pixel unit to receive the data signal with the second polarity.
4. The array substrate of claim 3, wherein the second pixel unit is connected to a first data line and a second data line, the first data line and the second data line are two data lines adjacently arranged,
when the second pixel unit receives the scanning signal from the first signal transmission line, the second pixel unit receives the data signal of the first polarity from the first data line;
when the second pixel unit receives the scanning signal from the second signal transmission line, the second pixel unit receives the data signal of the second polarity from the second data line.
5. The array substrate of claim 4, wherein the switching unit includes a first switching tube and a second switching tube, a gate of the first switching tube is connected to the first control line and is used for receiving the first mode control signal, a source of the first switching tube is connected to the scan driving circuit via the scan line, a drain of the first switching tube is connected to the second pixel unit via a first signal transmission line and is used for being conducted under control of the first mode control signal to transmit the scan signal output by the scan driving circuit to the second pixel unit so as to control the second pixel unit to receive the data signal of the first polarity from the first data line;
the grid electrode of the second switching tube is connected to the second control line and is used for receiving the second mode control signal, the source electrode of the second switching tube is connected to the scanning driving circuit through the scanning line, the drain electrode of the second switching tube is connected to the second pixel unit through a second signal line and is used for transmitting the scanning signal to the second pixel unit under the control of the second mode control signal so as to control the second pixel unit to receive the data signal with the second polarity from the second data line.
6. The array substrate of claim 5, wherein the switching unit further comprises a third switching tube and a fourth switching tube, a gate of the third switching tube is connected to the first control line for receiving the first mode control signal, a source of the third switching tube is connected to a low voltage terminal, a drain of the third switching tube is connected to the second signal transmission line for conducting under the control of the first mode control signal to transmit the low voltage output from the low voltage terminal to the second pixel unit for controlling the second pixel unit to stop receiving the data signal of the second polarity from the second data line;
the grid electrode of the fourth switching tube is connected to the second control line and used for receiving the second mode control signal, the source electrode of the fourth switching tube is connected to the low-voltage end, the drain electrode of the fourth switching tube is connected to the first signal transmission line and used for conducting under the control of the second mode control signal so as to transmit the low voltage to the second pixel unit, and the second pixel unit is controlled to stop receiving the data signal of the first polarity from the first data line.
7. The array substrate of claim 6, wherein the second pixel unit includes a first transistor, a second transistor, a storage capacitor and a liquid crystal capacitor, the gate of the first transistor is connected to the first signal transmission line for receiving the scan signal from the first signal transmission line, the source of the first transistor is connected to the first data line, the drain of the first transistor is connected to the storage capacitor and the liquid crystal capacitor, and when the first transistor is turned on under the control of the scan signal, the storage capacitor and the liquid crystal capacitor receive the data signal of the first polarity from the first data line to charge and perform image display according to the data signal of the first polarity;
the grid electrode of the second transistor is connected to a second signal transmission line and is used for receiving the scanning signal from the second signal transmission line, the source electrode of the second transistor is connected to the second data line, the drain electrode of the second transistor is connected to the storage capacitor and the liquid crystal capacitor, and when the second transistor is conducted under the control of the scanning signal, the storage capacitor and the liquid crystal capacitor receive the data signal with the second polarity from the second data line to charge and execute image display according to the data signal with the second polarity.
8. The array substrate of any one of claims 1 to 7, wherein when the pixel unit performs the first display mode, the i-th row of pixel units and the i+1-th row of pixel units are simultaneously turned on and receive the same data signal under the control of the scan signal to perform image display, wherein 1.ltoreq.i.ltoreq.n-1.
9. The array substrate of any one of claims 1-7, wherein when the pixel unit performs the first display mode, an i-th row of pixel units receives an i-th data signal for image display, an i+2-th row of pixel units receives an i+2-th data signal for image display, and an i+1-th row of pixel units receives the i-th data signal for a first duration and the i+2-th data signal for a second duration, wherein the first duration is longer than the second duration.
10. A display panel, comprising a data driving circuit and an array substrate according to any one of claims 1 to 9, wherein the data driving circuit is configured to output a data signal, and the scan driving circuit disposed on the array substrate is configured to output the scan signal to the pixel unit to control the pixel unit to receive the data signal to perform image display.
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| CN202211728548.9A CN116168656A (en) | 2022-12-29 | 2022-12-29 | Array substrate and display panel |
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| CN202211728548.9A CN116168656A (en) | 2022-12-29 | 2022-12-29 | Array substrate and display panel |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116758865A (en) * | 2023-06-29 | 2023-09-15 | 重庆惠科金渝光电科技有限公司 | Display panel, driving method thereof and electronic equipment |
| CN117316114A (en) * | 2023-11-08 | 2023-12-29 | 惠科股份有限公司 | Display panel and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116758865A (en) * | 2023-06-29 | 2023-09-15 | 重庆惠科金渝光电科技有限公司 | Display panel, driving method thereof and electronic equipment |
| CN117316114A (en) * | 2023-11-08 | 2023-12-29 | 惠科股份有限公司 | Display panel and display device |
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