CN109410882A - GOA circuit and liquid crystal display panel - Google Patents
GOA circuit and liquid crystal display panel Download PDFInfo
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- CN109410882A CN109410882A CN201811582370.5A CN201811582370A CN109410882A CN 109410882 A CN109410882 A CN 109410882A CN 201811582370 A CN201811582370 A CN 201811582370A CN 109410882 A CN109410882 A CN 109410882A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
Abstract
The invention discloses a kind of GOA circuit, multistage GOA driving unit and i clock signal connecting line including cascade setting, sequence controller corresponds to input clock signal CK to i clock signal connecting line1~CKi, the multistage GOA driving unit is successively divided into several groups according to cascade sequence, and each group respectively includes m grades of GOA driving units；In each group of GOA driving unit, the 1st to i-stage GOA driving unit is connected to the i articles of clock signal connecting line correspondingly respectively to receive clock signal CK1~CKi, i+1 to m grades of GOA driving units is connected to the i articles of clock signal connecting line by i phase inverter correspondingly, and the i phase inverter will be from the received clock signal CK of the i clock signal connecting line1~CKiBe converted to inverting clock signal XCK1~XCKiOutput is to the i+1 to m grades of GOA driving units；Wherein, i is the integer more than or equal to 1, m=2i.The invention also discloses a kind of liquid crystal display panels comprising GOA circuit as described above.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of GOA circuit, further relate to comprising GOA circuit as above
Liquid crystal display panel.
Background technique
In active liquid crystal display device, each pixel has a thin film transistor (TFT) (TFT), grid (Gate) connection
To horizontal scanning line, drain electrode (Drain) is connected to the data line of vertical direction, and source electrode (Source) is then connected to pixel electrode.
Apply enough voltage on horizontal scanning line, all TFT on this bar line can be made to open, at this time on the horizontal scanning line
Pixel electrode can be connect with the data line of vertical direction, so that control is not by the display signal voltage writing pixel on data line
Light transmittance with liquid crystal achievees the effect that control color in turn.The driving master of current active liquid crystal display panel horizontal scanning line
It to be completed by the external IC of panel, external IC can control the charging and discharging step by step of horizontal scanning lines at different levels.And GOA skill
Art, i.e. Gate Driver on Array (driving of array substrate row) technology can use original processing procedure of liquid crystal display panel
The driving circuit of horizontal scanning line is produced on the substrate around viewing area, makes it to substitute external IC to complete horizontal sweep
The driving of line.GOA technology can be reduced binding (bonding) process of external IC, has an opportunity to promote production capacity and reduces product cost,
And liquid crystal display panel can be made to be more suitable for making the display product of narrow frame or Rimless.
Existing GOA circuit generally includes cascade multistage GOA driving unit, the corresponding driving of every level-one GOA driving unit
Primary plateaus scan line.The primary structure of existing GOA driving unit includes pull-up control module (Pull-up control
Part), pull-up module (Pull-up part), grade transmission module (Transfer Part), pull-down module (Key Pull-down
Part) and drop-down maintenance module (Pull-down Holding Part) and responsible current potential lifting bootstrapping (Boast) electricity
Hold.By taking the GOA circuit of 2 CK input signals as an example, for n-th grade of GOA unit, pulls up control module and be responsible for controlling pull-up module
With the opening time of grade transmission module, the scanning drive signal G generally passed over according to previous stage GOA driving unitn-1It is passed with grade
Signal STn-1, export the grid control signal Q of the same level circuitn(commonly referred to as Q point)；Pull-up module and grade transmission module are by grid control
Signal Q processednControl, is mainly responsible for the scanning drive signal G that the same level clock signal CK is converted to the same level circuitN andGrade communication number
STn, pull-down module is responsible for grid control signal Q in first timenWith scanning drive signal GnDown for low potential, that is, connecing
Receive the scanning drive signal G for the high level that rear stage GOA circuit unit passes overn+1When, at the first time by the same level circuit
Grid control signal QnWith scanning drive signal GnScanning signal is closed down for low potential；Maintenance module is pulled down then to be responsible for inciting somebody to action this
The grid control signal Q of grade circuitnWith scanning drive signal GnMaintain (Holding) in off position (i.e. low level current potential)；From
The secondary lifting that capacitor (C boast) is then responsible for Q point is lifted, output the same level turntable driving can be stablized by being conducive to pull-up module in this way
Signal Gn。
In GOA circuit, clock signal CK is provided by external control chip, usually timing controller
(Tcon), timing controller needs to input the clock signal of out of phase into GOA circuit, and to realize, output scanning is driven step by step
Dynamic signal.In the prior art, if GOA circuit needs 2 clock signals, then timing controller needs output phase opposite
Two clock signal CK1And CK2To adjacent two-stage GOA driving unit；If GOA circuit needs 4 clock signals, then timing
4 clock signal CK that control chip needs output phase different1~CK4To continuous level Four GOA driving unit.With liquid crystal
The size of panel becomes greatly, and the quantity of clock signal is also more and more, and 6CK, 8CK clock signal are more and more applied to
In the circuit structure of liquid crystal display panel.The clock signal quantity needed in GOA circuit increases, and causes to provide the timing control of clock signal
The design difficulty and cost of coremaking piece also increase.
Therefore, the existing technology needs to be improved and developed.
Summary of the invention
In view of the deficiencies in the prior art, the present invention provides a kind of GOA circuit, which can make by timing control
The quantity for the initial clock signal that coremaking piece provides reduces half, thus reduces the design difficulty and cost of timing controller.
To achieve the goals above, present invention employs the following technical solutions:
A kind of GOA circuit, multistage GOA driving unit and clock signal connecting line including cascade setting, the clock letter
The GOA driving unit is connected to sequence controller by number connecting line, wherein the GOA circuit includes i clock signal connection
Line, the sequence controller correspond to input clock signal CK to the i clock signal connecting line1~CKi, the multistage GOA drive
Moving cell is successively divided into several groups according to cascade sequence, and each group respectively includes m grades of GOA driving units；
Wherein, in each group of GOA driving unit, the 1st to i-stage GOA driving unit is connected to institute correspondingly respectively
I clock signal connecting line is stated to receive clock signal CK1~CKi, i+1 to m grades of GOA driving units passes through i phase inverter
It is connected to the i clock signal connecting line correspondingly, the i phase inverter will be from the i clock signal connecting line
Received clock signal CK1~CKiBe converted to inverting clock signal XCK1~XCKiOutput is driven to the i+1 to m grades of GOA
Moving cell；
Wherein, i is the integer more than or equal to 1, m=2i.
Preferably, the i value is 1,2,3 or 4.
Specifically, every level-one GOA driving unit include pull-up control module, pull-up module, grade transmission module, bootstrap capacitor,
Pull-down module and drop-down maintenance module；Wherein, in n-th grade of GOA driving unit:
The scanning drive signal and grade communication number that the pull-up control module is generated according to the n-th-i grades of GOA driving unit are controlled
System generates grid control signal；
The pull-up module and the grade transmission module are controlled by the grid control signal respectively, correspond to this for what is received
The clock signal of grade is converted to the same level scanning drive signal and the output of grade communication number；
The bootstrap capacitor is connected between the output end of the pull-up control module and the output end of the pull-up module,
For making the pull-up module stablize output the same level scanning drive signal；
The pull-down module is controlled according to the scanning drive signal that the n-th+i grades of GOA driving unit generates by the grid control
Signal processed and the same level scanning drive signal are pulled low to benchmark low level signal；
The drop-down maintenance module is coupled to the grid control signal and the same level scanning drive signal and benchmark low level
Between signal, for the grid control signal and the maintenance of the same level scanning drive signal to be pulled low to benchmark low level signal；
Wherein, if n-th grade of GOA driving unit corresponds to the described 1st one of to i-stage GOA driving unit, institute
It states pull-up module and the grade transmission module is connected to the clock signal connecting line to receive corresponding clock signal CK1~CKi；
If n-th grade of GOA driving unit corresponds to the i+1 one of to m grades of GOA driving units, the pull-up module
Being connected to the phase inverter with the grade transmission module is output end to receive corresponding inverting clock signal XCK1~XCKi；
Wherein, n is the integer more than or equal to 1.
Specifically, the pull-up control module includes pull-up control transistor, and the source electrode of the pull-up control transistor connects
The scanning drive signal that the n-th-i grades of GOA driving unit generates is received, grid receives the grade communication that the n-th-i grades of GOA driving unit generates
Number, drain electrode exports the grid control signal.
Specifically, the pull-up module includes pulling up transistor, and the grid to pull up transistor is connected to the pull-up
The output end of control module, source electrode receive the clock signal of corresponding the same level, drain and export as the output end of the pull-up module
The same level scanning drive signal.
Specifically, the grade transmission module includes that grade passes transistor, and the grid that the grade passes transistor is connected to the pull-up
The output end of control module, source electrode receive the clock signal of corresponding the same level, drain and export as the output end of the grade transmission module
The same level grade communication number.
Specifically, the pull-down module includes the first pull-down transistor and the second pull-down transistor, the described first lower crystal pulling
The source electrode of body pipe is connected to the same level scanning drive signal, and grid receives the turntable driving letter that the n-th+i grades of GOA driving unit generates
Number, drain electrode is connected to benchmark low level signal；The source electrode of second pull-down transistor is connected to the grid control signal, grid
Pole receives the scanning drive signal that the n-th+i grades of GOA driving unit generates, and drain electrode is connected to benchmark low level signal.
Specifically, the drop-down maintenance module includes the first transistor, second transistor, third transistor, the 4th crystal
Pipe, the 5th transistor, the 6th transistor；The grid of the first transistor connects with source electrode and receives benchmark high level signal,
Drain electrode is connect with the source electrode of the second transistor；The grid of the second transistor is connected to the grid control signal, leakage
Pole is connected to benchmark low level signal；The source electrode of the third transistor is connect with the source electrode of the first transistor, grid with
The drain electrode of the first transistor connects, and drain electrode is connect with the source electrode of the 4th transistor；The grid of 4th transistor
It is connected to the grid control signal, drain electrode is connected to benchmark low level signal；The source electrode of 5th transistor is connected to institute
Grid control signal is stated, grid is connect with the drain electrode of the third transistor, and drain electrode is connected to benchmark low level signal；Described
The source electrode of six transistors is connected to the same level scanning drive signal, and grid is connect with the drain electrode of the third transistor, drain electrode connection
To benchmark low level signal.
Specifically, the phase inverter is Darlington configuration phase inverter.
Another aspect of the present invention is to provide a kind of liquid crystal display panel comprising GOA circuit as described above.
The GOA circuit provided in the embodiment of the present invention, for the m grade GOA driving unit in same group, wherein half the (the 1st
To i-stage) it is connected to signal connecting line and receives clock signal CK correspondingly1~CKi, the other half (i+1 is to m grades) are logical
It crosses phase inverter and is connected to signal connecting line, receive inverting clock signal XCK correspondingly1~XCKi, needed as a result, in GOA circuit
Mono- timing of quantity m for the clock signal wanted, can be by quantity (i, the i=of the initial clock signal provided by timing controller
M/2 half) is reduced, to reduce the design difficulty and cost of timing controller.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of liquid crystal display panel provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of GOA circuit provided in an embodiment of the present invention；
Fig. 3 is the timing diagram of each group of received clock signal of GOA driving unit in the embodiment of the present invention；
Fig. 4 is the structural schematic diagram of every level-one GOA driving unit in the embodiment of the present invention；
Fig. 5 is the circuit diagram of every level-one GOA driving unit in the embodiment of the present invention；
Fig. 6 is the circuit diagram of the phase inverter in the embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, with reference to the accompanying drawing to specific reality of the invention
The mode of applying is described in detail.The example of these preferred embodiments is illustrated in the accompanying drawings.Shown in attached drawing and according to
The embodiments of the present invention of attached drawing description are only exemplary, and the present invention is not limited to these embodiments.
Here, it should also be noted that, in order to avoid having obscured the present invention because of unnecessary details, in the accompanying drawings only
Show with closely related structure and/or processing step according to the solution of the present invention, and be omitted little with relationship of the present invention
Other details.
A kind of liquid crystal display device is present embodiments provided, as shown in Figure 1, the liquid crystal display panel includes display area
200 and the GOA circuit 100 that is integrally disposed on 200 edge of display area, the GOA circuit 100 include the more of cascade setting
Grade GOA driving unit 1 provides scanning to 200 n-th grades of display area horizontal scanning line according to n-th grade of control of GOA driving unit 1
Driving signal, wherein n is the integer more than or equal to 1.
Normally, the liquid crystal display panel includes the thin-film transistor array base-plate being oppositely arranged and colorized optical filtering base
Plate further includes the liquid crystal layer that the thin-film transistor array base-plate and colored optical filtering substrates is arranged in.The wherein GOA circuit
100 are arranged on the thin-film transistor array base-plate.
In the present embodiment, in order to enable by timing controller provide initial clock signal quantity be reduced with
Its design difficulty and cost are reduced, a kind of new structural GOA circuit 100 is provided comprising the multistage GOA for cascading setting drives
The GOA driving unit is connected to sequence controller by moving cell and clock signal connecting line, the clock signal connecting line.Its
In, the GOA circuit includes i clock signal connecting line, and the sequence controller is corresponding to the i clock signal connecting line
Input clock signal CK1~CKi；Wherein, i is the integer more than or equal to 1.
Wherein, the multistage GOA driving unit is successively divided into several groups according to cascade sequence, and each group is wrapped respectively
Include m grades of GOA driving units.For example, GOA circuit 100 includes cascade N grades of GOA driving unit, it is successively divided into J group, every group of packet
M grades of GOA driving units are included, then N=J × m, wherein N, J and m are positive integer, and m=2i.More than it should be noted that
It is described to be successively divided into several groups according to cascade sequence and be specifically: for N grades of GOA driving units in total, the 1st group be include
1 grade to m grades m grades of GOA driving units in total, the 2nd group be include m+1 grades to 2m grades m grades of GOA driving units in total, according to
It is secondary to analogize, J group be include N-m grades to N grades m grades of GOA driving units in total.
Wherein, in each group of m in total grades of GOA driving unit, the clock signal that needs m phase different in total.Tool
Body, the 1st to i-stage GOA driving unit is connected to the i articles of clock signal connecting line correspondingly respectively to receive clock
Signal CK1~CKi, i+1 to m grades of GOA driving units is connected to the i bars of clock by i phase inverter correspondingly and believes
Number connecting line, the i phase inverter will be from the received clock signal CK of the i clock signal connecting line1~CKiIt is converted to anti-
Clock signal XCK1~XCKiOutput is to the i+1 to m grades of GOA driving units.
Based on the GOA circuit 100 that the above thinking provides, for the m grade GOA driving unit in same group, wherein half (the
1 to i-stage) it is connected to signal connecting line and receives clock signal CK correspondingly1~CKi, the other half (i+1 is to m grades) are logical
It crosses phase inverter and is connected to signal connecting line, receive inverting clock signal XCK correspondingly1~XCKi, needed as a result, in GOA circuit
Mono- timing of quantity m for the clock signal wanted, can be by quantity (i, the i=of the initial clock signal provided by timing controller
M/2 half) is reduced, to reduce the design difficulty and cost of timing controller.
For example, for the GOA circuit of current common 2CK, 4CK, 6CK and 8CK, i.e. m respectively corresponds 2,4,6 and 8, existing
Timing controller is needed directly to provide 2,4,6 initial clock signals different with 8 phases in technology.And in the present invention, by
The quantity i for the initial clock signal that timing controller provides is 1,2,3 and 4 respectively, that is, is provided by timing controller first
The quantity of beginning clock signal reduces half.
The present invention is described in detail by taking the GOA circuit of 4CK as an example below, i.e., above-described, GOA circuit 100
In, m=4, i=2.
As shown in Fig. 2, multistage GOA driving unit 1 and 2 clock signal that the GOA circuit 100 includes cascade setting connects
Wiring L1、L2, the clock signal connecting line L1、L2The GOA driving unit is connected to sequence controller 2.The timing control
Device 2 processed corresponds to input clock signal CK to 2 clock signal connecting lines1And CK2。
For each group of 4 grades of GOA driving units 1 in total, jth group therein is exported as exemplary in Fig. 2, including
Successively cascade 4 grades of GOA driving units GOAj1、GOAj2、GOAj3And GOAj4, wherein j=1,2,3 ..., J.
As shown in Fig. 2, in jth group GOA driving unit, the 1st grade of GOA driving unit GOAj1It is connected to clock signal connection
Line L1To receive clock signal CK1, the 2nd grade of driving unit GOAj2It is connected to clock signal connecting line L2To receive clock signal
CK2, 3rd level GOA driving unit GOAj3Clock signal connecting line L is connected to by a phase inverter 3a1, the 4th grade of GOA driving list
First GOAj4Clock signal connecting line L is connected to by another phase inverter 3b2, from clock signal connecting line L1It is input to phase inverter
The clock signal CK of 3a1, it is inverted device 3a and is converted to inverting clock signal XCK1It is input to 3rd level GOA driving unit GOAj3, class
As, from clock signal connecting line L2It is input to the clock signal CK of phase inverter 3b2, it is inverted device 3b and is converted to inversion clock letter
Number XCK2It is input to the 4th grade of GOA driving unit GOAj4.The initial clock signal CK provided as a result, by timing controller 21With
CK2Ultimately form CK1、CK2、XCK1And XCK24 clock signals drive each group of GOA driving unit, clock signal CK in total1、
CK2、XCK1And XCK2Timing diagram it is as shown in Figure 3.
Fig. 4 is the structural schematic diagram of every level-one GOA driving unit 1 in the present embodiment, as shown in figure 4, n-th grade of GOA driving
Unit 1 includes pull-up control module 10, pull-up module 20, grade transmission module 30, bootstrap capacitor Cb, pull-down module 40 and drop-down dimension
Hold module 50.
Wherein, the scanning drive signal G that the pull-up control module 10 is generated according to the n-th -2 grades GOA driving unitsn-2With
Grade communication STn-2Control generates grid control signal Qn.The pull-up module 20 and the grade transmission module 30 are respectively by the grid
Pole controls signal QnControl, is converted to the same level scanning drive signal G for the clock signal CK/XCK of the correspondence the same level receivednWith
Grade communication STnOutput.The bootstrap capacitor Cb is connected to the output end for pulling up control module 10 and the pull-up module
Between 20 output end, for making the pull-up module 20 stablize output the same level scanning drive signal Gn.The pull-down module 40
The scanning drive signal G generated according to the n-th+2 grades GOA driving unitsn+2It controls the grid control signal QnIt is scanned with the same level
Driving signal GnIt is pulled low to benchmark low level signal VSS.The drop-down maintenance module 50 is coupled to the grid control signal QnWith
The same level scanning drive signal GnBetween benchmark low level signal VSS, it is used for the grid control signal QnIt scans and drives with the same level
Dynamic signal GnMaintenance is pulled low to benchmark low level signal VSS.
Wherein, if n-th grade of GOA driving unit corresponds to the described 1st to i-stage GOA drive in jth group GOA driving unit
One of moving cell, then the pull-up module 20 and the grade transmission module 30 are connected to the clock signal connecting line to connect
Receive corresponding clock signal CK；If n-th grade of GOA driving unit corresponds to the i+1 in jth group GOA driving unit to m
One of grade GOA driving unit, then the pull-up module 20 and the grade transmission module 30 are connected to described phase inverter 3a, 3b
Output end to receive corresponding inverting clock signal XCK..
Specifically, as shown in figure 5, the pull-up control module 10 includes pull-up control transistor T11, the pull-up control
The source electrode of transistor T11 receives the scanning drive signal G that the n-th -2 grades GOA driving units generaten-2, the n-th -2 grades GOA of grid reception
The grade communication ST that driving unit generatesn-2, the drain electrode output grid control signal Qn。
Specifically, described to pull up transistor T21's as shown in figure 5, the pull-up module 20 includes the T21 that pulls up transistor
Grid is connected to the output end of the pull-up control module 10 to receive the grid control signal Qn, source electrode, which receives, corresponds to the same level
Clock signal CK/XCK, drain and export the same level scanning drive signal G as the output end of the pull-up module 20n。
Specifically, as shown in figure 5, the grade transmission module 30 includes that grade passes transistor T22, the grade passes transistor T22's
Grid is connected to the output end of the pull-up control module 10 to receive the grid control signal Qn, source electrode, which receives, corresponds to the same level
Clock signal CK/XCK, drain and export the same level grade communication ST as the output end of the grade transmission module 30n。
Specifically, as shown in figure 5, the bootstrap capacitor Cb is connected to the pull-up output end of control module 10 and described
Between the output end of pull-up module 20.
Specifically, as shown in figure 5, the pull-down module 40 includes the first pull-down transistor T31 and the second pull-down transistor
The source electrode of T41, the first pull-down transistor T31 are connected to the same level scanning drive signal Gn, the n-th+2 grades GOA drives of grid reception
The scanning drive signal G that moving cell generatesn+2, drain and be connected to benchmark low level signal VSS.The second pull-down transistor T41
Source electrode be connected to the grid control signal Qn, the scanning drive signal of grid reception the n-th+2 grades GOA driving units generation
Gn+2, drain and be connected to benchmark low level signal VSS.
Specifically, as shown in figure 5, the drop-down maintenance module 50 includes the first transistor T51, second transistor T52, the
Three transistor T53, the 4th transistor T54, the 5th transistor T42, the 6th transistor T32.The grid of the first transistor T51
Benchmark high level signal LC is connected and received with source electrode, and drain electrode is connect with the source electrode of the second transistor T52.Described second is brilliant
The grid of body pipe T52 is connected to the grid control signal Qn, drain and be connected to benchmark low level signal VSS.The third is brilliant
The source electrode of body pipe T53 connect with the source electrode of the first transistor T51 and receives benchmark high level signal LC, grid and described the
The drain electrode of one transistor T51 connects, and drain electrode is connect with the source electrode of the 4th transistor T54.The grid of the 4th transistor T54
Pole is connected to the grid control signal Qn, drain and be connected to benchmark low level signal VSS.The source of the 5th transistor T42
Pole is connected to the grid control signal Qn, grid connect with the drain electrode of the third transistor T53, and it is low that drain electrode is connected to benchmark
Level signal VSS.The source electrode of the 6th transistor T32 is connected to the same level scanning drive signal Gn, grid and the third are brilliant
The drain electrode of body pipe T53 connects, and drain electrode is connected to benchmark low level signal VSS.
Specifically, described phase inverter 3a, 3b are Darlington configuration phase inverter.As shown in fig. 6, phase inverter 3a, 3b packet
Include transistor T61, transistor T62, transistor T63 and transistor T64.The grid of the transistor T61 is connected and is connect with source electrode
Benchmark high level signal LC is received, drain electrode is connect with the source electrode of the transistor T62.Described in the grid of the transistor T62 is used as
The input terminal of phase inverter 3a, 3b receive the clock signal CK inputted from clock signal connecting line, and drain electrode is connected to benchmark low level
Signal VSS.The source electrode of the transistor T63 connect with the source electrode of the transistor T61 and receives benchmark high level signal LC, grid
Pole is connect with the drain electrode of the transistor T61, and drain electrode is connect with the source electrode of the transistor T64, and the transistor T63
It drains and exports inverting clock signal XCK as the output end of described phase inverter 3a, 3b.The grid of the transistor T64 receive from
The clock signal CK of clock signal connecting line input, drain electrode are connected to benchmark low level signal VSS.Refering to Fig. 6, the phase inverter
In 3a, 3b, LC is high level signal, when the clock signal CK of input terminal is high level, the clock signal XCK of output end output
For low level；When the clock signal CK of input terminal is low level, the clock signal XCK of output end output is high level.
In conclusion GOA circuit and corresponding liquid crystal display panel that as above embodiment provides, by part grade
Phase inverter is set before GOA driving unit, the initial clock signal that timing controller is provided is converted to inverting clock signal
It is input to the GOA driving unit of corresponding stage, the timing of quantity m mono- of the clock signal needed as a result, in GOA circuit can will be by
The quantity (i, i=m/2) for the initial clock signal that timing controller provides reduces half, to reduce timing controller
Design difficulty and cost.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The above is only the specific embodiment of the application, it is noted that for the ordinary skill people of the art
For member, under the premise of not departing from the application principle, several improvements and modifications can also be made, these improvements and modifications are also answered
It is considered as the protection scope of the application.
Claims (10)
1. a kind of GOA circuit, multistage GOA driving unit and clock signal connecting line including cascade setting, the clock signal
The GOA driving unit is connected to sequence controller by connecting line, which is characterized in that the GOA circuit includes i clock signal
Connecting line, the sequence controller correspond to input clock signal CK to the i clock signal connecting line1~CKi, the multistage
GOA driving unit is successively divided into several groups according to cascade sequence, and each group respectively includes m grades of GOA driving units；
Wherein, in each group of GOA driving unit, the 1st to i-stage GOA driving unit is connected to described i articles correspondingly respectively
Clock signal connecting line is to receive clock signal CK1~CKi, i+1 to m grades of GOA driving units by i phase inverter one by one
The i clock signal connecting line, the i phase inverter will be received from the i clock signal connecting line
Clock signal CK1~CKiBe converted to inverting clock signal XCK1~XCKiOutput is single to the i+1 to m grades of GOA drivings
Member；
Wherein, i is the integer more than or equal to 1, m=2i.
2. GOA circuit according to claim 1, which is characterized in that the i value is 1,2,3 or 4.
3. GOA circuit according to claim 1 or 2, which is characterized in that every level-one GOA driving unit includes pull-up control
Module, pull-up module, grade transmission module, bootstrap capacitor, pull-down module and drop-down maintenance module；Wherein, n-th grade of GOA driving is single
In member:
The scanning drive signal and the control of grade communication number that the pull-up control module is generated according to the n-th-i grades of GOA driving unit produce
Raw grid control signal；
The pull-up module and the grade transmission module are controlled by the grid control signal respectively, by the correspondence the same level received
Clock signal is converted to the same level scanning drive signal and the output of grade communication number；
The bootstrap capacitor is connected between the output end of the pull-up control module and the output end of the pull-up module, is used for
The pull-up module is set to stablize output the same level scanning drive signal；
The scanning drive signal control that the pull-down module is generated according to the n-th+i grades of GOA driving unit, which controls the grid, to be believed
Number and the same level scanning drive signal be pulled low to benchmark low level signal；
The drop-down maintenance module is coupled to the grid control signal and the same level scanning drive signal and benchmark low level signal
Between, for the grid control signal and the maintenance of the same level scanning drive signal to be pulled low to benchmark low level signal；
Wherein, if n-th grade of GOA driving unit corresponds to the described 1st one of to i-stage GOA driving unit, it is described on
Drawing-die block and the grade transmission module are connected to the clock signal connecting line to receive corresponding clock signal CK1~CKi；If n-th
Grade GOA driving unit corresponds to the i+1 one of to m grades of GOA driving units, then the pull-up module and described
It is output end to receive corresponding inverting clock signal XCK that grade transmission module, which is connected to the phase inverter,1~XCKi；
Wherein, n is the integer more than or equal to 1.
4. GOA circuit according to claim 3, which is characterized in that the pull-up control module includes pull-up control crystal
The source electrode of pipe, the pull-up control transistor receives the scanning drive signal that the n-th-i grades of GOA driving unit generates, and grid receives
The grade communication number that n-th-i grades of GOA driving unit generates, drain electrode export the grid control signal.
5. GOA circuit according to claim 3, which is characterized in that the pull-up module include pull up transistor, it is described on
The grid of pull transistor is connected to the output end of the pull-up control module, and source electrode receives the clock signal of corresponding the same level, drain electrode
Output end as the pull-up module exports the same level scanning drive signal.
6. GOA circuit according to claim 3, which is characterized in that the grade transmission module includes that grade passes transistor, the grade
The grid for passing transistor is connected to the output end of the pull-up control module, and source electrode receives the clock signal of corresponding the same level, drain electrode
Output end as the grade transmission module exports the same level grade communication number.
7. GOA circuit according to claim 3, which is characterized in that the pull-down module include the first pull-down transistor and
Second pull-down transistor, the source electrode of first pull-down transistor are connected to the same level scanning drive signal, and grid receives the n-th+i grades
The scanning drive signal that GOA driving unit generates, drain electrode are connected to benchmark low level signal；The source of second pull-down transistor
Pole is connected to the grid control signal, and grid receives the scanning drive signal that the n-th+i grades of GOA driving unit generates, and drain electrode connects
It is connected to benchmark low level signal.
8. GOA circuit according to claim 3, which is characterized in that the drop-down maintenance module includes the first transistor,
Two-transistor, third transistor, the 4th transistor, the 5th transistor, the 6th transistor；
The grid of the first transistor connects with source electrode and receives benchmark high level signal, drain electrode and the second transistor
Source electrode connection；The grid of the second transistor is connected to the grid control signal, and drain electrode is connected to benchmark low level signal；
The source electrode of the third transistor is connect with the source electrode of the first transistor, and the drain electrode of grid and the first transistor connects
It connects, drain electrode is connect with the source electrode of the 4th transistor；The grid of 4th transistor is connected to the grid control signal,
Drain electrode is connected to benchmark low level signal；The source electrode of 5th transistor is connected to the grid control signal, grid and institute
The drain electrode connection of third transistor is stated, drain electrode is connected to benchmark low level signal；The source electrode of 6th transistor is connected to this
Grade scanning drive signal, grid are connect with the drain electrode of the third transistor, and drain electrode is connected to benchmark low level signal.
9. GOA circuit according to claim 3, which is characterized in that the phase inverter is Darlington configuration phase inverter.
10. a kind of liquid crystal display panel, which is characterized in that including the GOA circuit as described in claim 1-9 is any.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811582370.5A CN109410882A (en) | 2018-12-24 | 2018-12-24 | GOA circuit and liquid crystal display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811582370.5A CN109410882A (en) | 2018-12-24 | 2018-12-24 | GOA circuit and liquid crystal display panel |
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| CN109410882A true CN109410882A (en) | 2019-03-01 |
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| CN201811582370.5A Pending CN109410882A (en) | 2018-12-24 | 2018-12-24 | GOA circuit and liquid crystal display panel |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109817177A (en) * | 2019-03-20 | 2019-05-28 | 深圳市华星光电技术有限公司 | Gate driving circuit and array substrate |
| CN110021278A (en) * | 2019-03-05 | 2019-07-16 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display panel |
| CN112233630A (en) * | 2020-10-15 | 2021-01-15 | Tcl华星光电技术有限公司 | Gate drive circuit and display panel |
| WO2021012373A1 (en) * | 2019-07-23 | 2021-01-28 | 深圳市华星光电半导体显示技术有限公司 | Goa unit, goa circuit, and display panel |
| CN112596314A (en) * | 2020-12-10 | 2021-04-02 | Tcl华星光电技术有限公司 | Display panel |
| WO2021223280A1 (en) * | 2020-05-06 | 2021-11-11 | 武汉华星光电技术有限公司 | Fingerprint identification driving circuit |
| CN114429759A (en) * | 2022-03-01 | 2022-05-03 | Tcl华星光电技术有限公司 | Display panel and display device |
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