CN106652947A - Gate drive circuit and liquid crystal display device - Google Patents

Gate drive circuit and liquid crystal display device Download PDF

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Publication number
CN106652947A
CN106652947A CN201611226451.2A CN201611226451A CN106652947A CN 106652947 A CN106652947 A CN 106652947A CN 201611226451 A CN201611226451 A CN 201611226451A CN 106652947 A CN106652947 A CN 106652947A
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CN
China
Prior art keywords
transistor
circuit
signal
grid
drop
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Application number
CN201611226451.2A
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Chinese (zh)
Inventor
廖聪维
刘翔
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深圳市华星光电技术有限公司
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Priority to CN201611226451.2A priority Critical patent/CN106652947A/en
Publication of CN106652947A publication Critical patent/CN106652947A/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3648Control of matrices with row and column drivers using an active matrix

Abstract

The invention discloses a gate drive circuit. The gate drive circuit comprises a plurality of GOA drive units in cascading arrangement, wherein the level-N GOA drive unit comprises an upwards pulling control circuit, an upwards pulling circuit, a downwards pulling circuit, a reference low-level signal, a bootstrap capacitor, as well as a first downwards pulling holding circuit and a second downwards pulling holding circuit; the GOA drive unit further comprises a bridging transistor, the grid electrode of the bridging transistor is connected with the input end of the upwards pulling control circuit, and the source electrode and the drain electrode of the bridging transistor are connected with the first downwards pulling holding circuit and the second downwards pulling holding circuit; when the input end of the upwards pulling control circuit is used for receiving high-level signals, the bridging transistor communicates the input ends of the first downwards pulling holding circuit and the second downwards pulling holding circuit and sets the low level, so that a communicating circuit between a grid electrode control signal and a reference low-level signal is controlled to be switched off, wherein N is an positive integer. The invention further discloses a liquid crystal display device which comprises the gate drive circuit.

Description

Gate driver circuit and liquid crystal indicator

Technical field

The present invention relates to display technology field, more particularly to a kind of gate driver circuit, further relate to comprising as above grid The liquid crystal indicator of drive circuit.

Background technology

In active liquid crystal indicator, each pixel has a thin film transistor (TFT) (TFT), its grid (Gate) connection To horizontal scanning line, drain electrode (Drain) is connected to the data wire of vertical direction, and source electrode (Source) is then connected to pixel electrode. Apply enough voltage on horizontal scanning line, all TFT on the line can be caused to open, now on the horizontal scanning line Pixel electrode can be connected with the data wire of vertical direction, so as to by the display signal voltage writing pixel on data wire, control is not The effect of control color is further reached with the light transmittance of liquid crystal.The driving master of current active display panels horizontal scanning line To be completed by the external IC of panel, external IC can control the charging and discharging step by step of horizontal scanning lines at different levels.And GOA skills Art, i.e. Gate Driver on Array (driving of array base palte row) technology, can use original processing procedure of display panels The drive circuit of horizontal scanning line is produced on the substrate around viewing area, makes it to substitute external IC to complete horizontal sweep The driving of line.GOA technologies can reduce binding (bonding) operation of external IC, have an opportunity to lift production capacity and reduce product cost, And display panels can be made to be more suitable for making the display product of narrow frame or Rimless.

Existing GOA gate driver circuits, generally include the multiple GOA units for cascading, and drive per one-level GOA unit correspondence Primary plateaus scan line.The primary structure of GOA unit includes pull-up circuit (Pull-up part), pull-up control circuit (Pull- Up control part), transfer circuit (Transfer Part), pull-down circuit (Key Pull-down Part) and drop-down dimension Hold circuit (Pull-down Holding Part), and bootstrapping (Boast) electric capacity of responsible current potential lifting.Pull-up circuit is main It is responsible for for clock signal (Clock) being output as grid (Gate) signal;Pull-up control circuit is responsible for controlling the opening of pull-up circuit Time, transmission signal or Gate signals that general connection earlier stages GOA circuit is passed over;Pull-down circuit is responsible at first Between Gate is closed down for electronegative potential, that is, Gate signals;Drop-down holding circuit is then responsible for Gate output signals and pull-up electricity The Gate signals (commonly referred to Q points) on road maintain (Holding) in off position (i.e. low level current potential), generally have two it is drop-down Maintenance module alternating action;Bootstrap capacitor (C boast) is then responsible for the secondary lifting of Q points, is so conducive to pull-up circuit Gate signal outputs.

In existing GOA gate driver circuits, when Q point voltages rise to high level, drop-down holding circuit cut-out Q points with The connecting path of electronegative potential point.Because the cut-out action of drop-down holding circuit is controlled by Q point voltages, the cut-out of drop-down holding circuit The rising of Q point voltages is lagged behind, Q point voltages can not in time cut off the connecting path of Q points and electronegative potential point, cause during rising There is electric leakage in Q point voltages, and the rise time of Q point voltages is excessive, and this may result in the deterioration of GOA unit partial properties, when serious very The output that can extremely cause GOA unit decays step by step, until GOA gate driver circuits are entirely ineffective.

The content of the invention

In view of this, the invention provides a kind of gate driver circuit, the cut-out action of drop-down holding circuit is done sth. in advance in Q The process that point voltage rises, reduces charge leakage of the Q points in voltage bootstrap process, shortens the rise time of Q point voltages, improves The driving force and driving stability of GOA gate driver circuits.

To achieve these goals, present invention employs following technical scheme:

A kind of gate driver circuit, including multiple GOA driver elements that cascade is arranged, wherein, N level GOA driver elements Including pull-up control circuit, pull-up circuit, pull-down circuit, benchmark low level signal, bootstrap capacitor and the first drop-down maintenance electricity Road and the second drop-down holding circuit;The GOA driver elements also include a bridge joint transistor, and the grid of the bridge joint transistor connects The input of the pull-up control circuit is connected to, two-stage transmission signal before receiving, source electrode and the drain electrode point of the bridge joint transistor Do not connect the described first drop-down holding circuit and the second drop-down holding circuit;The input of the pull-up control circuit receives high electricity During ordinary mail, the bridge joint transistor mutually interconnects the input of the described first drop-down holding circuit and the second drop-down holding circuit Lead to and be set to low level, to control to cut off low with benchmark by the grid control signal of the output end generation of the pull-up control circuit Communication line between level signal;Wherein, N is positive integer.

Specifically, the pull-up control circuit transmits signal control and produces grid control signal according to front two-stage;On described Puller circuit is controlled by the grid control signal, and the scan clock signal for receiving is converted into scanning drive signal output;Institute State pull-down circuit and the grid control signal and the scanning drive signal are pulled low to by institute according to the transmission signal control of rear two-stage State benchmark low level signal;The bootstrap capacitor is connected to the defeated of the output end of the pull-up control circuit and the pull-up circuit Go out between end;The first drop-down holding circuit and the second drop-down holding circuit are when the scanning drive signal is in non-driven Between when, alternately the grid control signal and the scanning drive signal are communicated into the benchmark low level signal.

Preferably, the described first drop-down holding circuit and the second drop-down holding circuit have identical circuit structure, described First drop-down holding circuit and the second drop-down holding circuit include respectively the first transistor, transistor seconds, third transistor, the Four transistors, the 5th transistor, the 6th transistor;The grid and source electrode of the first transistor connects and receives pulling down clock letter Number, drain electrode is connected with the source electrode of the transistor seconds;The grid of the transistor seconds is connected to the grid control signal, Drain electrode is connected to the benchmark low level signal;The source electrode of the third transistor is connected with the source electrode of the first transistor, Grid is connected with the drain electrode of the first transistor, and drain electrode is connected with the source electrode of the 4th transistor;4th transistor Grid be connected to the grid control signal, drain electrode is connected to the benchmark low level signal;The source of the 5th transistor Pole is connected to the grid control signal, and grid is connected with the drain electrode of the third transistor, and it is low that drain electrode is connected to the benchmark Level signal;The source electrode of the 6th transistor is connected to the scanning drive signal, the leakage of grid and the third transistor Pole connects, and drain electrode is connected to the benchmark low level signal;Wherein, the source electrode of the bridge joint transistor and drain electrode connects respectively institute State the drain electrode of the third transistor of the first drop-down holding circuit and the second drop-down holding circuit;Wherein, the described first drop-down maintenance The height of the second pulling down clock signal that the first pulling down clock signal that circuit is received is received with the described second drop-down holding circuit Level logic is contrary.

Preferably, the described first drop-down holding circuit and the second drop-down holding circuit have identical circuit structure, described First drop-down holding circuit and the second drop-down holding circuit include respectively the first transistor, transistor seconds, third transistor, the Four transistors, the 5th transistor, the 6th transistor;The grid and source electrode of the first transistor connects and receives pulling down clock letter Number, drain electrode is connected with the source electrode of the transistor seconds;The grid of the transistor seconds is connected to the grid control signal, Drain electrode is connected to the benchmark low level signal;The source electrode of the third transistor is connected with the source electrode of the first transistor, Grid is connected with the drain electrode of the first transistor, and drain electrode is connected with the source electrode of the 4th transistor;4th transistor Grid be connected to the grid control signal, drain electrode is connected to the benchmark low level signal;The source of the 5th transistor Pole is connected to the grid control signal, and grid is connected with the drain electrode of the third transistor, and it is low that drain electrode is connected to the benchmark Level signal;The source electrode of the 6th transistor is connected to the scanning drive signal, the leakage of grid and the third transistor Pole connects, and drain electrode is connected to the benchmark low level signal;Wherein, the source electrode of the bridge joint transistor and drain electrode connects respectively institute State the drain electrode of the first transistor of the first drop-down holding circuit and the second drop-down holding circuit;Wherein, the described first drop-down maintenance The height of the second pulling down clock signal that the first pulling down clock signal that circuit is received is received with the described second drop-down holding circuit Level logic is contrary.

Preferably, the pull-up control circuit include pull-up controlling transistor, the grid of the pull-up controlling transistor and Source electrode is connected with each other and receives front two-stage transmission signal, the drain electrode output grid control signal.

Preferably, the pull-up circuit includes pulling up transistor, and the grid for pulling up transistor is connected to the grid Control signal, source electrode is connected to the scan clock signal, the drain electrode output scanning drive signal.

Preferably, the pull-down circuit includes the first pull-down transistor and the second pull-down transistor, first time crystal pulling The source electrode of body pipe is connected to the scanning drive signal, and grid is connected to rear two-stage transmission signal, and drain electrode is connected to the benchmark Low level signal;The source electrode of second pull-down transistor is connected to the grid control signal, and grid is connected to rear two-stage and passes Delivery signal, drain electrode is connected to the benchmark low level signal.

Preferably, the GOA driver elements also include transfer circuit, and the transfer circuit is by the grid control signal control System, by the scan clock signal for receiving this grade of transmission signal output is converted to.

Preferably, the transfer circuit includes transmission transistor, and the grid of the transmission transistor is connected to the grid Control signal, source electrode is connected to the scan clock signal, and drain electrode described level of output transmits signal.

Present invention also offers a kind of liquid crystal indicator, it includes gate driver circuit as above.

The gate driver circuit provided in the embodiment of the present invention, in the first drop-down holding circuit and the second drop-down holding circuit Between be connected to bridge joint transistor, and bridge the grid of transistor and controlled by the input signal of pull-up control circuit.Work as pull-up When control circuit receives input signal causes Q point voltages to rise to high level therewith for high level, bridge joint transistor is also by upper The input signal control conducting of control circuit is drawn, the input of the first drop-down holding circuit and the second drop-down holding circuit is mutual Low level is connected and is set to, with the connecting path for controlling to cut off Q points and electronegative potential point.That is, the cut-out of drop-down holding circuit is moved Make to do sth. in advance (at least do not lag behind the process of Q point voltages rising), reduce charge leakage of the Q points in voltage bootstrap process, contract The short rise time of Q point voltages, improve the driving force of GOA gate driver circuits and drive stability.

Description of the drawings

Fig. 1 is the circuit diagram of gate driver circuit provided in an embodiment of the present invention;

Fig. 2 is the oscillogram of the grid control signal in the embodiment of the present invention and scanning drive signal, be also show in figure The corresponding waveform of prior art is contrasted;

Fig. 3 is the circuit diagram of the gate driver circuit that another embodiment of the present invention is provided;

Fig. 4 is the structural representation of liquid crystal indicator provided in an embodiment of the present invention.

Specific embodiment

To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with the accompanying drawings to the concrete reality of the present invention The mode of applying is described in detail.The example of these preferred embodiments is illustrated in the accompanying drawings.Shown in accompanying drawing and according to What the embodiments of the present invention of Description of Drawings were merely exemplary, and the present invention is not limited to these embodiments.

Here, also, it should be noted that in order to avoid having obscured the present invention because of unnecessary details, in the accompanying drawings only The structure and/or process step closely related with scheme of the invention is shown, and is eliminated little with relation of the present invention Other details.

A kind of gate driver circuit, including multiple GOA driver elements that cascade is arranged are present embodiments provided, according to N The control of level GOA driver elements provides scanning drive signal G to viewing area N levels horizontal scanning lineN.As shown in figure 1, N levels GOA driver elements include pull-up control circuit 10, pull-up circuit 20, pull-down circuit 30, benchmark low level signal VSS, bootstrapping electricity Hold CB and the first drop-down holding circuit 40 and the second drop-down holding circuit 50;The GOA driver elements also include that a bridge joint is brilliant Body pipe T7.

Wherein, the pull-up control circuit 10 transmits signal ST according to front two-stageN-2Control produces grid control signal QN。 The pull-up circuit 20 is by the grid control signal QNControl, by the scan clock signal CK for receiving turntable driving is converted to Signal GNOutput.The pull-down circuit 30 transmits signal ST according to rear two-stageN+2Control the grid control signal QNWith it is described Scanning drive signal GNIt is pulled low to the benchmark low level signal VSS.The bootstrap capacitor CB is connected to the pull-up control electricity Between the output end of the output end on road 10 and the pull-up circuit 20.The drop-down maintenance of the first drop-down holding circuit 40 and second Circuit 50 is in scanning drive signal GNIn the non-driven time when, alternately by the grid control signal QNSweep with described Retouch drive signal GNIt is communicated to the benchmark low level signal VSS;Wherein, N is positive integer.

Wherein, the grid of the bridge joint transistor T7 is connected to the input of the pull-up control circuit 10, receives front two Level transmission signal STN-2, the source electrode of the bridge joint transistor T7 and drain electrode connect respectively the described first drop-down holding circuit 40 and the Two drop-down holding circuits 50.When the input of the pull-up control circuit 10 receives high level signal, the bridge joint transistor T7 The input of the described first drop-down holding circuit 40 and the second drop-down holding circuit 50 is interconnected and low level is set to, to control The grid control signal Q that system cut-out is produced by the output end of the pull-up control circuit 10NBetween benchmark low level signal VSS Communication line.

Wherein, as shown in figure 1, the GOA driver elements 1 also include transfer circuit 60, the transfer circuit 60 is by described Grid control signal QNControl, by the scan clock signal CK for receiving this grade of transmission signal ST is converted toNOutput.

Gate driver circuit as provided above, connects between the first drop-down holding circuit and the second drop-down holding circuit Bridge joint transistor, and bridge the grid of transistor and controlled by the input signal of pull-up control circuit.Work as pull-up control circuit When receives input signal causes Q point voltages to rise to high level therewith for high level, bridge joint transistor is also by pull-up control electricity The input signal control conducting on road, the input of the first drop-down holding circuit and the second drop-down holding circuit is interconnected juxtaposition For low level, with the connecting path for controlling to cut off Q points and electronegative potential point.That is, the cut-out action of drop-down holding circuit is done sth. in advance (extremely Few process for not lagging behind the rising of Q point voltages), charge leakage of the Q points in voltage bootstrap process is reduced, shorten Q points electricity The rise time of pressure, improve the driving force of GOA gate driver circuits and drive stability.

Specifically, pull-up control unit 10 transmits signal ST in the front two-stage that upper level driver element is producedN-2Effect Under, generate grid control signal QN.Grid control signal QNIt is responsible for the correct work schedule of whole GOA driver elements.When row scanning When proceeding to N levels, QNFor high level, can be used to open output scanning drive signal G of pull-up unit 20N.When N levels are in non- During row scanning mode, need to ensure QNFor reliable low level, pull-up unit 20 is set not export (i.e. GNFor low level).Therefore, exist In the design of GOA driver elements and drive circuit, it is necessary to assure QNSequential it is correct.In the present embodiment, as shown in figure 1, The pull-up control circuit 10 includes pull-up controlling transistor T11, and the grid and source electrode of pull-up controlling transistor T11 is mutual Connect and receive front two-stage transmission signal STN-2, the drain electrode output grid control signal QN

Specifically, pull-up unit 20 is mainly responsible for that scan clock signal CK is output as scanning drive signal G of gridN。 In the present embodiment, as shown in figure 1, the pull-up circuit 20 includes the T21 that pulls up transistor, the grid of the T21 that pulls up transistor Pole is connected to the grid control signal Q as the control signal input of pull-up unit 20N, when source electrode is connected to the scanning Clock signal CK, drain electrode output scanning drive signal GN, it is connected to the scan line (not shown) of correspondence row.

Specifically, drop-down unit 30 is in the very first time, by the drain potential of the T21 that pulls up transistor, (i.e. turntable driving to be believed Number GN) and grid potential (i.e. grid control signal QN) down for electronegative potential, that is, close scanning drive signal GN.In the present embodiment, As shown in figure 1, the pull-down circuit 30 includes the first pull-down transistor T31 and the second pull-down transistor T41.Wherein, described The source electrode of one pull-down transistor T31 is connected to scanning drive signal GN, grid is connected to rear two-stage transmission signal STN+2, leakage Pole is connected to the benchmark low level signal VSS;When after two-stage transmission signal STN+2For high level, the first pull-down transistor T31 By scanning drive signal GNBenchmark low level signal VSS is pulled low to, scanning drive signal G of this grade is closedN.Described second is drop-down The source electrode of transistor T41 is connected to the grid control signal QN, grid is connected to rear two-stage transmission signal STN+2, drain electrode connection To the benchmark low level signal VSS;When after two-stage transmission signal STN+2For high level, the second pull-down transistor T41 is by grid Control signal QNBenchmark low level signal VSS is pulled low to, grid control signal Q is closedN

Specifically, as shown in figure 1, the transfer circuit 60 includes transmission transistor T22, the transmission transistor T22's Grid is connected to the grid control signal QN, source electrode is connected to the scan clock signal CK, and drain electrode described level of output is passed Delivery signal STN.This level transmits signal STNFor the pull-up control unit of two-stage after control, by by the control pull-up control of transmission signal Unit processed, it is to avoid using scanning drive signal GNTo control This move so that scanning drive signal GNIt is more stable.

Further, as shown in figure 1, the bootstrap capacitor CB is connected to the output end of the pull-up control circuit 10 and institute State between the output end of pull-up circuit 20, i.e. the two ends of bootstrap capacitor CB connect respectively grid control signal QNAnd turntable driving Signal GN, the effect of the bootstrap capacitor CB is in QNFor high level when, storage pulls up transistor the voltage of T21 grid sources, works as GN Output high level line scan signals after, bootstrap capacitor can with secondary lifting pull up transistor T21 grid current potential, with ensure The T21 that pulls up transistor reliably is opened and output scanning drive signal GN.Complete scanning drive signal G of this gradeN, GNFor low Level, and maintain this low level always when other rows are scanned.

When after two-stage transmission signal STN+2After returning to low level, it is impossible to maintain QNAnd GNLow level, therefore, GOA drive In moving cell, using drop-down maintenance unit by QNAnd GNMaintain (Holding) in off position (low level state).The present embodiment In, drop-down maintenance unit includes the first drop-down holding circuit 40 and the second drop-down holding circuit 50, in the scanning drive signal GNIn the non-driven time when, the first drop-down holding circuit 40 and the second drop-down holding circuit 50 alternately control the grid Signal QNWith scanning drive signal GNThe benchmark low level signal VSS is communicated to, by QNAnd GNMaintain in off position.

Specifically, as shown in figure 1, the drop-down holding circuit 50 of the first drop-down holding circuit 40 and second has identical Circuit structure, the drop-down holding circuit 50 of the first drop-down holding circuit 40 and second respectively include the first transistor T51, T61, Transistor seconds T52, T62, third transistor T53, T63, the 4th transistor T54, T64, the 5th transistor T42, T43, the 6th Transistor T32, T33.Wherein, the grid and source electrode of described the first transistor T51, T61 connects and receives pulling down clock signal LC1, LC2, drain electrode is connected with the source electrode of described transistor seconds T52, T62;The grid connection of described transistor seconds T52, T62 To the grid control signal QN, drain and be connected to the benchmark low level signal VSS;Third transistor T53, T63 Source electrode is connected with the source electrode of described the first transistor T51, T61, and grid is connected with the drain electrode of described the first transistor T51, T61, Drain electrode is connected with the source electrode of described 4th transistor T54, T64;The grid of described 4th transistor T54, T64 is connected to the grid Pole control signal QN, drain and be connected to the benchmark low level signal VSS;The source electrode connection of described 5th transistor T42, T43 To the grid control signal QN, grid is connected with the drain electrode of third transistor T53, T63, and drain electrode is connected to the benchmark Low level signal VSS;The source electrode of described 6th transistor T32, T33 is connected to scanning drive signal GN, grid with it is described The drain electrode connection of third transistor T53, T63, drain electrode is connected to the benchmark low level signal VSS.Wherein, the bridge joint crystal The source electrode of pipe T7 and drain electrode connect respectively the 3rd crystal of the described first drop-down holding circuit 40 and the second drop-down holding circuit 50 The drain electrode of pipe T53, T63.Wherein, the first pulling down clock signal LC1 that the described first drop-down holding circuit 40 is received and described the The low and high level logic of the second pulling down clock signal LC2 that two drop-down holding circuit 50 is received is contrary, i.e. when LC1 is high level, Then LC2 is low level;Conversely, when LC1 is low level, then LC2 is high level.

Refering to Fig. 1 the first drop-down holding circuits 40 as above and the second drop-down holding circuit 50, its course of work is as follows:

1), in Q point voltages (grid control signal QN) ascent stage:When due to LC1 and LC2 being the low frequency of two complementations Clock signal, therefore when LC1 is high level, LC2 is low level;Conversely, when LC1 is low level, LC2 is high level.Currently Two-stage transmits signal STN-2For high level, transistor T7 conductings, in the presence of T7, you can to move P points to low electricity by K points Position;Or conversely, electronegative potential to is moved K points by P points.When K points and P points are electronegative potential, between control Q points and low level point 5th transistor T42, T43 cut-offs of communication line, i.e. grid control signal QNWith the company between benchmark low level signal VSS Logical circuit.Because the level conversion of K points and P points transmits signal ST by front two-stageN-2Control, front two-stage transmits signal STN-2Speed Degree is switched to the low level conversion stage far faster than Q point voltage liftings, P points or K point voltages from high level, and needs not wait for Q points current potential rises, and just moves P points or K points to low level voltage VSS by transistor T54, T64.Therefore, then P points or K points can pulled down to low level current potential prior to the lifting of Q point voltages, avoiding problems P points or K points voltage it is drop-down with Q point voltages are lifted to race hazard, reduce charge leakage of the Q points in voltage bootstrap process.

Oscillogram as shown in Figure 2, shows Q in figureNAnd GNContrast oscillogram, solid line is represented according to the present invention in figure The Q that the drive circuit that embodiment is provided is obtainedNAnd GNWaveform, dotted line represent according to prior art drive circuit obtain QN And GNWaveform.Figure it is seen that QNAnd GNRise time all obtain larger shortening, and obtain higher peak value electricity Pressure, it is ensured that QNAnd GNCorrect sequential, improve GOA gate driver circuits driving force and drive stability.

2), in the low level maintenance stage:STN-2For low level current potential, then T7 closings.So P points or K points are wherein One of be high level voltage, by low level holding circuit, QNAnd GNIt is coupled to low level voltage VSS.Therefore, T7 transistors Introducing can't disturb the work of low level maintenance stage.

It should be noted that above K point and P points refer to the grid tie point of the 4th transistor T54, T64.

In another preferred embodiment, as shown in figure 3, the source electrode of the bridge joint transistor T7 and drain electrode also may be used respectively To connect the drain electrode of the first transistor T51, T61 of the drop-down holding circuit 50 of the first drop-down holding circuit 40 and second.By It is pulled low by T7 in node M and N, this can just turn off T53 and person T63, then node P and K can be pulled to more quickly Low level.The structure and operation principle of remainder circuit with it is similar in the present embodiment, repeat no more here.

The present embodiment additionally provides a kind of liquid crystal indicator, as shown in figure 4, the liquid crystal indicator includes viewing area Domain 2 and the gate driver circuit 1 being integrally disposed on the edge of viewing area 2, the gate driver circuit 1 employs as above real Apply the gate driver circuit that example is provided.

In sum, example is performed as described above answer gate driver circuit is provided, it can move the cut-out of drop-down holding circuit Make the process for rising in Q point voltages ahead of time, reduce charge leakage of the Q points in voltage bootstrap process, shorten the rising of Q point voltages Time, improve the driving force of GOA gate driver circuits and drive stability.

It should be noted that herein, such as first and second or the like relational terms are used merely to a reality Body or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or deposit between operating In any this actual relation or order.And, term " including ", "comprising" or its any other variant are intended to Nonexcludability is included, so that a series of process, method, article or equipment including key elements not only will including those Element, but also including other key elements being not expressly set out, or also include for this process, method, article or equipment Intrinsic key element.In the absence of more restrictions, the key element for being limited by sentence "including a ...", it is not excluded that Also there is other identical element in process, method, article or equipment including the key element.

The above is only the specific embodiment of the application, it is noted that for the ordinary skill people of the art For member, on the premise of without departing from the application principle, some improvements and modifications can also be made, these improvements and modifications also should It is considered as the protection domain of the application.

Claims (10)

1. a kind of gate driver circuit, including multiple GOA driver elements that cascade is arranged, it is characterised in that N levels GOA drive Unit includes pull-up control circuit (10), pull-up circuit (20), pull-down circuit (30), benchmark low level signal (VSS), bootstrapping electricity Hold (CB) and the first drop-down holding circuit (40) and the second drop-down holding circuit (50);The GOA driver elements also include one Bridge joint transistor (T7), the grid of bridge joint transistor (T7) is connected to the input of the pull-up control circuit (10), connects Two-stage transmission signal (ST before receivingN-2), source electrode and the drain electrode of bridge joint transistor (T7) connect respectively the described first drop-down maintenance Circuit (40) and the second drop-down holding circuit (50);When the input of the pull-up control circuit (10) receives high level signal, The transistor (T7) that bridges is by the described first drop-down holding circuit (40) and the input phase of the second drop-down holding circuit (50) It is intercommunicated and be set to low level, to control to cut off the grid control signal produced by the output end of the pull-up control circuit (10) (QN) and the communication line between benchmark low level signal (VSS);
Wherein, N is positive integer.
2. gate driver circuit according to claim 1, it is characterised in that the pull-up control circuit (10) is according to front two Level transmission signal (STN-2) control generation grid control signal (QN);The pull-up circuit (20) is by the grid control signal (QN) control, the scan clock signal for receiving (CK) is converted into scanning drive signal (GN) output;The pull-down circuit (30) Signal (ST is transmitted according to rear two-stageN+2) control the grid control signal (QN) and the scanning drive signal (GN) be pulled low to The benchmark low level signal (VSS);The bootstrap capacitor (CB) be connected to the pull-up control circuit (10) output end and Between the output end of the pull-up circuit (20);The first drop-down holding circuit (40) and the second drop-down holding circuit (50) exist Scanning drive signal (the GN) in the non-driven time when, alternately by the grid control signal (QN) and the scanning drive Dynamic signal (GN) it is communicated to the benchmark low level signal (VSS).
3. gate driver circuit according to claim 2, it is characterised in that the first drop-down holding circuit (40) and Two drop-down holding circuits (50) are with identical circuit structure, the first drop-down holding circuit (40) and the second drop-down maintenance electricity Road (50) include respectively the first transistor (T51, T61), transistor seconds (T52, T62), third transistor (T53, T63), the Four transistors (T54, T64), the 5th transistor (T42, T43), the 6th transistor (T32, T33);The first transistor (T51, T61 grid and source electrode) connects and receives pulling down clock signal (LC1, LC2), drains and the transistor seconds (T52, T62) Source electrode connection;The grid of the transistor seconds (T52, T62) is connected to the grid control signal (QN), drain electrode is connected to The benchmark low level signal (VSS);The source electrode of the third transistor (T53, T63) and the first transistor (T51, T61 source electrode connection), grid is connected with the drain electrode of the first transistor (T51, T61), drains and the 4th transistor The source electrode connection of (T54, T64);The grid of the 4th transistor (T54, T64) is connected to the grid control signal (QN), Drain electrode is connected to the benchmark low level signal (VSS);The source electrode of the 5th transistor (T42, T43) is connected to the grid Control signal (QN), grid is connected with the drain electrode of the third transistor (T53, T63), and drain electrode is connected to the benchmark low level Signal (VSS);The source electrode of the 6th transistor (T32, T33) is connected to the scanning drive signal (GN), grid with it is described The drain electrode connection of third transistor (T53, T63), drain electrode is connected to the benchmark low level signal (VSS);
Wherein, the source electrode of bridge joint transistor (T7) and drain electrode connects respectively the described first drop-down holding circuit (40) and second The drain electrode of the third transistor (T53, T63) of drop-down holding circuit (50);
Wherein, the described first drop-down holding circuit (40) receives the first pulling down clock signal (LC1) and the described second drop-down dimension The low and high level logic for holding the second pulling down clock signal (LC2) of circuit (50) reception is contrary.
4. gate driver circuit according to claim 2, it is characterised in that the first drop-down holding circuit (40) and Two drop-down holding circuits (50) are with identical circuit structure, the first drop-down holding circuit (40) and the second drop-down maintenance electricity Road (50) include respectively the first transistor (T51, T61), transistor seconds (T52, T62), third transistor (T53, T63), the Four transistors (T54, T64), the 5th transistor (T42, T43), the 6th transistor (T32, T33);The first transistor (T51, T61 grid and source electrode) connects and receives pulling down clock signal (LC1, LC2), drains and the transistor seconds (T52, T62) Source electrode connection;The grid of the transistor seconds (T52, T62) is connected to the grid control signal (QN), drain electrode is connected to The benchmark low level signal (VSS);The source electrode of the third transistor (T53, T63) and the first transistor (T51, T61 source electrode connection), grid is connected with the drain electrode of the first transistor (T51, T61), drains and the 4th transistor The source electrode connection of (T54, T64);The grid of the 4th transistor (T54, T64) is connected to the grid control signal (QN), Drain electrode is connected to the benchmark low level signal (VSS);The source electrode of the 5th transistor (T42, T43) is connected to the grid Control signal (QN), grid is connected with the drain electrode of the third transistor (T53, T63), and drain electrode is connected to the benchmark low level Signal (VSS);The source electrode of the 6th transistor (T32, T33) is connected to the scanning drive signal (GN), grid with it is described The drain electrode connection of third transistor (T53, T63), drain electrode is connected to the benchmark low level signal (VSS);
Wherein, the source electrode of bridge joint transistor (T7) and drain electrode connects respectively the described first drop-down holding circuit (40) and second The drain electrode of the first transistor (T51, T61) of drop-down holding circuit (50);
Wherein, the described first drop-down holding circuit (40) receives the first pulling down clock signal (LC1) and the described second drop-down dimension The low and high level logic for holding the second pulling down clock signal (LC2) of circuit (50) reception is contrary.
5. gate driver circuit according to claim 2, it is characterised in that the pull-up control circuit (10) is including pull-up Controlling transistor (T11), the grid and source electrode of pull-up controlling transistor (T11) are connected with each other and receive front two-stage transmission letter Number (STN-2), the drain electrode output grid control signal (QN)。
6. gate driver circuit according to claim 2, it is characterised in that the pull-up circuit (20) is including upper crystal pulling Pipe (T21), the grid for pulling up transistor (T21) is connected to the grid control signal (QN), source electrode is connected to described sweeping Retouch clock signal (CK), the drain electrode output scanning drive signal (GN)。
7. gate driver circuit according to claim 2, it is characterised in that the pull-down circuit (30) is drop-down including first Transistor (T31) and the second pull-down transistor (T41), the source electrode of first pull-down transistor (T31) is connected to the scanning Drive signal (GN), grid is connected to rear two-stage transmission signal (STN+2), drain electrode is connected to the benchmark low level signal (VSS);The source electrode of second pull-down transistor (T41) is connected to the grid control signal (QN), grid is connected to rear two Level transmission signal (STN+2), drain electrode is connected to the benchmark low level signal (VSS).
8. according to the arbitrary described gate driver circuit of claim 1-7, it is characterised in that the GOA driver elements also include Transfer circuit (60), the transfer circuit (60) is by the grid control signal (QN) control, by the scan clock for receiving letter Number (CK) is converted to this grade of transmission signal (STN) output.
9. gate driver circuit according to claim 8, it is characterised in that the transfer circuit (60) includes transmission crystal Pipe (T22), the grid of the transmission transistor (T22) is connected to the grid control signal (QN), source electrode is connected to described sweeping Clock signal (CK) is retouched, drain electrode described level of output transmits signal (STN)。
10. a kind of liquid crystal indicator, it is characterised in that include the gate driver circuit as described in claim 1-9 is arbitrary.
CN201611226451.2A 2016-12-27 2016-12-27 Gate drive circuit and liquid crystal display device CN106652947A (en)

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Application publication date: 20170510