GB2614817A - Test circuit of display panel and display device - Google Patents

Abstract

A test circuit (100) of a display panel (10) and a display device (200); a first active switch (130) controls the connection and disconnection of a test signal line (113), a low level signal test line, and a high level signal test line; the high level signal test line is also connected to a control end of each first active switch (130); when a protection circuit (140) operates normally on the display panel (10), receiving a low-level signal output control signal on a low level signal line controlling a first active switch (130) to disconnect.

Description

TEST CIRCUIT OF DISPLAY PANEL AND DISPLAY DEVICE

[0001] This application claims the priority and benefit of Chinese patent application CN2021111949316, titled "Test Circuit of Display Panel and Display Device" and filed October 14, 2021 with China National Intellectual Property Administration, the entire contents of which are incorporated herein by reference

TECHNICAL FIELD

[0002] This present application relates to the field of display technology, and more particularly relates to a test circuit of a display panel and a display device.

BACKGROUND

[0003] The description provided in this section is intended for the mere purpose of providing background information related to the present application but doesn't necessarily constitute prior art.

[0004] Flat-panel displays are currently the mainstream displays. Among them, liquid crystal displays are widely used in electronic products such as computer screens, flat-screen TVs, and mobile phones because of their thin and light appearance and power-saving advantages. A liquid crystal display includes a liquid crystal display panel, a backlight module, an optical film, a sealant frame, and a conductive adhesive tape disposed on a side of the display panel.

[0005] A liquid crystal display panel may include a display region and a non-display region around the display region. Multiple test traces are disposed in the non-display region. In order to test the circuit conduction of each liquid crystal display panel on the large display motherboard, the test pads of all the liquid crystal display panels on the large display motherboard may be connected together by test traces for testing purposes. But after cutting the large display motherboard, the test traces will be exposed to the air from the side of the LCD panel. During normal display, however, since the internal circuits are directly or indirectly connected to the test traces, the exposed test traces are electrically charged and may contact an external ground terminal to cause a short circuit problem, thereby affecting the display effect of the display panel

SUMMARY

100061 It is therefore one purpose of the present application to provide a test trace of a display panel and a display device, so as to address the short circuit problem of the test traces.

100071 This application discloses a test circuit for a display panel. The display panel includes a high-level signal trace and a low-level signal trace, which are a driving circuit of the display panel. The test circuit includes a plurality of test traces, a plurality of first active switches and a protection circuit. The plurality of test traces including a high-level signal test trace, a low-level signal test trace, and at least one test signal trace. The plurality of first active switches are disposed in one-to-one correspondence with the test traces. The first active switches control the turn-on and turn-off of the test signal trace, the low-level signal test trace and the high-level signal test trace. The low-level signal trace is connected to the low-level signal test trace through one of the first active switches. The high-level signal trace is connected to the high-level signal test trace through another first active switch. The high-level signal test trace is also connected to the control terminal of each of the first active switches. The protection circuit includes a control signal input terminal and a control signal output terminal. The control signal input terminal is connected to both the high-level signal trace and the low-level signal trace. The control signal output terminal is connected to the control terminal of each of the first active switches. When the display panel is operating normally, the protection circuit receives the low-level signal from the low-level signal trace and outputs the control signal to control the first active switches to be turned off.

[00081 The present application further discloses a display device, including a conductive tape and a display panel, where the conductive tape covers exposed positions of a plurality of test traces. The display panel includes a high-level signal trace and a low-level signal trace, which are connected to a driving circuit of the display panel. The test circuit includes a plurality of test traces, a plurality of first active switches and a protection circuit. The plurality of test traces including a high-level signal test trace, a low-level signal test trace, and at least one test signal trace. The plurality of first active switches are disposed in one-to-one correspondence with the test traces. The first active switches control the turn-on and turn-off of the test signal trace, the low-level signal test trace and the high-level signal test trace. The low-level signal trace is connected to the low-level signal test trace through one of the first active switches. The high-level signal trace is connected to the high-level signal test trace through another first active switch. The high-level signal test trace is also connected to the control terminal of each of the first active switches. The protection circuit includes a control signal input terminal and a control signal output terminal. The control signal input terminal is connected to both the high-level signal trace and the low-level signal trace. The control signal output terminal is connected to the control terminal of each of the first active switches. When the display panel is operating normally, the protection circuit receives the low-level signal from the low-level signal trace and outputs the control signal to control the first active switches to be turned off.

[0009] In this application, the protection circuit is connected to both the high-level signal trace and the low-level signal trace. During the test stage of the display panel, the conduction of the test traces is controlled by the high-level signal on the high-level signal test trace. During the display stage of the display panel, the protection circuit is used to control the test traces 110 to be turned off. Thus, while the testing is not affected during the test stage, during the display stage of the display panel, the test traces no longer carry charges near the exposed end by virtue of the protection circuit 140 and the first active switches, thus preventing problems such as short circuit and ESD (Electro-Static discharge) at the exposed positions of the test traces.

BRIEF DESCRIPTION OF DRAWINGS

[0010] The accompanying drawings are used to provide a further understanding of the embodiments according to the present application, and constitute a part of the specification. They are used to illustrate the embodiments according to the present application, and explain the principle of the present application in conjunction with the text description. Apparently, the drawings in the following description merely represent some embodiments of the present disclosure, and for those having ordinary skill in the art, other drawings may also be obtained based on these drawings without investing creative efforts. A brief description of the accompanying drawings is provided as follows.

10011] FIG. 1 is a schematic diagram of a display motherboard according to a first embodiment of the present application.

100121 FIG. 2 is a schematic diagram of a test circuit of a display panel according to the first embodiment of the present application.

[0013] FIG. 3 is a schematic diagram of a test circuit of a display panel according to a second embodiment of the present application [0014] FIG. 4 is a schematic diagram of a display device according to a third embodiment of the present application.

DETAILED DESCRIPTION OF EMBODIMENTS

[0015] It should be understood that the terms used herein, the specific structures and function details disclosed herein are intended for the mere purposes of describing specific embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0016] As used herein, terms "first'', "second', or the like are merely used for illustrative purposes, and shall not be construed as indicating relative importance or implicitly indicating the number of technical features specified. Thus, unless otherwise specified, the features defined by "first-and "second" may explicitly or implicitly include one or more of such features. Terms "multiple-, -a plurality of', and the like mean two or more. Term "comprising", "including", and any variants thereof mean non-exclusive inclusion, so that one or more other features, integers, steps, operations, units, components, and/or combinations thereof may be present or added.

[0017] In addition, terms "center-, "transverse", "up", "down", "left", "right", "vertical", horizontal", "top'', -bottom", "inside", "outside", or the like are used to indicate orientational or relative positional relationships based on those illustrated in the drawings. They are merely intended for simplifying the description of the present disclosure, rather than indicating or implying that the device or element referred to must have a particular orientation or be constructed and operate in a particular orientation. Therefore, these terms are not to be construed as restricting the present disclosure.

[0018] Furthermore, as used herein, terms "installed on", "mounted on", "connected to", "coupled to", "connected with", and "coupled with" should be understood in a broad sense unless otherwise specified and defined. For example, they may indicate a fixed connection, a detachable connection, or an integral connection. They may denote a mechanical connection, or an electrical connection. They may denote a direct connection, a connection through an intermediate, or an internal connection between two elements. For those of ordinary skill in the art, the specific meanings of the above terms as used in the present application can be understood depending on specific contexts [0019] Hereinafter this application will be described in further detail with reference to the accompanying drawings and some optional embodiments.

[0020] Embodiment 1: [0021] Referring to FIG. 1, as a first embodiment of the present application, a schematic top view of a display motherboard is disclosed. The display motherboard 1 includes a plurality of uncut display panels 10. The display motherboard 1 includes a plurality of cutting lines 2 along the edges of the uncut display panels 10. The display motherboard 1 is further includes test terminals. The test traces 110 of each uncut display panel 10 are respectively connected to the test terminals (not shown in the FIG.), and are exposed at the positions where they intersect the corresponding cutting line 2 after cutting. In particular, the display motherboard 1 is further includes a plurality of test common lines 3, and each display panel 10 includes a plurality of test traces 110. The multiple test traces 110 are respectively connected to the multiple test common lines 3 in one-to-one correspondence, and are in turn connected to the test terminals through the test common lines 3. The large display motherboard 1 further includes multiple cutting lines 2, and the display panels 10 can be cut off from the large display motherboard 1 by cutting along the multiple cutting lines 2. Accordingly, at the positions of the cutting lines 2, the test traces 110 on the side of each display panel 10 are exposed.

100221 Referring to FIG. 2, there is shown a schematic diagram of a test circuit of a display panel according to a first embodiment of the present application, disclosing a test circuit of a display panel. The display panel 10 includes a high-level signal trace and a low-level signal trace, and the high-level signal trace and the low-level signal trace are a driving circuit of the display panel 10. The test circuit 100 includes a plurality of test traces 110, a plurality of first active switches 130, and a protection circuit 140. The plurality of test traces 110 includes a high-level signal test trace, a low-level signal test trace, and at least one test signal trace 113. The plurality of first active switches 130 are disposed in one-to-one correspondence with the test traces 110. The first active switches 130 control the turn-on and turn-off of the test signal trace 113, the low-level signal test trace, and the high-level signal test trace. The low-level signal trace is connected to the low-level signal test trace through a respective first active switch 130. The high-level signal trace is connected to the high-level signal test trace through another respective first active switch 130. The high-level signal test trace is also connected to the control terminal of each of the first active switches 130. The protection circuit 140 includes a control signal input terminal and a control signal output terminal. The control signal input terminal is connected to the high-level signal trace and the low-level signal trace. The control signal output terminal is connected to the control terminal of each of the first active switches 130. When the display panel is operating normally, the protection circuit 140 receives the low-level signal on the low-level signal trace and outputs the control signal to control the first active switches to be turned off 100231 In this application, the protection circuit 140 is connected to both the high-level signal trace and the low-level signal trace. During the test stage of the display panel 10, the conduction of the test traces 110 is controlled by the high-level signal on the high-level signal test trace. During the display stage of the display panel 10, the high-level signal and the low-level signal on the high-level signal trace and the low-level signal trace control the test trace sl 10 to be turned off Thus, while the testing is not affected during the test stage, during the display stage of the display panel 10, the test traces 110 no longer carry charges near the exposed end by virtue of the protection circuit 140 and the first active switches, thus preventing problems such as short circuit and ESD (Electro-Static discharge) at the exposed positions of the test traces 110.

[0024] It should be noted that the connection of the high-level signal trace and the low-level signal trace to the driving circuit of the display panel 10 means that when the display panel 10 displays, the signals provided by the circuit board are transmitted to other circuits such as the driving circuit on the display panel 10 along the high-level signal trace and the low-level signal trace. The high-level signal test trace and the low-level signal test trace are used to provide a test signal for the display panel 10 by an external test interface such as a probe through the high-level signal test trace and the low-level signal test trace during the test process. However, during normal display, the signal is no longer transmitted through the high-level signal test trace and the low-level signal test trace. The test traces 110 may be connected to the internal circuits, and there may be charges on the test traces 110 during the normal display process. A core idea of the present application is to turn off all the first active switches 130 when the display panel 10 is displaying through an in-panel low-level signal. However, during the test stage, the low level signal will not turn off the first active switches 130, but the first active switches 130 will be turned on by the high level signal, so that the test signal can be transmitted to the internal circuits of the display panel 10 through the first active switches 130.

[0025] In particular, the high-level signal and low-level signal used in this application are the VGH signal (that is, the gate-on voltage signal) and the VGL signal (that is, the gate-off voltage signal). The VGH and VGL signals are the high level and low level of a scanning signal of the display panel, which are themselves used to control the turning on and off of the pixel active switches of the display panel. The display panel 10 includes a gate-on voltage trace 11 and a gate-off voltage trace 12. The plurality of test traces 110 includes a gate-on voltage test trace 111, a gate-off voltage test trace 112, and at least one test signal trace 113. The gate-on voltage trace 11 is connected to the gate-on voltage test trace 111. The gate-off voltage trace 12 is connected to the gate-off voltage test trace 112. The plurality of first active switches 130 are disposed in one-to-one correspondence with the test signal trace 113, the gate-off voltage test trace 112, and the gate-on voltage test trace 111. The gate-on voltage trace 11 is connected to the gate-on voltage test trace 111 through a first active switch 130. The gate-off voltage trace 12 is connected to the gate-off voltage test trace 112 through another first active switch 130. The first active switches 130 control the turn-on and turn-off of the test signal trace 113, the gate-off voltage test trace 112, and the gate-on voltage test trace 111. The protection circuit 140 includes a control signal input terminal and a control signal output terminal. The control signal input terminal is connected to the gate-on voltage trace and the gate-off voltage trace. The control signal output terminal is connected to the control terminal of each of the first active switches 130. When the display panel is operating normally, the protection circuit 140 receives the low-level signal on the low-level signal trace and outputs the control signal to control the first active switches to be turned off The gate-on voltage signal is a gate-on voltage, which is a high level signal. The gate-off voltage signal is used as a gate-off voltage, which is a low-level signal. The first active switches 130 of the present application can be turned on under the action of the gate-on voltage signal, and kept off under the action of the gate-off voltage signal.

[0026] It should be noted that the gate-off voltage test trace 112 is also connected through a first active switch 130. In the test stage, the first active switches 130 are controlled to be turned on by the gate-on voltage signal, so that the gate-off voltage signal and other test data signals are transmitted to the inside of the display panel 10. The test signal traces 113 include a frame scan start signal (Start Vertical, STV) test trace, a clock signal test trace, a reset signal test trace, and the like. Of course, only some test signals are listed here. The input test signals in different test function stages, such as booting test and RGB test may be different, but they are all applicable to the test circuit 100 of the present application. The first active switches 130 can be adjusted according to the actual number of test signal traces 113, so that each test signal trace 113 can be controlled.

[0027] Here, the gate-on voltage signal and the gate-off voltage signal also need to be input by the test traces 110 during the test stage. The input of the gate-off voltage signal is controlled by the first active switches 130. In particular, the exposed position of each test trace 110 is a test input terminal, and the control terminal of the first active switch 130 is connected to the test input terminal of the gate-on voltage test trace 111. When the plurality of first active switches are in the test stage of the display panel, the gate-on voltage signal on the gate-on voltage test trace is received to control the first active switches to be turned on. The protection circuit 140 does not output a control signal to the control terminals of the first active switches during the test stage of the display panel.

[0028] In particular, the control terminal and input terminal of the first active switch 130 between the gate-on voltage test trace and the gate-on voltage trace are connected together. During the test stage, the test input terminal of the gate-on voltage test trace 111 inputs the gate-on voltage signal and turns on the respective first active switch 130, and meanwhile transmits the gate-on voltage signal to the gate-on voltage trace 11. When the display panel 10 is operating normally, the gate-on voltage trace 11 will receive the gate-on voltage signal from the circuit board. The gate-on voltage signal will not be transmitted to the test input terminal of the gate-on voltage test trace 111 due to the isolation of the corresponding first active switch 130, so that the exposed position of the gate-on voltage test trace 111 will not carry charges.

[0029] In particular, the protection circuit 140 includes a second active switch 142. The input terminal and the control terminal of the second active switch 142 are connected to the gate-on voltage trace 11. The output terminal of the second active switch 142 is connected to the test input terminal of the gate-off voltage test trace 112. The protection circuit 140 further includes a third active switch 151. The input terminal of the third active switch 151 is connected to the gate-off voltage trace 12. The control terminal of the third active switch 151 is connected to the output terminal of the second active switch 142. The output terminal of the third active switch 151 is connected to the control terminal of the first active switch 130. During the test stage of the display panel 10, the gate-off voltage signal on the gate-off voltage test trace 112 controls the third active switch 151 to be turned off. During the display stage of the display panel 10, the gate-on voltage signal on the gate-on voltage trace 11 controls the third active switch 151 to be turned on. The second control signal is the gate-off voltage signal on the gate-off voltage trace 12. The third active switch 151 receives the gate-off voltage signal on the gate-off voltage trace 12 to control the first active switch 130 to turn off [0030] During the test stage of the display panel 10, the gate-on voltage signal output by the first active switch 130 on the gate-on voltage test trace controls the second active switch 142 to be turned on, which in turn transmits the gate-on voltage signal to the control terminal of the third active switch 151. At this time, the control terminal of the third active switch 151 is connected to the test input terminal of the gate-off voltage test trace 112 at the same time. The direct connection between the gate-on voltage signal and the gate-off voltage signal may cause a short circuit causing the circuit to be burned down. But at this time, the gate-on voltage signal and the gate-off voltage signal are connected through the intermediate second active switch 142, so a short circuit will not be caused, and it will cause the voltage of the control terminal of the third active switch 151 to be forcibly pulled down by the gate-off voltage signal, so that the third active switch 151 is in the off state. As such, the gate-off voltage signal on the gate-off voltage trace 12 cannot be transmitted to the control terminal of the first active switch 130 through the third active switch 151, and so the first active switch 130 is still turned on under the control of the gate-on voltage signal input from the test input terminal of the gate-on voltage test trace 111. In the display stage of the display panel 10, the test input terminals of all test traces 110 are not inputting test signals at this time, and the signals required by the display panel 10 are all provided by the circuit board. That is, the gate-on voltage signal on the gate-on voltage trace 11 and the gate-off voltage signal on the gate-off voltage trace 12 are provided by the circuit board. The gate-on voltage signal on the gate-on voltage trace 11 turns on the second active switch 142, and transmits the gate-on voltage signal to the control terminal of the third active switch 151. At this time, although the control terminal of the third active switch 151 is still connected to the test input terminal of the gate-off voltage test trace 112, the test input terminal of the gate-off voltage test trace 112 no longer provides the gate-off voltage signal. Therefore, the third active switch 151 is controlled to be turned on by the gate-on voltage signal. The third active switch 151 transmits the gate-off voltage signal on the gate-off voltage trace 12 to the control terminal of the first active switch 130 Although the control terminal of the first active switch 130 is also connected to the test input terminal of the gate-on voltage test terminal, the test input terminal of the gate-on voltage test terminal no longer provides the gate-on voltage signal. Therefore, the first active switch 130 is controlled to be turned off by the gate-off voltage signal, so that the test signal trace 113 and the gate-off voltage test trace 112 are in a disconnected state. Accordingly, there are no charges at the test input terminals of the test signal traces 113 and the gate-off voltage test trace 112.

100311 FIG. 3 shows a test circuit 100 of a display panel 10 according to a second embodiment. As a variant of the first embodiment, a test circuit 100 for a display panel 10 is disclosed. The difference from FIG. 2 is that the protection circuit 140 further includes a fourth active switch 152. The control terminal of the fourth active switch 152 is connected to the test input terminal of the gate-on voltage test trace 111. The control terminal of the third active switch 151 is connected to the test input terminal of the gate-off voltage test trace 112 through the fourth active switch 152. The other parts are the same as that of the first embodiment and so are not to be repeated here.

[0032] This variant embodiment is not much different from the previous embodiment in the test stage In particular, in the test stage, the control terminal of the fourth active switch 152 receives the gate-on voltage signal on the test input terminal of the gate-on voltage test trace 111, which controls the fourth active switch 152 to be turned on, so that the control terminal of the third active switch 151 is connected to the gate-off voltage signal on the gate-off voltage test trace 112. The difference lies in the normal operating stage of the display panel 10. Since the test input terminal of the gate-on voltage test trace 111 no longer provides the gate-on voltage signal, the fourth active switch 152 is not turned on, so that in the testing stage, the output terminal of the second active switch 142 is no longer connected to the test input terminal of the gate-off voltage test trace 112, which prevents the circuit from being affected by the gate-on voltage signal at the test input terminal.

[0033] In particular, the first active switch 130, the second active switch 142, the third active switch 151, and the fourth active switch 152 are each an N-type thin film transistor. Of course, they may also be P-type thin film transistors, and the corresponding circuit design needs to be changed, and the corresponding changed solution also falls in the scope of protection of the present application.

[0034] In another modified embodiment, the test signal traces 113 include a frame scan start signal test trace, a clock signal test trace, a reset signal test trace, a gate-on voltage test trace 111, and a gate-off voltage test trace 112. That is, a first active switch HO is disposed on each of the test signal traces 113, and the control terminal of each of the first active switches 130 is connected to the protection circuit 140. In this embodiment, the high-level signal trace is a VDD trace, the high-level signal test trace is a VDD test trace, the low-level signal trace is a VSS trace, and the low-level signal test trace is a VSS test trace. Its circuit design is basically the same as the circuit design of the above-mentioned embodiment, and so is not to be repeated here. In order to prevent the short circuit between the VDD test trace and the VSS test trace, resistors can be set in series to prevent short circuit. Furthermore, in the previous embodiment, a resistor(s) may also be set between the output terminal of the second active switch and the gate-off voltage test trace, and the control terminal of the third active switch is connected to the end of the resistor(s) adjacent to the test input terminal of the gate-off voltage test trace.

[0035] Referring now to FIG. 4, as a third embodiment of the present application, a display device is disclosed. The display device 200 includes a conductive tape 201, a display panel 10, and a test circuit 100 for the display panel 10 that is disclosed in the first or second embodiment above. The conductive tape is used to cover exposed positions of the plurality of test traces 110.

[0036] In this embodiment, since the conductive tape may be used to be attached to the side of the display panel 10, its purpose is to conduct the static electricity on the display panel 10 to the back plate or the ground terminal, and due to the design of the motherboard, exposed test traces 110 may be formed on the side of the display panel 10. In particular, in the display industry, the technological process includes: motherboard processing cell assembly cutting into Q-panel cutting into a single display panel 10 -> bonding circuit boards, etc. -> module production. In the current process flow, the last step is module production, including backlight combination, black conductive tape covering the circuit board, etc. However, during the lighting inspection process, there will always be unexplained black screens and failure to light up. After analysis, it is known that after the Q-panel is cut into a single display panel 10, the test traces 110 used in the original test stage are broken, and multiple test traces 110 form "metal points" on the cross-section, while the conductive tape that plays the role of preventing light leakage and attaching may be made of aluminum. In this way, after the test traces 110 are broken, a short circuit is formed between the metal points and the ground terminal on the circuit board via the black conductive tape, so that the manufactured module cannot be normally lit up. However, in this embodiment, by designing the test circuit 100 according to the first or second embodiment, the metal points of the test traces 110 at the exposed end no longer carry charges, so that there is no short circuit.

[0037] It should be noted that the inventive concept of the present application can be formed into many embodiments, but the length of the application document is limited and so these embodiments cannot be enumerated one by one. The technical features can be arbitrarily combined to form a new embodiment, and the original technical effect may be enhanced after the various embodiments or technical features are combined [0038] The technical solutions of the present application can be widely used in various display panels, such as TN (Twisted Nematic) display panels, 1PS (1n-Plane Switching) display panels, VA (Vertical Alignment) display panels, and MVA (Multi-Domain Vertical Alignment) display panels Of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, may also be applicable to the above solutions [0039] The foregoing description is merely a further detailed description of the present application made with reference to some specific illustrative embodiments, and the specific implementations of the present application will not be construed to be limited to these illustrative embodiments. For those having ordinary skill in the technical field to which this application pertains, numerous simple deductions or substitutions may be made without departing from the concept of this application, which shall all be regarded as falling in the scope of protection of this application.

Claims (20)

2. I. A test circuit of a display panel, the display panel comprising a high-level signal trace and a low-level signal trace that are connected to a driving circuit of the display panel, the test circuit comprising: a plurality of test traces, comprising a high-level signal test trace, a low-level signal test trace, and at least one test signal trace; a plurality of first active switches, disposed in one-to-one correspondence with the plurality of test traces and used to control turn-on and turn-off of the at least one test signal trace, the low-level signal test trace, and the high-level signal test trace; wherein the low-level signal trace is connected to the low-level signal test trace through a respective one of the plurality of first active switches, the high-level signal trace is connected to the high-level signal test trace through another respective first active switch, and wherein the high-level signal test trace is further connected to a control terminal of each of the plurality of first active switches; a protection circuit, comprising a control signal input terminal and a control signal output terminal, wherein the control signal input terminal is connected to each of the high-level signal trace and the low-level signal trace, and the control signal output terminal is connected to the control terminal of each of the plurality of first active switches; wherein when the display panel is operating normally, the protection circuit is operative to receive a low-level signal on the low-level signal trace and output a control signal to control the plurality of first active switches to be turned off 2. The test circuit as recited in claim 1, wherein the plurality of test traces are exposed from a side surface of the display panel.
3. 3. The test circuit as recited in claim 1, wherein the high-level signal trace is a gate-on voltage trace, and the high-level signal test trace is a gate-on voltage test trace, the low-level signal trace is a gate-off voltage trace, and the low-level signal test trace is a gate-off voltage test trace.
4. 4. The test circuit as recited in claim 3, wherein an exposed position of each of the plurality of test traces is a test input terminal, and wherein the control terminal of each of the plurality of first active switches is connected to the test input terminal of the gate-on voltage test trace; wherein during a test stage of the display panel, the plurality of the first active switches are operative to receive a gate-on voltage signal from the gate-on voltage test trace to control the plurality of first active switches to be turned on, and the protection circuit does not output a control signal to the control terminal of each of the plurality of first active switches during the test stage of the display panel.
5. The test circuit as recited in claim 4, wherein the protection circuit comprises a second active switch and a third active switch, wherein an input terminal and a control terminal of the second active switch are each connected to the gate-on voltage trace, and wherein an output ten-final of the second active switch is connected to a test input terminal of the gate-off voltage test trace; wherein an input terminal of the third active switch is connected to the gate-off voltage trace, a control terminal of the third active switch is connected to the output terminal of the second active switch, and an output terminal of the third active switch is connected to the control terminal of each of the plurality of first active switches; wherein during the test stage of the display panel, a gate-off voltage signal on the gate-off voltage test trace is operative to control the third active switch to be turned off; during the display stage of the display panel, a gate-on voltage signal on the gate-on voltage trace is operative to control the third active switch to be turned on, and the third active switch is operative to receive the gate-off voltage signal on the gate-off voltage trace to control each of the plurality of first active switches to be turned off.
6. 6. The test circuit as recited in claim 5, wherein the protection circuit further comprises a fourth active switch, wherein a control terminal of the fourth active switch is connected to the test input terminal of the gate-on voltage test trace, a control terminal of the third active switch is connected to the test input terminal of the gate-off voltage test trace through the fourth active switch.
7. 7. The test circuit as recited in claim 1, wherein the at least one test signal trace comprises a frame scan start signal test trace, a clock signal test trace, and a reset signal test trace.
8. 8. The test circuit as recited in claim 6, wherein the first active switch, the second active switch, the third active switch, and the fourth active switch are each an N-type thin film transistor.
9. 9. The test circuit as recited in claim 4, wherein, during the test stage of the display panel, the test input terminal of the gate-on voltage test trace and the test input terminal of the gate-off voltage test trace and operative to respectively provide the gate-on voltage signal and the gate-off voltage signal; wherein when the display panel is operating normally, the test input terminal of the gate-on voltage test trace and the test input terminal of the gate-off voltage test trace do not provide the gate-on voltage signal and the gate-off voltage signal.
10. 10. The test circuit as recited in claim 1, wherein during the test stage, the low-level signal trace is operative to receive a low-level signal from the low-level signal test trace arid transmit it to an inside of the display panel; wherein when the display panel is operating normally, the low-level signal trace is operative to receive a low-level signal from within the display panel; wherein during the test stage of the display panel, the protection circuit does not output a control signal to the control terminal of each of the plurality of first active switches; wherein when the display panel is working normally, the protection circuit is operative to receive an low-level signal on the low-level signal trace from within the display panel and output a control signal to control each of the plurality of first active switches to be turned off.
11. 11. A display device, comprising a conductive tape and a display panel, the conductive tape covering exposed positions of a plurality of test traces of the display panel, the display panel comprising a high-level signal trace and a low-level signal trace that are connected to a driving circuit of the display panel, the test circuit comprising: a plurality of test traces, comprising a high-level signal test trace, a low-level signal test trace, and at least one test signal trace; a plurality of first active switches, disposed in one-to-one correspondence with the plurality of test traces and used to control turn-on and turn-off of the at least one test signal trace, the low-level signal test trace, and the high-level signal test trace; wherein the low-level signal trace is connected to the low-level signal test trace through a respective one of the plurality of first active switches, the high-level signal trace is connected to the high-level signal test trace through another respective first active switch, and wherein the high-level signal test trace is further connected to a control terminal of each of the plurality of first active switches; a protection circuit, comprising a control signal input terminal and a control signal output terminal, wherein the control signal input terminal is connected to each of the high-level signal trace and the low-level signal trace, and the control signal output terminal is connected to the control terminal of each of the plurality of first active switches, wherein when the display panel is operating normally, the protection circuit is operative to receive a low-level signal on the low-level signal trace and output a control signal to control each of the plurality of first active switches to be turned off.
12. 12. The display device as recited in claim 11, wherein the plurality of test traces are exposed from a side surface of the display panel and are in contact with the conductive tape.
13. 13. The display device as recited in claim 11, wherein the high-level signal trace is a gate-on voltage trace, the high-level signal test trace is a gate-on voltage test trace, the low-level signal trace is a gate-off voltage trace, and the low-level signal test trace is a gate-off voltage test trace.
14. 14. The display device as recited in claim 13, wherein an exposed position of each of the plurality of test traces is a test input terminal, and the control terminal of each of the plurality of first active switches is connected to the test input terminal of the gate-on voltage test trace; wherein during a test stage of the display panel, each of the plurality of the first active switches is operative to receive a gate-on voltage signal of the gate-on voltage test trace to control each of the plurality of first active switches to be turned on; during the test stage of the display panel, the protection circuit does not output a control signal to the control terminal of each of the plurality of first active switches.
15. 15. The display device as recited in claim 14, wherein the protection circuit comprises a second active switch and a third active switch, wherein an input terminal and a control terminal of the second active switch are each connected to the gate-on voltage trace, and wherein an output terminal of the second active switch is connected to the test input terminal of the gate-off voltage test trace, wherein an input terminal of the third active switch is connected to the gate-off voltage trace, a control terminal of the third active switch is connected to the output terminal of the second active switch, and wherein an output terminal of the third active switch is connected to the control terminal of each of the plurality of first active switches, wherein during the test stage of the display panel, the gate-off voltage signal of the gate-off voltage test trace is operative to control the third active switch to be turned off; and during the display stage of the display panel, the gate-on voltage signal of the gate-on voltage trace is operative to control the third active switch to be turned on, and the third active switch is operative to receive a gate-off voltage signal from the gate-off voltage trace to control each of the plurality of first active switches to be turned off.
16. 16. The display device as recited in claim 15, wherein the protection circuit further comprises a fourth active switch, wherein a control terminal of the fourth active switch is connected to the test input terminal of the gate-on voltage test trace, and the control terminal of the third active switch is connected to the test input terminal of the gate-off voltage test trace through the fourth active switch.
17. 17. The display device as recited in claim 11, wherein the at least one test signal trace comprises a frame scan start signal test trace, a clock signal test trace, and a reset signal test trace.
18. 18. The display device as recited in claim 16, wherein the first active switch, the second active switch, the third active switch, and the fourth active switch are each an N-type thin film transistors.
19. 19 The display device as recited in claim 14, wherein during the test stage of the display panel, the test input terminal of the gate-on voltage test trace and the test input terminal of the gate-off voltage test trace and operative to respectively provide the gate-on voltage signal and the gate-off voltage signal; wherein when the display panel is operating normally, the test input terminal of the gate-on voltage test trace and the test input terminal of the gate-off voltage test trace do not provide the gate-on voltage signal and the gate-off voltage signal.
20. 20. The display device as recited in claim 11, wherein during the test stage, the low-level signal trace is operative to receive a low-level signal of the low-level signal test trace and transmit the low-level signal to an inside of the display panel; when the display panel is operating normally, the low-level signal trace is operative to receive a low-level signal from within the display panel, and wherein the protection circuit does not output a control signal to the control terminal of each of the plurality of first active switches during the test stage of the display panel; wherein when the display panel is operating normally, the protection circuit is operative to receive a low-level signal on the low-level signal trace from within the display panel and output the control signal to control each of the plurality of first active switches to be turned off.