CN109461415B

CN109461415B - Display panel's drive circuit and display panel

Info

Publication number: CN109461415B
Application number: CN201811337228.4A
Authority: CN
Inventors: 王明良
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2018-11-12
Filing date: 2018-11-12
Publication date: 2020-10-16
Anticipated expiration: 2038-11-12
Also published as: CN109461415A

Abstract

The invention discloses a drive circuit of a display panel and the display panel, comprising: the time sequence control circuit is used for reading the initialization data of the display panel; the power supply circuit is used for supplying power to the display panel; a gate driver for driving scan lines of the panel; the voltage reduction circuit is used for carrying out voltage reduction processing on the input signal; and a switching circuit; the sequential control circuit is connected with a first input end of the switch circuit, the power supply circuit is connected with a second input end of the switch circuit through the voltage reduction circuit, and an output end of the switch circuit is connected with the grid driver. The abnormal starting picture is avoided through the output of the grid driver, and meanwhile, the design is simple and easy to implement, the cost is lower, and the starting time is saved.

Description

Display panel's drive circuit and display panel

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a driving circuit thereof.

Background

With the continuous development of liquid crystal technology, liquid crystal displays have been widely used in the fields of computers, mobile phones, televisions, and the like. Since the lcd panel itself does not have a light-emitting property, a backlight module is required to be added to the panel, and the backlight module is one of the key components of the lcd, and is used to provide a light source with sufficient brightness and uniform distribution, so that the lcd panel can normally display images. The lighting effect of the backlight module directly affects the visual effect of the liquid crystal display. When the display device is started, each unit needs to be initialized and configured, and only after each unit finishes the initialization and configuration, the display panel of the display device can normally display.

When the display device is just started, the internal chip of the display device needs a certain time to read the initialization data, and the power supply configuration also needs a certain time, so that the backlight module of the display device works normally in the period, and the abnormal starting picture is easy to appear.

Disclosure of Invention

In order to achieve the above object, the present invention provides a driving circuit of a display panel and a display panel, which can improve the power-on efficiency.

The invention discloses a driving circuit of a display panel, comprising: the time sequence control circuit is used for reading the initialization data of the display panel; the power supply circuit is used for supplying power to the display panel; a gate driver for driving scan lines of the panel; the voltage reduction circuit is used for carrying out voltage reduction processing on the input signal; and a switching circuit; the switching circuit comprises a first input terminal and a second input terminal;

the sequential control circuit is connected with a first input end of the switch circuit, the power supply circuit is connected with a second input end of the switch circuit through the voltage reduction circuit, and an output end of the switch circuit is connected with the grid driver.

Optionally, the switching circuit includes: the first judging circuit outputs a first logic signal according to the signal input by the time sequence control circuit; a second judgment circuit for outputting a second logic signal according to the signal input from the voltage reduction circuit; a third judgment circuit for outputting a third logic signal according to the first logic signal and the second logic signal;

the input end of the first judging circuit is connected with the time sequence control circuit, the input end of the second judging circuit is connected with the voltage reduction circuit, the output ends of the first judging circuit and the second judging circuit are connected with the input end of a third judging circuit, and the output end of the third judging circuit is connected with the grid driver.

Optionally, the voltage reducing circuit includes a first resistor and a second resistor, the first resistor is connected in series with the second resistor, a first end of the first resistor is connected to the power supply circuit, a second end of the first resistor is connected to a first end of the second resistor, a second end of the second resistor is grounded, and a second input end of the switching circuit is connected between the first resistor and the second resistor.

Optionally, the resistance of the first resistor is greater than the resistance of the second resistor.

Optionally, the first judging circuit includes a first active switch, an input end of the first active switch is connected to the timing control circuit, and an output end of the first active switch is connected to the third judging circuit.

Optionally, the second judging circuit includes a second active switch, an input end of the second active switch is connected to the voltage-reducing circuit, and an output end of the second active switch is connected to the third judging circuit.

Optionally, the third determining circuit includes a third active switch, an input end of the third active switch is connected to the first determining circuit and the second determining circuit, respectively, and an output end of the third active switch is connected to the gate driver.

Optionally, the first determining circuit includes a first gate circuit, the second determining circuit includes a second gate circuit, and the third determining circuit includes a third gate circuit.

The invention also discloses a driving circuit of the display panel, which comprises: the time sequence control circuit is used for reading the initialization data of the display panel; the power supply circuit is used for supplying power to the display panel; a gate driver for driving scan lines of the panel;

the drive circuit further includes: the circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first field effect transistor, a second field effect transistor and a third field effect transistor;

the time sequence control circuit is connected with the grid electrode of the second field effect transistor; the power supply circuit is connected with a first resistor and a second resistor in series and grounded, the grid electrode of the first field effect transistor is connected between the first resistor and the second resistor, the drain electrode of the first field effect transistor and the drain electrode of the second field effect transistor are connected to the grid electrode of the third field effect transistor in common, and the grid electrode of the third field effect transistor is connected with a third resistor in series and grounded; the source level of the first field effect transistor, the source level of the second field effect transistor and the source level of the third field effect transistor are connected with power supply voltage, the drain electrode of the third field effect transistor is connected with the grid driver, and the drain electrode of the third field effect transistor is connected with a fourth resistor in series and is grounded.

The invention also discloses a display panel comprising the drive circuit of the display panel.

According to the research of the inventor, when the display device is just started, because the time sequence control circuit needs a certain time to read the external code, and the power supply circuit also needs time to output each voltage, if the backlight is normally opened, the startup picture is abnormal; compared with the method for delaying the backlight opening time, the method for starting the display screen of the display device can ensure that the starting picture is normal, in the application, whether the time sequence control circuit and the power supply circuit are configured or not is judged, if the configuration is completed, the grid driver is restarted to normally work, the display of the panel is driven, if one of the time sequence control chip and the power supply circuit is not configured, the grid driver cannot output the data, the black picture state is kept, the starting picture is prevented from being abnormal, and meanwhile, the method is simple and easy to design, low in cost and capable of saving the.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the invention;

FIG. 2 is a schematic diagram of another driving circuit according to an embodiment of the invention;

FIG. 3 is a schematic diagram of another driving circuit according to an embodiment of the invention;

FIG. 4 is a schematic diagram of another driving circuit according to an embodiment of the invention;

FIG. 5 is a schematic step diagram of a driving method according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a signal waveform according to an embodiment of the present invention;

fig. 7 is a schematic view of another display device according to another embodiment of the present invention.

100, a display panel; 110. a timing control circuit; 120. a power supply circuit; 130. a switching circuit; 1301. a first input terminal; 1302. a second input terminal; 131. a first judgment circuit; 1311. a first active switch; 1312. a first gate circuit; 1313. a first not gate circuit; 132. a second judgment circuit; 1321. a second active switch; 1322. a second gate circuit; 1323. a second not gate circuit; 133. a third judgment circuit; 1331. a third active switch; 1332. a third gate circuit; 1333. a NOR gate circuit; 140. a gate controller; 150. a voltage reduction circuit; 161. a detection circuit; 162. a gate circuit; 163. an AND gate circuit; 200. a backlight circuit.

Detailed Description

It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.

Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The invention will be further elucidated with reference to the drawings and alternative embodiments.

As shown in fig. 1 to fig. 3, an embodiment of the invention discloses a driving circuit of a display panel, including: a timing control circuit 110 for reading initialization data of the display panel; a power supply circuit 120 for supplying power to the display panel; a gate driver 140 for driving scan lines of the panel; a voltage reduction circuit 150 for performing voltage reduction processing on the input signal; and a switching circuit 130; the switching circuit 130 comprises a first input 1301 and a second input 1302; the timing control circuit 110 is connected to the first input terminal 1301 of the switch circuit 130, the power supply circuit 120 is connected to the second input terminal 1302 of the switch circuit 130 through the voltage step-down circuit 150, and the output terminal of the switch circuit 130 is connected to the gate driver 140.

In this scheme, after the configuration of the timing control circuit 110 is completed, a ready signal (ready signal) is output to the switch circuit 130, a start voltage signal (VGH signal) of the power supply circuit 120 is subjected to voltage reduction processing by the voltage reduction circuit 150 and then output to the switch circuit 130, and when the ready signal and the start voltage signal are in a high level state at the same time, the switch circuit 130 outputs a high level to control the output of the gate driver 140; if one of the timing control chip and the power circuit 120 is not configured, the gate driver 140 cannot output the signal, so that the black screen state is maintained, and the abnormal starting screen is avoided.

In an optional embodiment, the switch circuit 130 includes: a first judgment circuit 131 for outputting a first logic signal according to a signal input from the timing control circuit 110; a second judgment circuit 132 for outputting a second logic signal according to the signal input from the voltage reduction circuit 150; a third judgment circuit 133 that outputs a third logic signal based on the first logic signal and the second logic signal; the input terminal of the first judging circuit 131 is connected to the timing control circuit 110, the input terminal of the second judging circuit 132 is connected to the voltage step-down circuit 150, the output terminals of the first judging circuit 131 and the second judging circuit 132 are connected to the input terminal of the third judging circuit 133, and the output terminal of the third judging circuit 133 is connected to the gate driver 140.

In this embodiment, the first determining circuit 131 is used to determine the ready signal output by the timing control circuit 110, and when the ready signal rises from a low level to a high level, the first determining circuit 131 outputs the first logic signal; the second determining circuit 132 is used for determining the VGH signal output by the voltage decreasing circuit 150, and when the VGH signal is increased from a low level to a high level, the second determining circuit 132 outputs a second logic signal; when the first logic signal and the second logic signal are at a high level, the third judgment circuit 133 outputs a high level to control the gate driver 140 output.

In an alternative embodiment, the voltage dropping circuit 150 includes a first resistor and a second resistor, the first resistor is connected in series with the second resistor, a first end of the first resistor is connected to the power circuit 120, a second end of the first resistor is connected to a first end of the second resistor, a second end of the second resistor is grounded, and a second input end of the switching circuit 130 is connected between the first resistor and the second resistor.

In this embodiment, the voltage dropping circuit 150 is two series resistors, and the principle of voltage division of the series resistors is utilized to reduce the high-voltage start voltage signal to a low-voltage power start signal and output the low-voltage power start signal to the second determination circuit 132, so as to prevent the start voltage signal from being directly output to the second determination circuit 132, which may cause circuit damage due to excessive voltage.

In this embodiment, optionally, the resistance of the first resistor is greater than the resistance of the second resistor. In the scheme, the starting voltage signal can reach 30V at most, the second judgment circuit 132 is enough to reach 3.7V, generally can not exceed 5V, the voltage is divided according to the series resistor and is far away, the larger the resistor is, the more the voltage is divided, and when the resistance value of the first resistor is larger than that of the second resistor, the power starting signal is output to the second judgment circuit 132, and can be output normally without damaging the circuit.

Optionally, in this embodiment, the first determining circuit 131 includes a first active switch 1311, an input end of the first active switch 1311 is connected to the timing control circuit 110, and an output end of the first active switch 1311 is connected to the third determining circuit 133.

Optionally, in this embodiment, the second determining circuit 132 includes a second active switch 1321, an input end of the second active switch 1321 is connected to the voltage-reducing circuit 150, and an output end of the second active switch 1321 is connected to the third determining circuit 133.

In an alternative embodiment, the third determining circuit 133 includes a third active switch 1331, an input terminal of the third active switch 1331 is respectively connected to the first determining circuit 131 and the second determining circuit 132, and an output terminal of the third active switch 1331 is connected to the gate driver 140.

In this embodiment, the first active switch 1311 is a PMOS P1 (P-type field effect transistor), the second active switch 1321 is a PMOS P3, the third active switch 1331 is a PMOS P3, as shown in fig. 1, the voltage level at the upper end of R2 is named as V1, V1 controls the gate of the PMOSP1, the Ready signal output by the timing control circuit 110 is used as the gate control signal of the PMOS P2, when the voltage level of the VGH signal is lower during startup, the voltage level of V1 is also lower, since the turn-on voltage VGS of the PMOS is less than 0, P1 is turned on, VDD is the logic voltage of the system, VDD is communicated with R3 through P1 at this time, the voltage level at the upper end of R3 is named as V2, V2 is VDD, and for the PMOS P3, VGS is 0, so P3 cannot be turned on, the state of the signal OE can only be connected to the ground by R4, so that the signal output is output at this time, and the gate driver 140 cannot start up the output low level. Similarly, when the Ready signal of the timing control circuit 110 is at a low level, the PMOS P2 may be turned on, VDD may be turned on by the PMOS P2 and R3, and V2 is equal to VDD, so the PMOS P3 may be controlled to be turned off. It can be seen that as long as either of PMOS P1 and PMOS P2 is open, V2 is equal to VDD, PMOS P3 is turned off, and the OE signal output is low, i.e., if either of the VGH signal and Ready signal is low, the OE signal is low;

that is, only when the voltage level of the VGH signal is sufficient, V1 is at a high level, VGS of the PMOS P1 is equal to 0, PMOSP1 is turned off, and at the same time, the Ready signal of the timing control circuit 110 is at a high level, the PMOS P2 is also turned off, V2 is turned on through R3 and ground, and V2 is equal to 0, then VGS of the PMOS P3 is less than 0, P3 is turned on, VDD is turned on through PMOS P3 and R4, and the OE signal is at a high level, so that as shown in fig. 3, only when the VGH signal and the Ready signal are normally operated, the OE signal is at a high level, and the gate driver 140 starts normal output.

Optionally, the first determining circuit 131 includes a first gate circuit 1312, the second determining circuit 132 includes a second gate circuit 1322, and the third determining circuit 133 includes a third gate circuit 1332.

In this embodiment, as shown in fig. 4, the first gate circuit is a first not gate circuit 1313, the second gate circuit is a second not gate circuit 1323, and the third gate circuit is a nor gate circuit 1333; the nor gate 1333 outputs a high level only when the voltage level of the VGH signal is high, and the first not gate 1313 outputs a low level, and when the voltage level of the Ready signal is high, and the second not gate 1323 outputs a low level, the nor gate 1333 outputs a high level; the switch circuit 130 may be an and circuit, and only when the voltage level of the VGH signal is at a high level, and the voltage level of the Ready signal is at a high level; the and circuit outputs a high level.

As shown in fig. 1, as another embodiment of the present invention, a driving circuit of a display panel is disclosed, including: a timing control circuit 110 for reading initialization data of the display panel; a power supply circuit 120 for supplying power to the display panel; a gate driver 140 for driving scan lines of the panel;

the drive circuit further includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first field effect transistor P1, a second field effect transistor P2 and a third field effect transistor P3;

the timing control circuit 110 is connected to the gate of the second field effect transistor P2; the power supply circuit 120 is connected with the first resistor R1 and the second resistor R2 in series and grounded, the gate of the first field effect transistor P1 is connected between the first resistor R1 and the second resistor R2, the drain of the first field effect transistor P1 and the drain of the second field effect transistor P2 are connected with the gate of the third field effect transistor P3 in common, and the gate of the third field effect transistor P3 is connected with the third resistor R3 in series and grounded; the source of the first field effect transistor P1, the source of the second field effect transistor P2 and the source of the third field effect transistor P3 are connected to the power voltage in common, the drain of the third field effect transistor P3 is connected to the gate driver 140, and the drain of the third field effect transistor is connected in series with the fourth resistor R4 and is grounded.

In the scheme, whether the sequential control circuit 110 and the power circuit 120 are configured or not is judged, if the configuration is completed, the gate driver 140 is started to normally work to drive the panel to display, and if one of the sequential control chip and the power circuit 120 is not configured, the gate driver 140 cannot output, so that the black picture state is kept, the abnormal starting picture is avoided, meanwhile, the design is simple and easy, the cost is lower, and the starting time is saved. As shown in fig. 1, when the voltage level of the VGH signal is sufficient, V1 is at a high level, VGS of the PMOS P1 is equal to 0, the PMOS P1 is turned off, and at the same time, the Ready signal of the timing control circuit 110 is at a high level, the PMOS P2 is also turned off, at this time, V2 is turned on through R3 and ground, and V2 is equal to 0, then VGS of the PMOS P3 is less than 0, at this time, P3 is turned on, VDD is communicated through PMOS P3 and R4, at this time, the OE signal is at a high level, so that as shown in fig. 3, only when the VGH signal and the Ready signal both operate normally, the OE signal is at a high level, and the gate driver 140 starts normal output.

As shown in fig. 5 to 6, as another embodiment of the present invention, there is also disclosed a driving method of a display device, including the steps of:

s31, synchronously starting the backlight circuit, the timing control circuit 110 and the power supply circuit 120;

s32, the timing control circuit 110 outputs the first signal after initialization;

s33, the power circuit 120 outputs a second signal after starting;

and S34, controlling the gate driver 140 to output the driving signal according to the first signal and the second signal.

In this embodiment, as shown in fig. 6, the first signal is a ready signal, the second signal is a start voltage signal (VGH signal), and the driving signal is an OE signal, and when the ready signal changes from a low level to a high level and the potential of the VGH signal rises from the low level to the high level, the gate driver 140 is controlled to output an OE signal, and at this time, the OE signal changes from the low level to the high level. The start voltage signal is a start voltage for displaying the display device, and the voltage serving as the voltage signal is a voltage with the highest level among the voltages output by the power circuit 120 to the respective units, and is a voltage signal finally generated in the power circuit 120, so that the start voltage signal is used as a reference for determining whether the power circuit 120 has normally output. By judging whether the configuration of the timing control circuit 110 and the power supply circuit 120 is completed, if the configuration is completed, the gate driver 140 is started to normally work, the panel is driven to display, if one of the timing control chip and the power supply circuit 120 is not configured, the gate driver 140 cannot output, the black picture state is kept, the abnormal starting picture is avoided, meanwhile, the design is simple and easy, the cost is low, and the starting time is saved.

As shown in fig. 6, as another embodiment of the present invention, a display device is disclosed, which includes a backlight circuit and a display panel; the backlight circuit 200 is used for providing backlight for the display panel 100; the display panel includes: a timing control circuit 110 for reading initialization data of the display panel; a power supply circuit 120 for supplying power to the display panel 100; a gate driver 140 for driving scan lines of the panel; a detection circuit 161 and a gate circuit 162; the detection circuit 161 reads the start voltage signal and outputs a power supply start signal; the timing control circuit 110 outputs a first signal to the gate circuit; the power supply circuit 120 outputs a start voltage signal to the detection circuit 161, and the detection circuit 161 outputs a power supply start signal to the gate circuit; the gate circuit controls the gate driver 140 to output the driving signal according to the first signal and the power-on signal.

In the scheme, whether the time sequence control circuit 110 and the power supply circuit 120 are configured or not is judged through the control circuit, if the configuration is completed, the grid driver 140 is started to normally work to drive the panel to display, and if one of the time sequence control chip and the power supply circuit 120 is not configured, the grid driver 140 cannot output, so that the black picture state is kept, the abnormal starting picture is avoided, meanwhile, the design is simple and easy, the cost is lower, and the starting time is saved.

It should be noted that, the limitations of the steps involved in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all should be considered to belong to the protection scope of the present disclosure.

The technical solution of the present invention can be widely applied to various display panels, such as TN type display panels (called twisted nematic panels), IPS type display panels (In-Plane Switching), VA type display panels (Multi-domain vertical Alignment technology), and of course, other types of display panels, such as organic light emitting display panels (OLED display panels for short), which can be applied to the above solutions.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A driving circuit of a display panel, comprising:

the time sequence control circuit is used for reading the initialization data of the display panel;

the power supply circuit is used for providing power supply for the display panel;

a gate driver for driving scan lines of the display panel;

the voltage reduction circuit is used for carrying out voltage reduction processing on the input signal;

the switch circuit is used for judging the output signal;

the switching circuit comprises a first input terminal and a second input terminal;

the time sequence control circuit is connected with a first input end of the switch circuit, the power supply circuit is connected with a second input end of the switch circuit through the voltage reduction circuit, and an output end of the switch circuit is connected with the grid driver;

the switching circuit further includes:

the first judging circuit outputs a first logic signal according to the signal input by the time sequence control circuit;

a second judgment circuit for outputting a second logic signal according to the signal input from the voltage reduction circuit;

a third judgment circuit for outputting a third logic signal according to the first logic signal and the second logic signal;

2. The driving circuit of the display panel according to claim 1, wherein the voltage dropping circuit includes a first resistor and a second resistor, the first resistor is connected in series with the second resistor, a first terminal of the first resistor is connected to the power supply circuit, a second terminal of the first resistor is connected to a first terminal of the second resistor, a second terminal of the second resistor is grounded, and a second input terminal of the switching circuit is connected between the first resistor and the second resistor.

3. The driving circuit of the display panel according to claim 2, wherein the first resistor has a resistance value larger than that of the second resistor.

4. The driving circuit of claim 1, wherein the first determining circuit comprises a first active switch, an input terminal of the first active switch is connected to the timing control circuit, and an output terminal of the first active switch is connected to the third determining circuit.

5. The driving circuit of claim 1, wherein the second determining circuit comprises a second active switch, an input terminal of the second active switch is connected to the voltage-reducing circuit, and an output terminal of the second active switch is connected to the third determining circuit.

6. The driving circuit of claim 1, wherein the third determining circuit comprises a third active switch, an input terminal of the third active switch is connected to the first determining circuit and the second determining circuit, and an output terminal of the third active switch is connected to the gate driver.

7. The display panel driving circuit according to claim 1, wherein the first determination circuit includes a first gate circuit, the second determination circuit includes a second gate circuit, and the third determination circuit includes a third gate circuit.

8. A driving circuit of a display panel, comprising:

the power supply circuit is used for supplying power to the display panel;

a gate driver for driving scan lines of the panel;

9. A display panel comprising the driving circuit of the display panel according to any one of claims 1 to 8.