CN211181608U - Power supply time sequence control circuit and display device - Google Patents
Power supply time sequence control circuit and display device Download PDFInfo
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- CN211181608U CN211181608U CN201921693332.7U CN201921693332U CN211181608U CN 211181608 U CN211181608 U CN 211181608U CN 201921693332 U CN201921693332 U CN 201921693332U CN 211181608 U CN211181608 U CN 211181608U
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Abstract
The application discloses power supply sequential control circuit and display device. The power supply timing control circuit includes: the comparison unit is connected to the first power supply and used for providing control voltage according to the reference power supply and the first power supply; and the output unit is connected to the comparison unit and the second power supply and used for providing output voltage according to the control voltage and the second power supply, wherein when the voltage value of the first power supply is smaller than that of the reference power supply, the output voltage is stopped being provided, and when the voltage value of the first power supply is larger than that of the reference power supply, the output voltage is started to be provided. When the first power supply is a low-level voltage, the output voltage is also a low level, and when the first power supply is a high-level voltage, the magnitude of the output voltage is related to that of the second power supply, so that the purpose of controlling the time sequence of the output voltage is achieved.
Description
Technical Field
The utility model relates to an electronic circuit technical field, more specifically relates to a power supply sequential control circuit and display device.
Background
With the popularity of electronic circuits, chips are increasingly being used in a variety of integrated circuits or systems. In the working process of the chip, the power supply timing of the power supply is one of important parameters, for example, a source driver chip (source IC) requires that the power supply XVCC boosts voltage before the power supply AVDD when starting up, and requires that the power supply AVDD turns off before the power supply XVCC when shutting down.
In the prior art, the timing sequences of a Power supply XVCC and a Power supply AVDD of a Power supply chip (Power IC) cannot meet the source requirement, and the actually measured waveform is as shown in fig. 1, where the Power supply AVDD is boosted before the Power supply XVCC, the source driver chip is abnormally turned on, so that the picture is abnormal, and even the source driver chip may be damaged.
Therefore, further improvement of the power supply chip in the prior art is needed to solve the above problems.
SUMMERY OF THE UTILITY MODEL
In view of the above, it is an object of the present invention to provide a power timing control circuit and a display device, wherein an output voltage is provided according to a first power and a second power, and when the first power is a low level voltage, the output voltage is also the low level voltage, so that the timing of the output voltage can be controlled.
According to the utility model discloses an aspect provides a power supply sequential control circuit, include: the comparison unit is connected to a first power supply and used for providing control voltage according to a reference power supply and the first power supply; and the output unit is connected to the comparison unit and the second power supply and used for providing output voltage according to the control voltage and the second power supply, wherein when the voltage value of the first power supply is smaller than the voltage value of the reference power supply, the output voltage is stopped to be provided, and when the voltage value of the first power supply is larger than the voltage value of the reference power supply, the output voltage is started to be provided.
Preferably, the comparing unit includes: a first resistor having a first terminal connected to the first power supply; a second resistor having a first terminal connected to the reference power supply; and a comparator, wherein a positive phase input end of the comparator is connected to the second end of the first resistor, a negative phase input end of the comparator is connected to the second end of the second resistor, a positive power supply end of the comparator is connected to a high level voltage, a negative power supply end of the comparator is connected to a low level voltage, and an output end of the comparator provides the control voltage.
Preferably, the output unit includes: a third resistor, a first end of the third resistor being connected to an output end of the comparison unit; and a switching tube, wherein a control end of the switching tube receives the control voltage through the third resistor, a first path end is connected to the second power supply, and a second path end provides the output voltage, wherein when the control voltage is a low level voltage, the switching tube stops providing the output voltage, and when the control voltage is a high level voltage, the switching tube starts providing the output voltage.
Preferably, the output unit further includes: a fourth resistor, wherein a first end of the fourth resistor is connected to the second path end of the switching tube, and a second end of the fourth resistor is connected to the reference ground.
Preferably, the output unit further includes: and a first end of the fifth resistor is connected to the second power supply, and a second end of the fifth resistor is connected to the first pass end of the switching tube.
Preferably, the switch tube is an N-channel MOS field effect transistor.
Preferably, a voltage value of the output voltage is not greater than a voltage value of the second power supply.
According to another aspect of the present invention, there is provided a display device, including: the power supply chip is used for providing a first power supply and a second power supply; the power supply timing control circuit as described above, configured to generate an output voltage from the first power supply and the second power supply; and a display panel for displaying a picture according to image data, wherein a power supply of the display panel is provided by at least the first power supply and the output voltage.
Preferably, the display panel includes: the grid driving chip is used for providing grid driving data; the source driving chip is used for providing source driving data; and the array substrate is used for displaying pictures according to the source electrode driving data and the grid electrode driving data, wherein the first power supply and the output voltage provide working voltage of the source electrode driving chip.
Preferably, the display panel includes an integrated gate driving circuit, and the first power supply and the output voltage respectively provide a low level signal and a high level signal of the integrated gate driving circuit.
The utility model provides a power supply time sequence control circuit and display device, when first power is low level voltage, output voltage also is the low level, and when first power was high level voltage, output voltage's size was related to the second power, has reached the purpose of control output voltage's chronogenesis.
Furthermore, the power supply time sequence control circuit is simple in structure and small in occupied area, and the purpose of controlling the time sequence of the output voltage can be achieved without replacing the original power supply chip and the original source electrode driving chip in the display device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a timing diagram of a power supply according to the prior art;
fig. 2 shows a schematic diagram of a power supply timing control circuit according to an embodiment of the invention;
fig. 3 shows a timing diagram of a power supply according to an embodiment of the invention;
fig. 4 shows a schematic diagram of a display device according to an embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
In the description of the present invention, it is to be understood that the terms "connected" and "connected," unless otherwise expressly specified or limited, are used in a generic sense, e.g., directly or indirectly through intervening media. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.
Fig. 2 shows a schematic diagram of a power timing control circuit according to an embodiment of the present invention.
As shown in fig. 2, the power supply timing control circuit 110 includes a comparison unit 111 and an output unit 112 for controlling the output timing of the first power supply V1 and the second power supply V2.
The comparison unit 111 comprises a reference supply VFA first resistor R1, a second resistor R2 and a comparator U1 for providing a control voltage according to a first power source V1. A first end of the first resistor R1 is connected to the first power source V1, and a second end is connected to the non-inverting input terminal of the comparator U1; a first terminal of the second resistor R2 is connected to a reference power supply VFAnd a second terminal connected to the inverting input of comparator U1; the positive power supply terminal of the comparator U1 is connected to the power supply VCC, the negative power supply terminal is connected to the reference ground, and the output terminal provides the control voltage.
The output unit 112 includes a third resistor R3 and a switch Q1, and is used for providing an output voltage V2-out according to the control voltage provided by the comparison unit 111. The control terminal of the switch Q1 is connected to the control voltage via a third resistor R3, the first path terminal is connected to the second power source V2, and the second path terminal is used for providing the output voltage V2-out. In this embodiment, the switching Transistor Q1 is preferably an N-channel MOS Field Effect Transistor (MOSFET).
Preferably, the output unit 112 further includes a fourth resistor R4 and a fifth resistor R5, the first path terminal of the switch Q1 is connected to the second power source V2 via the fifth resistor R5, and the second path terminal is connected to the ground via the fourth resistor R4, so as to avoid the second path terminal of the switch Q1 from floating, and provide a path for releasing charges. The fourth resistor R4 and the fifth resistor R5 form a voltage divider circuit, the magnitude of the output voltage V2-out is related to the ratio of the fourth resistor R4 to the fifth resistor R5, and the magnitude of the fourth resistor R4 is much larger than that of the fifth resistor R5, so that the magnitude of the output voltage V2-out is substantially equal to the voltage of the second power supply V2. In an alternative embodiment, the fifth resistor R5 may be omitted in order to make the magnitude of the output voltage V2-out equal to the magnitude of the voltage of the second power source V2.
In this embodiment, when the voltage value of the first power supply V1 is smaller than the reference power supply VFWhen the voltage value of the comparator U1 is equal to the voltage of the reference ground, that is, the control voltage is a low level voltage, the switch Q1 is turned off, and the second path terminal of the switch Q1 stops providing the output voltage V2-out; when the voltage value of the first power supply V1 is greater than the reference power supply VFWhen the voltage value of the voltage source is smaller than the voltage value of the power source VCC, the control voltage output by the comparator U1 is equal to the voltage of the power source VCC, that is, the control voltage is a high level voltage, the switch Q1 is turned on, and the second path terminal of the switch Q1 starts to provide the output voltage V2-out.
It should be understood that the present invention is not limited thereto, and a plurality of power timing control circuits 110 may be combined to realize timing control of a plurality of power supplies. In addition, the same object can be achieved by changing the received signals of the non-inverting input terminal and the inverting input terminal of the comparator U1 in the power timing control circuit 110 and the type of the switching tube Q1.
Fig. 3 shows a timing diagram of a power supply according to an embodiment of the invention.
Taking the first power supply V1 as the power supply XVCC of the source driver chip and the second power supply V2 as the power supply AVDD of the source driver chip as an example, the reference power supply V is setFThe voltage value of (2) is 1.8V. If the power supply XVCC is less than 1.8V, the control voltage is low level voltage, the switch tube Q1 is switched off, and the output voltage V2-out is stopped to be provided; if the power source XVCC is greater than 1.8V, the control voltage is high, the switch Q1 is turned on, the output voltage V2-out starts to be provided, and the output voltage V2-out is substantially equal to or completely equal to the power source AVDD.
Then, when the system is turned on, if the power AVDD is boosted before the power XVCC, the power timing control circuit will stop providing the output voltage V2-out, i.e. the output voltage V2-out will lag behind the power XVCC; when the system is powered off, if the voltage of the power source XVCC drops before the voltage of the power source AVDD occurs, the power timing control circuit will stop providing the output voltage V2-out, i.e. the output voltage V2-out must also drop when the voltage of the power source XVCC drops.
As shown in FIG. 3, only when the voltage level of the power supply XVCC is high, the output voltage V2-out can be high, the output voltage V2-out is substantially equal to or completely equal to the power supply AVDD, and when the voltage level of the power supply XVCC is low, the output voltage V2-out must also be low, so that the power supply XVCC and the output voltage V2-out are provided to the source driver chip, which can satisfy the voltage required by the normal operation of the source driver chip, and the display problem caused by the timing error of the power supply XVCC and the power supply AVDD will not occur.
It should be understood that the present invention is not limited thereto, and the first power source V1 and the second power source V2 may also be two power sources with any other timing relation, for example, the first power source V1 and the second power source V2 may also be a low level signal VG L and a high level signal VGH for a gate driver in array (GIA) integrated circuit, and the high level signal VGH is boosted after the low level signal VG L.
Fig. 4 shows a schematic diagram of a display device according to an embodiment of the invention.
As shown in fig. 4, the display device 100 disclosed in the present embodiment includes: a power supply chip 101 for providing at least a power supply XVCC and a power supply AVDD; the power supply timing control circuit 110 is used for generating output voltage V2-out according to a power supply XVCC and a power supply AVDD; and a display panel for displaying a picture according to the image data.
In the embodiment, when the display device 100 is powered on, the power chip 101 provides the power XVCC and the power AVDD to the power timing control circuit 110, and the power timing control circuit 110 generates the output voltage V2-out and provides the power XVCC and the output voltage V2-out to the display panel to drive the source driver chip 130. Only when the power source XVCC is at a high level, the output voltage V2-out can be at a high level, and the magnitude of the output voltage V2-out is substantially equal to or completely equal to the magnitude of the power source AVDD, and when the power source XVCC is at a low level, the output voltage V2-out must also be changed to a low level, so that the power source XVCC and the output voltage V2-out are provided to the source driver chip, which can satisfy the voltage required by the normal operation thereof, and the display problem caused by the timing error of the power source XVCC and the power source AVDD cannot occur.
Taking the liquid crystal display device as an example, the display panel includes a timing controller (not shown), a source driving chip 130, and a gate driving chip 120. The timing controller transmits source driving data and gate driving data to the source driving chip 130 and the gate driving chip 120, respectively, according to the image data. The gate driving chip 120 is connected to the array substrate 140 through a plurality of gate lines, the source driving chip 130 is connected to the array substrate 140 through a plurality of source lines, the array substrate 140 is provided with a plurality of thin film transistors connected to the gate lines and the source lines and having drain electrodes, the drain electrodes of the thin film transistors are connected to pixel electrodes, the source driving chip 130 charges the pixel electrodes according to source driving data, so that liquid crystal molecules are changed in arrangement, the light transmittance of liquid crystal is changed, and the pixels are made to show different colors through the filtering effect of the filtering unit. The gate driving chip 120 sequentially supplies gate signals to the plurality of gate lines according to the gate driving data, thereby sequentially gating the pixel electrode connected to the source line on each gate line, so that the source driving chip 130 sequentially charges the corresponding pixel electrode through the source line.
In this embodiment, the internal structure of the display device is described as an example of a liquid crystal display device, but the display device of the present invention is not limited to the liquid crystal display device, and the display device may be a plasma display device, an L ED display device, an O L ED display device, or another type of display device, and the internal structure of the display device is not limited thereto.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A power timing control circuit, comprising:
the comparison unit is connected to a first power supply and used for providing control voltage according to a reference power supply and the first power supply; and
an output unit connected to the comparison unit and a second power supply for providing an output voltage according to the control voltage and the second power supply,
wherein the supply of the output voltage is stopped when the voltage value of the first power supply is less than the voltage value of the reference power supply,
and when the voltage value of the first power supply is larger than that of the reference power supply, starting to provide the output voltage.
2. The power supply timing control circuit according to claim 1, wherein the comparison unit includes:
a first resistor having a first terminal connected to the first power supply;
a second resistor having a first terminal connected to the reference power supply; and
a comparator having a positive input terminal connected to the second terminal of the first resistor, an inverted input terminal connected to the second terminal of the second resistor, a positive supply terminal connected to a high level voltage, a negative supply terminal connected to a low level voltage, and an output terminal supplying the control voltage,
wherein the control voltage is a low level voltage when the voltage value of the first power supply is less than the voltage value of the reference power supply,
when the voltage value of the first power supply is greater than the voltage value of the reference power supply, the control voltage is a high-level voltage.
3. The power supply timing control circuit according to claim 1, wherein the output unit includes:
a third resistor, a first end of the third resistor being connected to an output end of the comparison unit; and
a switch tube, a control end of the switch tube receiving the control voltage via the third resistor, a first path end connected to the second power supply, a second path end providing the output voltage,
wherein, when the control voltage is a low level voltage, the switch tube stops providing the output voltage,
when the control voltage is a high level voltage, the switch tube starts to provide the output voltage.
4. The power supply timing control circuit according to claim 3, wherein the output unit further includes:
a fourth resistor, wherein a first end of the fourth resistor is connected to the second path end of the switching tube, and a second end of the fourth resistor is connected to the reference ground.
5. The power supply timing control circuit according to claim 4, wherein the output unit further includes:
and a first end of the fifth resistor is connected to the second power supply, and a second end of the fifth resistor is connected to the first pass end of the switching tube.
6. The power timing control circuit of claim 3, wherein the switching transistor is an N-channel MOS field effect transistor.
7. The power timing control circuit of claim 1, wherein the voltage value of the output voltage is not greater than the voltage value of the second power supply.
8. A display device, comprising:
the power supply chip is used for providing a first power supply and a second power supply;
the power timing control circuit of any of claims 1 to 7, configured to generate an output voltage from the first power supply and the second power supply; and
a display panel for displaying a picture according to the image data,
wherein the power supply of the display panel is provided by at least the first power supply and the output voltage.
9. The display device according to claim 8, wherein the display panel comprises:
the grid driving chip is used for providing grid driving data;
the source driving chip is used for providing source driving data; and
an array substrate for displaying a picture according to the source driving data and the gate driving data,
the first power supply and the output voltage provide working voltage of the source driving chip.
10. The display device according to claim 8, wherein the display panel comprises an integrated gate driving circuit, and the first power supply and the output voltage respectively provide a low level signal and a high level signal of the integrated gate driving circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921693332.7U CN211181608U (en) | 2019-10-11 | 2019-10-11 | Power supply time sequence control circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921693332.7U CN211181608U (en) | 2019-10-11 | 2019-10-11 | Power supply time sequence control circuit and display device |
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| CN211181608U true CN211181608U (en) | 2020-08-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038364A (en) * | 2021-11-26 | 2022-02-11 | 京东方科技集团股份有限公司 | Display device, control method thereof and display system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114038364A (en) * | 2021-11-26 | 2022-02-11 | 京东方科技集团股份有限公司 | Display device, control method thereof and display system |
| CN114038364B (en) * | 2021-11-26 | 2023-12-12 | 京东方科技集团股份有限公司 | Display device, control method thereof and display system |
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