CN113539204A - Common voltage output circuit, printed circuit board and display device - Google Patents
Common voltage output circuit, printed circuit board and display device Download PDFInfo
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- CN113539204A CN113539204A CN202110793759.XA CN202110793759A CN113539204A CN 113539204 A CN113539204 A CN 113539204A CN 202110793759 A CN202110793759 A CN 202110793759A CN 113539204 A CN113539204 A CN 113539204A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
Abstract
The present disclosure provides a common voltage output circuit, including: a first control circuit having a first output terminal configured to output a first voltage signal through the first output terminal; a switch circuit having a control terminal, a common voltage input terminal and a common voltage output terminal, the control terminal being coupled to the first output terminal, the switch circuit being configured to make conduction between the common voltage input terminal and the common voltage output terminal in response to control of the first voltage signal; wherein a time when the first control circuit outputs the first voltage signal is later than a time when the common voltage is input to the common voltage input terminal. The embodiment of the disclosure also provides a printed circuit board, a display device and a public voltage output method.
Description
Technical Field
The present disclosure relates to the field of display, and in particular, to a common voltage output circuit, a printed circuit board, a display device, and a common voltage output method.
Background
A Liquid Crystal Display (LCD) is one of the most widely used displays. A liquid crystal display generally includes an array substrate, a pair of cell substrates, and a liquid crystal layer disposed between the two substrates, and realizes gray scale control by adjusting a state of the liquid crystal layer according to a magnitude of an electric field applied to the liquid crystal layer, thereby adjusting transmittance of light. However, the conventional liquid crystal display has a "white flash" problem after being turned on.
Disclosure of Invention
In a first aspect, an embodiment of the present disclosure provides a common voltage output circuit, including:
a first control circuit having a first output terminal configured to output a first voltage signal through the first output terminal;
a switch circuit having a control terminal, a common voltage input terminal and a common voltage output terminal, the control terminal being coupled to the first output terminal, the switch circuit being configured to make conduction between the common voltage input terminal and the common voltage output terminal in response to control of the first voltage signal;
wherein a time when the first control circuit outputs the first voltage signal is later than a time when the common voltage is input to the common voltage input terminal.
In some embodiments, the first control circuit further has a first input terminal, and the first control circuit is specifically configured to output the first voltage signal through the first output terminal according to the high-level voltage signal for gate driving during at least a part of a period in which the high-level voltage signal for gate driving is input to the first input terminal, and output a second voltage signal through the first output terminal at least when the high-level voltage signal for gate driving is not input to the first input terminal;
the switch circuit is further configured to open circuit between the common voltage input terminal and the common voltage output terminal under control of the second voltage signal.
In some embodiments, the first control circuit further has a third input terminal,
the common voltage output circuit further includes: a second control circuit having a second input and a second output, the second output coupled to the third input;
the second control circuit is configured to output a control signal through the second output terminal in response to control of the first enable signal input from the second input terminal;
the first control circuit is further configured to output the second voltage signal through the first output terminal in response to control of the control signal.
In some embodiments, a period in which the second control circuit outputs the control signal completely covers a period in which a gate-driving high-level voltage signal is not input to the first input terminal;
the outputting a second voltage signal through the first output terminal at least when the first input terminal is not inputted with the high-level voltage signal for driving the gate includes:
the first control circuit outputs the second voltage signal through the first output terminal in response to control of the control signal input from the third input terminal.
In some embodiments, the outputting a first voltage signal through the first output terminal according to the high-level voltage signal for gate driving during at least a part of the period in which the high-level voltage signal for gate driving is input to the first input terminal specifically includes:
the first control circuit outputs a first voltage signal through the first output terminal according to the gate driving high-level voltage signal in a period in which the first input terminal receives the gate driving high-level voltage signal and the third input terminal does not receive the second voltage signal.
In some embodiments, further comprising: a logic board having a third output coupled to the second input;
the logic board is configured to output the first enable signal through the third output terminal within a first preset time period after the logic board is powered on to control the second output terminal of the second control circuit to output the control signal, and output the second enable signal through the third output terminal after the logic board is powered on and the first preset time period passes to control the second output terminal of the second control circuit to stop outputting the control signal.
In some embodiments, a timer is disposed within the logic board, the timer configured to start timing when the logic board completes power-up;
the logic board body is configured to output the first enable signal through the third output terminal when the timing result of the timer is less than the first preset time duration, and output the second enable signal when the timing result of the timer reaches the first preset time duration.
In some embodiments, the second control circuit comprises: a first transistor;
the control electrode of the first transistor is connected with the second input end, the first electrode of the first transistor is connected with the second output end, and the second electrode of the second transistor is coupled with the first voltage end.
In some embodiments, the first control circuit comprises: a first resistor and a second resistor;
a first terminal of the first resistor is coupled to the first input terminal, and a second terminal of the first resistor is coupled to the first output terminal;
the first end of the second resistor is coupled to the first output end, and the second end of the second resistor is coupled to a second voltage end.
In some embodiments, the switching circuit comprises: a second transistor;
a control electrode of the second transistor is coupled to the control terminal, a first electrode of the second transistor is coupled to the common voltage input terminal, and a second electrode of the second transistor is coupled to the common voltage output terminal.
In some embodiments, the switching circuit further comprises: a third resistor connected in series between the second pole of the second transistor and the common voltage output terminal.
In some embodiments, further comprising: a fourth resistor, a fifth resistor, a first capacitor and/or a second capacitor;
a first terminal of the fourth resistor is coupled to the common voltage input terminal, and a second terminal of the fourth resistor is coupled to a third voltage terminal;
a first terminal of the fifth resistor is coupled to the common voltage output terminal, and a second terminal of the fifth resistor is coupled to a fourth voltage terminal;
a first end of the first capacitor is coupled to the first output end, and a second end of the first capacitor is coupled to a first voltage end;
the first end of the second capacitor is coupled with the common voltage output end, and the first end of the second capacitor is coupled with the fifth voltage end.
In a second aspect, embodiments of the present disclosure also provide a printed circuit board for a display device, including: the common voltage output circuit as provided in the above first aspect.
In some embodiments, the printed circuit board further comprises: a circuit board body;
each electrical element in the common voltage output circuit is fixed on the circuit board body, and a lead which is used for coupling different electrical elements in the common voltage output circuit is integrated in the circuit board body.
In some embodiments, the common voltage output circuit employs the common voltage output circuit of claim 2, the printed circuit board further comprising: the power management chip is fixed on the circuit board body;
the power management chip has a high-level voltage signal supply terminal for gate driving for providing a high-level voltage signal for gate driving and a common voltage supply terminal for providing a common voltage, the first input terminal is coupled to the high-level voltage signal supply terminal for gate driving, and the common voltage input terminal is coupled to the common voltage supply terminal.
In a third aspect, an embodiment of the present disclosure further provides a display device, including: a display panel and the printed circuit board as provided in the second aspect above, the printed circuit board providing a common voltage to the display panel.
In a fourth aspect, an embodiment of the present disclosure further provides a common voltage output method, where based on the common voltage output circuit provided in the first aspect, the common voltage output method includes:
the first control circuit outputs a first voltage signal through the first output end;
the switch circuit is responsive to control of the first voltage signal to conduct between the common voltage input terminal and the common voltage output terminal.
In some embodiments, before the step of the first control circuit outputting the first voltage signal through the first output terminal, the method further includes:
the first control circuit outputs a second voltage signal through the first output terminal at least when the first input terminal is not inputted with a high-level voltage signal for driving the grid electrode;
the switch circuit opens the circuit between the common voltage input terminal and the common voltage output terminal in response to the control of the second voltage signal;
the outputting, by the first control circuit, the first voltage signal through the first output terminal specifically includes:
the first control circuit outputs a first voltage signal through the first output terminal according to the gate driving high-level voltage signal during at least a part of a period in which the gate driving high-level voltage signal is input to the first input terminal.
In some embodiments, before the step of the first control circuit outputting the second voltage signal through the first output terminal, the method further includes:
the second control circuit outputs a control signal through the second output terminal in response to control of the first enable signal at least when a high-level voltage signal for gate driving is not input to the first input terminal;
the step of outputting the second voltage signal by the first control circuit through the first output terminal specifically includes:
the first control circuit outputs the second voltage signal through the first output terminal in response to control of the control signal.
In some embodiments, before the step of outputting a control signal through the second output terminal by the second control circuit in response to the control of the first enable signal, the method further comprises:
and the logic board outputs the first enabling signal through the third output end within a first preset time after the power-on is finished.
Before the step of outputting the first voltage signal through the first output terminal according to the high-level voltage signal for driving the gate by the first control circuit, the method further includes:
and the logic board outputs the second enable signal through the third output end after the power-on is completed and the first preset time is passed, so as to control the second output end of the second control circuit to stop outputting the control signal.
Drawings
FIG. 1 is a timing diagram illustrating signals loaded on a pixel electrode and a common electrode in a pixel region when a display device is turned on according to the related art;
fig. 2 is a schematic circuit structure diagram of a common voltage output circuit according to an embodiment of the disclosure;
FIG. 3 is a timing diagram of the gate driving high-level voltage signal supply terminal and the common voltage supply terminal of the power management chip according to the embodiment of the disclosure;
fig. 4 is a schematic circuit diagram of another circuit structure of the common voltage output circuit provided in the embodiment of the present disclosure;
FIG. 5 is a timing diagram illustrating the operation of the common voltage output circuit shown in FIG. 4;
fig. 6 is a schematic diagram of another circuit structure of the common voltage output circuit according to the embodiment of the disclosure;
fig. 7 is a schematic circuit diagram of a further circuit structure of the common voltage output circuit according to the embodiment of the disclosure;
FIG. 8 is a timing diagram illustrating operation of the common voltage output circuit shown in FIG. 7;
fig. 9 is a schematic circuit structure diagram of a printed circuit board for a display device according to an embodiment of the disclosure;
fig. 10 is a flowchart of a common voltage output method according to an embodiment of the disclosure;
FIG. 11 is a flow chart of another common voltage output method provided by the embodiments of the present disclosure;
FIG. 12 is a flowchart of another method for outputting a common voltage according to an embodiment of the present disclosure;
fig. 13 is a flowchart of another common voltage output method according to an embodiment of the disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present disclosure, a common voltage output circuit, a printed circuit board, a display device and a common voltage output method provided by the present disclosure are described in detail below with reference to the accompanying drawings.
The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. Likewise, the word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not restricted to physical or mechanical couplings, but can include electrical couplings, whether direct or indirect (e.g., other electronic components may also be present between two coupled components).
The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the drain and source of each transistor may be coupled in an interchangeable manner, and thus, the drain and source of each transistor in the embodiment of the present disclosure are not different. Here, only in order to distinguish two poles of the transistor except for the control electrode (i.e., the gate), one of the poles is referred to as a drain and the other pole is referred to as a source. The thin film transistor used in the embodiment of the present disclosure may be an N-type transistor or a P-type transistor. In the embodiment of the present disclosure, when an N-type thin film transistor is used, the first electrode thereof may be a source electrode, and the second electrode thereof may be a drain electrode. In the following embodiments, the thin film transistor is described as an N-type transistor.
In the present disclosure, an "active level signal" refers to a signal that can control the transistor to be turned on when the signal is input to the control electrode of the transistor, and an "inactive level signal" refers to a signal that can control the transistor to be turned off when the signal is input to the control electrode of the transistor. For an N-type transistor, a high level signal is an active level signal, and a low level signal is a non-active level signal; for a P-type transistor, the low level signal is an active level signal and the high level signal is an inactive level signal.
In the following description, the transistors will be described as N-type transistors as an example, and at this time, the active level signal refers to a high level signal and the inactive level signal refers to a low level signal. It is conceivable that when a P-type transistor is employed, the timing of the control signal needs to be adjusted accordingly. Specific details are not set forth herein but are intended to be within the scope of the present disclosure.
The image display principle of the liquid crystal display is as follows: the pixel voltage loaded in each pixel region is changed to change the electric fields at two sides of the liquid crystal molecules corresponding to the pixel region so as to control the torsion angle of the liquid crystal molecules, and further control the luminous flux of the pixel region. The pixel voltage of each pixel region is determined by the common voltage and the data voltage.
After the liquid crystal display is started up, the loading process of the common voltage and the pixel voltage in the display panel is as follows: the common voltage supply end of the power management chip outputs a common voltage, and the common voltage is transmitted to the common electrode through a common voltage line in the display panel; the source driving circuit provides corresponding data voltage to each data line according to display data input from the outside after power-on is completed, and the data voltage is written into a pixel electrode in the pixel area through a transistor in the pixel area.
Fig. 1 is a timing diagram of signals loaded on a pixel electrode and a common electrode in a pixel area when a display device is turned on in the related art, as shown in fig. 1, taking a certain pixel area in a display panel as an example, in a process of turning on the display device, a time when the common electrode E _ COM in the pixel area completes writing of a common voltage is prior to a time when the pixel electrode E _ PIX completes writing of a data voltage. Specifically, the common voltage Vcom is written first (indicated by a high-level state) at a stage t1 after power-on, and the data voltage Vdata is written (indicated by a high-level state) at a stage t2 after power-on.
At the stage t1, since the common voltage Vcom is completely written and the data voltage Vdata is not completely written (at this time, the voltage applied to the pixel electrode is generally the ground voltage, which is approximately 0V), the pixel voltage in the pixel region is not 0, and the liquid crystal molecules in the pixel region are twisted and exhibit the maximum gray scale. At stage t2, the data voltage is completely written, and the pixel region normally exhibits display gray scale.
As for the entire display device, the display device presents a full white screen at stage t1 and a normal display screen at stage t 2. Therefore, the display device related to the related art presents a full white picture in a short time after being started, and then presents a normal display picture, namely, the problem of 'flashing white' when being started exists.
The embodiment of the present disclosure provides a common voltage output circuit, which can delay output of a common voltage supplied to a display panel, and can improve or even completely solve the problem of "white flash" of a display device after power-on in the related art to a certain extent.
Fig. 2 is a schematic circuit structure diagram of a common voltage output circuit provided in the embodiment of the present disclosure, and as shown in fig. 2, the common voltage output circuit includes: a first control circuit 1 and a switch circuit 2; the first control circuit 1 has a first output terminal OUT1, the first control circuit 1 is configured to output a first voltage signal through the first output terminal OUT 1; the switch circuit 2 has a control terminal IN _ CT, a common voltage input terminal IN _ COM, and a common voltage output terminal OUT _ COM, the control terminal IN _ CT is coupled to the first output terminal OUT1, the switch circuit 2 is configured to make conduction between the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM IN response to control of the first voltage signal; the timing at which the first control circuit 1 outputs the first voltage signal is later than the timing at which the common voltage is input to the common voltage input terminal IN _ COM.
The "time when the common voltage is input to the common voltage input terminal IN _ COM" refers to a time when the common voltage is written into the common voltage input terminal IN _ COM by the common voltage supply terminal of the power management chip after the power management chip is turned on.
IN the disclosed embodiment, the switch circuit 2 is responsive to the control of the first voltage signal to make conduction between the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM, and the first control circuit 1 outputs the first voltage signal at a time later than a time at which the common voltage is input to the common voltage input terminal IN _ COM, that is, at a time when conduction between the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM is started later than a time at which the common voltage is input to the common voltage input terminal IN _ COM, that is, at a time when the common voltage output terminal OUT _ COM supplies the common voltage to the display panel later than a time at which the common voltage supply terminal of the power management chip writes the common voltage to the common voltage input terminal IN _ COM; therefore, the technical scheme of the disclosure can realize delayed output of the common voltage supplied to the display panel.
In practical applications, by delaying the output of the common voltage supplied to the display panel, the duration of the t1 stage in fig. 1 can be shortened or even completely eliminated, so that the duration of the display device displaying a full white picture after power-on is shortened or even the full white picture is not displayed, thereby achieving a purpose of improving or even completely solving the problem of the display device appearing "flash white" after power-on in the related art to a certain extent.
With continued reference to fig. 2, IN some embodiments, the first control circuit 1 further has a first input terminal IN1, the first control circuit 1 is specifically configured to output a first voltage signal according to the high-level voltage signal for gate driving through the first output terminal OUT1 during at least a portion of the period when the high-level voltage signal for gate driving is input to the first input terminal IN1, and to output a second voltage signal through the first output terminal OUT1 at least when the high-level voltage signal for gate driving is not input to the first input terminal IN 1; the switch circuit 2 is further configured to open the circuit between the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM under the control of the second voltage signal.
Fig. 3 is a timing diagram of the gate driving high-level voltage signal supply terminal and the common voltage supply terminal of the power management chip in the embodiment of the disclosure, as shown in fig. 3, in the embodiment of the disclosure, when the display device is turned on, the timing at which the gate driving high-level voltage signal supply terminal outputs the SP _ VGH gate driving high-level voltage is later than the timing at which the common voltage supply terminal SP _ COM outputs the common voltage.
The high-level voltage signal for driving the gate is a high-level voltage signal (generally denoted as VGH) provided by the power management chip to the clock generation circuit; the clock generating circuit generates a clock signal (generally denoted as CLK) for driving the gate based on the high-level voltage signal for driving the gate and a low-level voltage signal (generally denoted as VGL) for driving the gate provided by the power management chip, the clock signal for driving the gate being provided to the shift register, the shift register outputting the clock signal for driving the gate through a signal output terminal to be used as a gate driving signal (also referred to as a gate scanning signal), and in the general display panel, VGH is a signal for last power-on of the display panel and is later than the power-on time of the common voltage signal, and a preferable delay effect can be obtained for outputting the common voltage.
To facilitate a better understanding of the technical aspects of the present disclosure by those skilled in the art, the following detailed description is given with reference to specific examples.
Fig. 4 is a schematic circuit structure diagram of another common voltage output circuit provided in an embodiment of the present disclosure, and as shown in fig. 4, the common voltage output circuit shown in fig. 4 is a specific alternative implementation based on the common voltage output circuit shown in fig. 2.
In some embodiments, the first control circuit 1 includes: a first resistor R1 and a second resistor R2; a first terminal of the first resistor R1 is coupled to the first input terminal IN1, and a second terminal of the first resistor R1 is coupled to the first output terminal OUT 1; a first terminal of the second resistor R2 is coupled to the first output terminal OUT1, and a second terminal of the second resistor R2 is coupled to a second voltage terminal.
The first resistor R1 and the second resistor R2 can divide the voltage (i.e., the high level voltage VGH) inputted from the first input terminal, so that the resistances of R1 and R2 can be designed according to the magnitude of VGH and the specific voltage of the first voltage signal to be outputted; meanwhile, the current in the circuit is ensured to be appropriate during the voltage division process of the first resistor R1 and the second resistor R2.
In some embodiments, the resistance of the first resistor R1 ranges from 5k Ω to 50k Ω, and the resistance of the second resistor R1 ranges from 5k Ω to 50k Ω. As a specific example, the resistance value of the first resistor R1 is 20k Ω, and the resistance value of the second resistor R2 is 10k Ω.
In some embodiments, the switching circuit 2 includes: a second transistor M2; a control electrode of the second transistor M2 is coupled to the control terminal IN _ CT, a first electrode of the second transistor M2 is coupled to the common voltage input terminal IN _ COM, and a second electrode of the second transistor M2 is coupled to the common voltage output terminal OUT _ COM.
In the embodiment of the disclosure, the first voltage terminal and the second voltage terminal are both low level voltage terminals (providing a low level voltage signal, such as the ground voltage VSS, the VSS voltage is about OV), and the voltage level of the high level voltage signal for driving the gate is VGH, for example, which is described in detail. At this time, the first voltage signal is a high level voltage signal, and the second voltage signal is a low level voltage signal.
Fig. 5 is an operation timing diagram of the common voltage output circuit shown IN fig. 4, as shown IN fig. 5, IN a stage s1 after power-on, the common voltage input terminal IN _ COM is inputted with the common voltage, and the common voltage input terminal IN _ COM is IN a high state; the first input terminal IN1 is not inputted with a high-level voltage signal for driving the gate and is IN a floating state, the ground voltage VSS is written into the first output terminal OUT1 through the second resistor R2, the first output terminal OUT1 is IN a low-level state, that is, the first output terminal OUT1 outputs a second voltage signal; at this time, the gate-source voltage of the second transistor M2 is less than 0, the second transistor M2 is turned off, and the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM are disconnected, that is, the common voltage is input at the common voltage input terminal IN _ COM, but the common voltage is not output at the common voltage output terminal OUT _ COM.
At a stage s2 after the power-on, a common voltage is input to the common voltage input terminal IN _ COM, and the common voltage input terminal IN _ COM is IN a high level state; a high-level voltage signal for driving the gate is input to the first input terminal IN1, and the first input terminal IN1 is IN a high-level state; at this time, through the voltage division of the first resistor R1 and the second resistor R2, the voltage at the first output terminal OUT1 is approximately equal to VGH × R1/(R1+ R2), where R1 and R2 are resistance values of the first resistor R1 and the second resistor R2, respectively, and the first output is in a high state, that is, the first output terminal OUT1 outputs a first voltage signal; at this time, the gate-source voltage of the second transistor M2 is greater than 0, the second transistor M2 is turned on, the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM are turned on, and the common voltage input at the common voltage input terminal IN _ COM is written to the common voltage output terminal OUT _ COM, that is, the common voltage output terminal OUT _ COM outputs the common voltage.
As can be seen from this, in the embodiment of the present disclosure, the time when the common voltage output terminal OUT _ COM outputs the common voltage may substantially coincide with the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, so as to achieve the purpose of delaying and outputting the common voltage supplied to the display panel.
Fig. 6 is a schematic diagram of another circuit structure of the common voltage output circuit provided in the embodiment of the present disclosure, and as shown in fig. 6, the common voltage output circuit provided in this embodiment includes not only the first control circuit 1 and the switch circuit 2 in the previous embodiment, but also the second control circuit 3.
Wherein the first control circuit 1 further has a third input IN 3; the second control circuit 3 has a second input terminal IN2 and a second output terminal OUT2, the second output terminal OUT2 being coupled to the third input terminal IN 3; the second control circuit 3 is configured to output a control signal through the second output terminal OUT2 IN response to control of the first enable signal inputted from the second input terminal IN 2; accordingly, the first control circuit 1 is further configured to output the second voltage signal through the first output terminal OUT1 in response to the control of the control signal.
IN some embodiments, the period IN which the second control circuit 3 outputs the control signal completely covers the period IN which the gate-driving high-level voltage signal is not input to the first input terminal IN 1. The aforementioned outputting, by the first control circuit 1, the second voltage signal through the first output terminal OUT1 when the high-level voltage signal for gate driving is not input to the first input terminal IN1 specifically includes: the first control circuit 1 outputs the second voltage signal through the first output terminal OUT1 IN response to the control of the control signal input from the third input terminal IN 3.
IN some embodiments, the outputting of the first voltage signal by the first control circuit 1 through the first output terminal OUT1 according to the high-level voltage signal for driving the gate during at least a part of the period when the high-level voltage signal for driving the gate is inputted to the first input terminal IN1 specifically includes: the first control circuit 1 outputs the first voltage signal through the first output terminal OUT1 according to the high-level voltage signal for gate driving IN a period IN which the first input terminal IN1 is inputted with the high-level voltage signal for gate driving and the third input terminal IN3 does not receive the second voltage signal.
IN the embodiment of the present disclosure, by providing the second control circuit 3 and outputting the control signal by the second control circuit 3, and accordingly outputting the second voltage signal by the first output terminal OUT1 IN response to the control of the control signal inputted by the third input terminal IN3 by the first control circuit 1, it is possible to realize that the timing at which the common voltage output terminal OUT _ COM outputs the common voltage can be located after the timing at which the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, and that the timing at which the common voltage output terminal OUT _ COM outputs the common voltage can be accurately controlled. Which will be described in detail with reference to specific embodiments.
In some embodiments, the common voltage output circuit further comprises: a logic board 4 (also referred to as a screen driving board, a central control board or a TCON board); the logic board 4 has a third output OUT3, the third output OUT3 being coupled to the second input IN 2; the logic board 4 is configured to output the first enable signal through the third output terminal to control the second output terminal OUT2 of the second control circuit 3 to output the control signal within a first preset time period after the logic board 4 completes power-on (the end time of the first preset time period is not earlier than the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, and generally, the end time of the first preset time period is set to be after the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage), and output the second enable signal through the third output terminal to control the second output terminal OUT2 of the second control circuit 3 to stop outputting the control signal after the logic board 4 completes power-on and passes through the first preset time period.
In some embodiments, a timer (not shown) is disposed within the logic board 4, the timer being configured to start timing when the logic board 4 completes powering up; the logic board 4 is specifically configured to output the first enable signal through the third output terminal OUT3 when the timing result of the timer is less than the first preset time period, and output the second enable signal when the timing result of the timer reaches the first preset time period.
Fig. 7 is a schematic diagram of another circuit structure of the common voltage output circuit according to the embodiment of the disclosure, as shown in fig. 7, in some embodiments, specific circuit structures of the first control circuit 1 and the switch circuit 2 may be as shown in fig. 4, and are not described herein again.
In some embodiments, the second control circuit 3 includes: a first transistor M1; the control electrode of the first transistor M1 is connected to the second input terminal IN2, the first electrode of the first transistor M1 is connected to the second output terminal OUT2, and the second electrode of the second transistor M2 is coupled to the first voltage terminal.
In the embodiment of the disclosure, the first voltage terminal and the second voltage terminal are both low-level voltage terminals (providing low-level voltage signals, such as the ground voltage VSS, and the VSS voltage is about OV), the voltage level of the high-level voltage signal for driving the gate is VGH, the ending time of the first preset time period is after the time when the high-level voltage signal for driving the gate is output by the gate driving high-level voltage signal supply terminal of the power management chip, the first enable signal is a high-level voltage signal, the second enable signal is a low-level voltage signal, and the control signal is a low-level voltage signal.
Fig. 8 is an operation timing diagram of the common voltage output circuit shown in fig. 7, as shown in fig. 8, in a stage s1 after the power-on, when the timing result of the timer is less than the first preset time period, the logic board 4 outputs the first enable signal, that is, the logic board 4 outputs the high level voltage signal; a common voltage is input to the common voltage input end IN _ COM, and the common voltage input end IN _ COM is IN a high level state; the first input terminal IN1 is not inputted with a high-level voltage signal for gate driving and is IN a floating state.
Since the logic board 4 outputs the high-level voltage signal, the first transistor M1 is IN a conducting state, the ground voltage VSS is written into the third input terminal IN3 through the first transistor M1, and accordingly the first output terminal OUT1 is IN a low-level state, i.e., the first output terminal OUT1 outputs the second voltage signal; at this time, the gate-source voltage of the second transistor M2 is less than 0, the second transistor M2 is turned off, and the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM are disconnected, that is, the common voltage is input at the common voltage input terminal IN _ COM, but the common voltage is not output at the common voltage output terminal OUT _ COM.
At a stage s2_1 after the power-on, when the timing result of the timer is less than a first preset time length, the logic board 4 outputs a first enable signal, that is, the logic board 4 outputs a high-level voltage signal; the common voltage input terminal IN _ COM is inputted with a common voltage, the common voltage input terminal IN _ COM is IN a high level state, the first input terminal IN1 is inputted with a high level voltage signal for gate driving, and the first input terminal IN1 is IN a high level state.
Since the logic board 4 outputs the high level voltage signal, the first transistor M1 is in a conducting state, and the ground voltage VSS is written to the second output terminal OUT2 through the first transistor M1, i.e., the second control transistor outputs the control signal; accordingly, the control signal is inputted to the third input terminal IN3, and the first output terminal OUT1 is IN a low state, i.e., the first output terminal OUT1 outputs the second voltage signal. At this time, the gate-source voltage of the second transistor M2 is less than 0, the second transistor M2 is turned off, and the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM are disconnected, that is, the common voltage is input to the common voltage input terminal IN _ COM and the high-level voltage signal for gate driving is input to the first input terminal IN1, but the common voltage is not output from the common voltage output terminal OUT _ COM.
At a stage s2_2 after the power-on, when the timing result of the timer is greater than or equal to the first preset duration, the logic board 4 outputs the second enable signal, that is, the logic board 4 outputs the low-level voltage signal; the common voltage input terminal IN _ COM is inputted with a common voltage, the common voltage input terminal IN _ COM is IN a high level state, the first input terminal IN1 is inputted with a high level voltage signal for gate driving, and the first input terminal IN1 is IN a high level state.
Since the logic board 4 outputs the low level voltage signal, the first transistor M1 is IN the off state, and the second control circuit 3 stops outputting the control signal, i.e., the third input terminal IN3 does not input the control signal. At this time, the first resistor R1 and the second resistor R2 divide the gate driving high level voltage signal VGH, the voltage at the first output terminal OUT1 is approximately equal to VGH × R1/(R1+ R2), where R1 and R2 are resistance values of the first resistor R1 and the second resistor R2, respectively, and the first output is in a high level state, that is, the first output terminal OUT1 outputs the first voltage signal; at this time, the gate-source voltage of the second transistor M2 is greater than 0, the second transistor M2 is turned on, the common voltage input terminal IN _ COM and the common voltage output terminal OUT _ COM are turned on, and the common voltage input at the common voltage input terminal IN _ COM is written to the common voltage output terminal OUT _ COM, that is, the common voltage output terminal OUT _ COM outputs the common voltage.
The sum of the time lengths of the above-mentioned phase s1 and the phase s2_1 is equal to the first preset time length, and the time length of the phase s2_1 represents the time length in which the common voltage is further delayed for output after the gate driving high-level voltage is output from the gate driving high-level voltage signal supply terminal of the power management chip. As can be seen from this, by providing the second control circuit 3, not only can the time when the common voltage output terminal OUT _ COM outputs the common voltage be located after the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, but also the time when the common voltage output terminal OUT _ COM outputs the common voltage can be precisely controlled, so as to achieve precise control of the delayed output of the common voltage.
In some embodiments, the switching circuit 2 further comprises: a third resistor R3 and a third resistor R3 are connected in series between the second pole of the second transistor M2 and the common voltage output terminal OUT _ COM. The third resistor R3 is used to control the charging current between the second pole of the second transistor M2 and the common voltage output terminal OUT _ COM, so that the electrical components can be effectively prevented from being damaged due to the excessive charging current. The resistance of the third resistor R3 can be designed in advance according to actual needs.
With continued reference to fig. 4 and 7, in some embodiments, the common voltage output circuit further comprises: a first capacitance C1; the first terminal of the first capacitor C1 is coupled to the first output terminal OUT1, and the second terminal of the first capacitor C1 is coupled to the first voltage terminal.
In some embodiments, the common voltage output circuit further comprises: a second capacitance C2; the first terminal of the second capacitor C2 is coupled to the common voltage output terminal OUT _ COM, and the first terminal of the second capacitor C2 is coupled to the fifth voltage terminal.
In the embodiment of the disclosure, by coupling a capacitor to the first output terminal OUT1 and the common voltage output terminal OUT _ COM, the capacitor can perform a function of filtering and stabilizing voltage of the corresponding output terminal, so as to improve stability of the signal output by the corresponding output terminal.
With continued reference to fig. 4 and 7, in some embodiments, the common voltage output circuit further comprises: a fourth resistor R4; a first terminal of the fourth resistor R4 is coupled to the common voltage input IN _ COM, and a second terminal of the fourth resistor R4 is coupled to the third voltage terminal.
In some embodiments, the common voltage output circuit further comprises: a fifth resistor R5; a first terminal of the fifth resistor R5 is coupled to the common voltage output terminal OUT _ COM, and a second terminal of the fifth resistor R5 is coupled to the fourth voltage terminal.
The third voltage terminal to the fifth voltage terminal can be ground voltage terminals, and the ground voltage terminals provide a ground voltage VSS. When the display device is IN a shutdown state, the common voltage input end IN _ COM may be discharged through the fourth resistor R4 to enable the voltage at the common voltage input end IN _ COM to drop from the common voltage to the ground voltage, and the common voltage output end OUT _ COM may be discharged through the fifth transistor to enable the voltage at the common voltage output end OUT _ COM to drop from the common voltage to the ground voltage, so as to avoid that the common voltage input end IN _ COM and the common voltage output end OUT _ COM are IN a high-voltage state when the display device is IN the shutdown state, which is beneficial to prolonging the service life of the common voltage output circuit.
In summary, the common voltage output circuit provided by the embodiments of the present disclosure can delay outputting the common voltage supplied to the display panel, and can improve or even completely solve the problem of "white flash" of the display device after the display device is turned on in the related art to a certain extent.
Based on the same inventive concept, the embodiment of the disclosure also provides a printed circuit board for a display device. Fig. 9 is a schematic Circuit structure diagram of a Printed Circuit board for a display device according to an embodiment of the present disclosure, and as shown in fig. 9, the Printed Circuit Board (PCB) for a display device includes the common voltage output Circuit 5 provided in the previous embodiment; for a detailed description of the common voltage output circuit 5, reference may be made to the contents of the foregoing embodiments, and details are not described here.
In some embodiments, the printed circuit board further comprises: a circuit board body 6; the electrical components (e.g., transistors, resistors, capacitors, etc.) in the common voltage output circuit 5 are fixed (e.g., fixed by a bonding process) on the circuit board body 6, and the wires for coupling the different electrical components in the common voltage output circuit 5 are integrated in the circuit board body 6.
In some embodiments, the printed circuit board further comprises: the power management chip 7, the power management chip 7 is fixed on the circuit board body 6; the power management chip 7 has a high-level voltage signal supply terminal for gate driving for supplying a high-level voltage signal for gate driving and a common voltage supply terminal for supplying a common voltage, a first input terminal coupled to the high-level voltage signal supply terminal for gate driving, and a common voltage input terminal coupled to the common voltage supply terminal.
Based on the same inventive concept, the embodiment of the present disclosure further provides a display device, including: a display panel and a printed circuit board as provided in the previous embodiments, wherein the printed circuit board is operable to provide a common voltage to the display panel.
The display device provided by the embodiment of the disclosure may be: the display device comprises any product or component with a display function, such as a liquid crystal display screen, a wearable device, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present disclosure.
Based on the same inventive concept, the embodiment of the disclosure also provides a common voltage output method. Fig. 10 is a flowchart of a common voltage output method provided in an embodiment of the present disclosure, and as shown in fig. 10, the common voltage output method is based on the common voltage output circuit provided in the previous embodiment, and the common voltage output circuit includes:
step S101, the first control circuit outputs a first voltage signal through a first output end.
And step S102, the switch circuit enables the common voltage input end and the common voltage output end to be conducted in response to the control of the first voltage signal.
In the disclosed embodiment, the switch circuit makes the common voltage input end and the common voltage output end conduct in response to the control of the first voltage signal, and the time when the first control circuit outputs the first voltage signal is later than the time when the common voltage is input to the common voltage input end, that is, the time when the conduction between the common voltage input end and the common voltage output end is started is later than the time when the common voltage is input to the common voltage input end, that is, the time when the common voltage output end supplies the common voltage to the display panel is later than the time when the common voltage supply end of the power management chip writes the common voltage to the common voltage input end; therefore, the technical scheme of the disclosure can realize delayed output of the common voltage supplied to the display panel.
Fig. 11 is a flowchart of another common voltage output method provided in the embodiment of the present disclosure, and as shown in fig. 11, the common voltage output method includes:
in step S201, at least when the first input terminal does not input the high level voltage signal for driving the gate, the first control circuit outputs the second voltage signal through the first output terminal.
In step S202, the switch circuit opens the circuit between the common voltage input terminal and the common voltage output terminal in response to the control of the second voltage signal.
In step S203, during at least a portion of the period when the high-level voltage signal for gate driving is input to the first input terminal, the first control circuit outputs the first voltage signal through the first output terminal according to the high-level voltage signal for gate driving.
And step S204, the switch circuit enables the common voltage input end and the common voltage output end to be conducted in response to the control of the first voltage signal.
For the specific description of step S201 to step S204, refer to the content in the foregoing embodiments, and are not described herein again.
In the embodiment of the present disclosure, the time when the common voltage output terminal outputs the common voltage may be substantially the same as the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, or the time when the common voltage output terminal outputs the common voltage may be later than the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, so as to achieve the purpose of delaying the output of the common voltage supplied to the display panel.
Fig. 12 is a flowchart of another common voltage output method provided by an embodiment of the present disclosure, and as shown in fig. 12, the common voltage output method is based on the common voltage output circuit shown in fig. 6 or fig. 7, and the common voltage output method includes:
in step S301, the second control circuit outputs a control signal through the second output terminal in response to the control of the first enable signal at least when the high-level voltage signal for driving the gate is not input to the first input terminal.
In step S302, the first control circuit outputs a second voltage signal through the first output terminal in response to the control of the control signal.
In step S303, the switching circuit opens the circuit between the common voltage input terminal and the common voltage output terminal in response to the control of the second voltage signal.
In step S304, during at least a portion of the period when the high-level voltage signal for gate driving is input to the first input terminal, the first control circuit outputs the first voltage signal through the first output terminal according to the high-level voltage signal for gate driving.
In step S305, the switch circuit makes conduction between the common voltage input terminal and the common voltage output terminal in response to the control of the first voltage signal.
For the specific description of step S301 to step S305, refer to the content in the foregoing embodiments, and are not described herein again.
In the embodiment of the present disclosure, the time when the common voltage output terminal outputs the common voltage may be substantially the same as the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, or the time when the common voltage output terminal outputs the common voltage may be later than the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, so as to achieve the purpose of delaying the output of the common voltage supplied to the display panel.
Fig. 13 is a flowchart of still another common voltage output method provided in an embodiment of the present disclosure, and as shown in fig. 13, the common voltage output method is based on the common voltage output circuit shown in fig. 6 or fig. 7, and the common voltage output method includes:
step S401, the logic board outputs a first enable signal through the third output terminal within a first preset time after the power-on is completed.
In step S402, the second control circuit outputs a control signal through the second output terminal in response to the control of the first enable signal.
In step S403, the first control circuit outputs the second voltage signal through the first output terminal in response to the control of the control signal.
And S404, the switch circuit responds to the control of the second voltage signal to make the circuit between the common voltage input end and the common voltage output end be disconnected.
Step S405, after the logic board is powered on and the first preset time period passes, the logic board outputs a second enable signal through the third output terminal to control the second output terminal of the second control circuit to stop outputting the control signal.
In step S406, the first control circuit outputs a first voltage signal through the first output terminal according to the high-level voltage signal for driving the gate.
In step S407, the switch circuit makes conduction between the common voltage input terminal and the common voltage output terminal in response to the control of the first voltage signal.
For the specific description of step S401 to step S407, refer to the content in the foregoing embodiments, and are not described herein again.
In the embodiment of the present disclosure, the time when the common voltage output terminal outputs the common voltage may be substantially the same as the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, or the time when the common voltage output terminal outputs the common voltage may be later than the time when the gate driving high-level voltage signal supply terminal of the power management chip outputs the gate driving high-level voltage, so as to achieve the purpose of delaying the output of the common voltage supplied to the display panel; the specific output time of the common voltage can be accurately controlled through a first preset time length preset in the logic board.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (20)
1. A common voltage output circuit, comprising:
a first control circuit having a first output terminal configured to output a first voltage signal through the first output terminal;
a switch circuit having a control terminal, a common voltage input terminal and a common voltage output terminal, the control terminal being coupled to the first output terminal, the switch circuit being configured to make conduction between the common voltage input terminal and the common voltage output terminal in response to control of the first voltage signal;
wherein a time when the first control circuit outputs the first voltage signal is later than a time when the common voltage is input to the common voltage input terminal.
2. The common voltage output circuit according to claim 1, wherein;
the first control circuit further has a first input terminal, and is specifically configured to output the first voltage signal through the first output terminal according to the high-level voltage signal for gate driving during at least a part of a period in which the high-level voltage signal for gate driving is input to the first input terminal, and to output a second voltage signal through the first output terminal at least when the high-level voltage signal for gate driving is not input to the first input terminal;
the switch circuit is further configured to open circuit between the common voltage input terminal and the common voltage output terminal under control of the second voltage signal.
3. The common voltage output circuit of claim 2, wherein said first control circuit further has a third input terminal,
the common voltage output circuit further includes: a second control circuit having a second input and a second output, the second output coupled to the third input;
the second control circuit is configured to output a control signal through the second output terminal in response to control of the first enable signal input from the second input terminal;
the first control circuit is further configured to output the second voltage signal through the first output terminal in response to control of the control signal.
4. The common voltage output circuit according to claim 3, wherein a period in which the second control circuit outputs the control signal completely covers a period in which a high-level voltage signal for gate driving is not input to the first input terminal;
the outputting a second voltage signal through the first output terminal at least when the first input terminal is not inputted with the high-level voltage signal for driving the gate includes:
the first control circuit outputs the second voltage signal through the first output terminal in response to control of the control signal input from the third input terminal.
5. The common voltage output circuit according to claim 3, wherein the outputting a first voltage signal via the first output terminal according to the high level voltage signal for gate driving during at least a part of the period in which the high level voltage signal for gate driving is inputted to the first input terminal, comprises:
the first control circuit outputs a first voltage signal through the first output terminal according to the gate driving high-level voltage signal in a period in which the first input terminal receives the gate driving high-level voltage signal and the third input terminal does not receive the second voltage signal.
6. The common voltage output circuit according to claim 3, further comprising: a logic board having a third output coupled to the second input;
the logic board is configured to output the first enable signal through the third output terminal within a first preset time period after the logic board is powered on to control the second output terminal of the second control circuit to output the control signal, and output the second enable signal through the third output terminal after the logic board is powered on and the first preset time period passes to control the second output terminal of the second control circuit to stop outputting the control signal.
7. The common voltage output circuit of claim 6, wherein a timer is disposed within the logic board, the timer configured to start timing when the logic board completes power-up;
the logic board body is configured to output the first enable signal through the third output terminal when the timing result of the timer is less than the first preset time duration, and output the second enable signal when the timing result of the timer reaches the first preset time duration.
8. The common voltage output circuit according to claim 3, wherein the second control circuit comprises: a first transistor;
the control electrode of the first transistor is connected with the second input end, the first electrode of the first transistor is connected with the second output end, and the second electrode of the second transistor is coupled with the first voltage end.
9. The common voltage output circuit according to any one of claims 1 to 8, wherein the first control circuit comprises: a first resistor and a second resistor;
a first terminal of the first resistor is coupled to the first input terminal, and a second terminal of the first resistor is coupled to the first output terminal;
the first end of the second resistor is coupled to the first output end, and the second end of the second resistor is coupled to a second voltage end.
10. The common voltage output circuit according to any one of claims 1 to 8, wherein the switching circuit comprises: a second transistor;
a control electrode of the second transistor is coupled to the control terminal, a first electrode of the second transistor is coupled to the common voltage input terminal, and a second electrode of the second transistor is coupled to the common voltage output terminal.
11. The common voltage output circuit according to claim 10, wherein the switching circuit further comprises: a third resistor connected in series between the second pole of the second transistor and the common voltage output terminal.
12. The common voltage output circuit according to any one of claims 1 to 8, further comprising: a fourth resistor, a fifth resistor, a first capacitor and/or a second capacitor;
a first terminal of the fourth resistor is coupled to the common voltage input terminal, and a second terminal of the fourth resistor is coupled to a third voltage terminal;
a first terminal of the fifth resistor is coupled to the common voltage output terminal, and a second terminal of the fifth resistor is coupled to a fourth voltage terminal;
a first end of the first capacitor is coupled to the first output end, and a second end of the first capacitor is coupled to a first voltage end;
the first end of the second capacitor is coupled with the common voltage output end, and the first end of the second capacitor is coupled with the fifth voltage end.
13. A printed circuit board for a display device, comprising: a common voltage output circuit as claimed in any one of claims 1 to 12.
14. The printed circuit board of claim 13, further comprising: a circuit board body;
each electrical element in the common voltage output circuit is fixed on the circuit board body, and a lead which is used for coupling different electrical elements in the common voltage output circuit is integrated in the circuit board body.
15. The printed circuit board of claim 14, wherein the common voltage output circuit employs the common voltage output circuit of claim 2, the printed circuit board further comprising: the power management chip is fixed on the circuit board body;
the power management chip has a high-level voltage signal supply terminal for gate driving for providing a high-level voltage signal for gate driving and a common voltage supply terminal for providing a common voltage, the first input terminal is coupled to the high-level voltage signal supply terminal for gate driving, and the common voltage input terminal is coupled to the common voltage supply terminal.
16. A display device, comprising: a display panel and a printed circuit board as claimed in any one of claims 13 to 15, the printed circuit board providing a common voltage to the display panel.
17. A common voltage output method based on the common voltage output circuit according to any one of claims 1 to 12, comprising:
the first control circuit outputs a first voltage signal through the first output end;
the switch circuit is responsive to control of the first voltage signal to conduct between the common voltage input terminal and the common voltage output terminal.
18. The common voltage output method according to claim 17, wherein the common voltage output circuit employs the common voltage output circuit according to any one of claims 2 to 8;
before the step of the first control circuit outputting the first voltage signal through the first output terminal, the method further comprises:
the first control circuit outputs a second voltage signal through the first output terminal at least when the first input terminal is not inputted with a high-level voltage signal for driving the grid electrode;
the switch circuit opens the circuit between the common voltage input terminal and the common voltage output terminal in response to the control of the second voltage signal;
the outputting, by the first control circuit, the first voltage signal through the first output terminal specifically includes:
the first control circuit outputs a first voltage signal through the first output terminal according to the gate driving high-level voltage signal during at least a part of a period in which the gate driving high-level voltage signal is input to the first input terminal.
19. The common voltage output method according to claim 18, wherein the common voltage output circuit is the common voltage output circuit according to any one of claims 3 to 8;
before the step of the first control circuit outputting the second voltage signal through the first output terminal, the method further comprises:
the second control circuit outputs a control signal through the second output terminal in response to control of the first enable signal at least when a high-level voltage signal for gate driving is not input to the first input terminal;
the step of outputting the second voltage signal by the first control circuit through the first output terminal specifically includes:
the first control circuit outputs the second voltage signal through the first output terminal in response to control of the control signal.
20. The common voltage output method according to claim 19, wherein the common voltage output circuit is the common voltage output circuit in claim 6 or 7;
before the step of outputting a control signal through the second output terminal by the second control circuit in response to the control of the first enable signal, the method further comprises:
and the logic board outputs the first enabling signal through the third output end within a first preset time after the power-on is finished.
Before the step of outputting the first voltage signal through the first output terminal according to the high-level voltage signal for driving the gate by the first control circuit, the method further includes:
and the logic board outputs the second enable signal through the third output end after the power-on is completed and the first preset time is passed, so as to control the second output end of the second control circuit to stop outputting the control signal.
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| CN114495854A (en) * | 2021-12-28 | 2022-05-13 | 绵阳惠科光电科技有限公司 | Driving circuit, driving method and display device |
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| CN109559702A (en) * | 2019-01-15 | 2019-04-02 | 合肥鑫晟光电科技有限公司 | Public electrode voltages control circuit and driving method, display panel |
| CN111477181A (en) * | 2020-05-22 | 2020-07-31 | 京东方科技集团股份有限公司 | Gate driving circuit, display substrate, display device and gate driving method |
| CN213025343U (en) * | 2020-09-29 | 2021-04-20 | 昆山龙腾光电股份有限公司 | Time sequence control circuit and display device |
| CN213583064U (en) * | 2020-11-17 | 2021-06-29 | 昆山龙腾光电股份有限公司 | Regulating circuit and liquid crystal display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114495854A (en) * | 2021-12-28 | 2022-05-13 | 绵阳惠科光电科技有限公司 | Driving circuit, driving method and display device |
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