CN204632309U - A kind of display panel and display device - Google Patents
A kind of display panel and display device Download PDFInfo
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- CN204632309U CN204632309U CN201520258216.8U CN201520258216U CN204632309U CN 204632309 U CN204632309 U CN 204632309U CN 201520258216 U CN201520258216 U CN 201520258216U CN 204632309 U CN204632309 U CN 204632309U
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Abstract
The utility model discloses a kind of display panel and display device, inconsistent with the resistance value transmitting each wire of sweep signal or data-signal in the display panel solving prior art, sweep signal or data-signal is made to arrive time delay of each integrated circuit (IC) chip inconsistent, scanning sequence or data-driven sequential is made to occur deviation, cause the phenomenon occurring that display brightness is uneven or image is not good, affect the problem of display quality.Described display panel, comprise multiple source signals end, each source signal end correspondence at least two integrated circuit (IC) chip, described in each corresponding with same described source signal end, all same with this described source signal end of the input end of integrated circuit (IC) chip is electrically connected by wire, and in the multiple described integrated circuit (IC) chip corresponding with same described source signal end, the input end of integrated circuit (IC) chip described in each is electrically connected by wire with the input end of ic core described at least one outside self.
Description
Technical field
The utility model relates to display technique field, particularly relates to a kind of display panel and display device.
Background technology
Flat-panel screens (F1at Pane1 Disp1ay, FPD) oneself becomes the main product on market, the kind of flat-panel screens also gets more and more, as liquid crystal display (Liquid Crysta1 Disp1ay, LCD), Organic Light Emitting Diode (Organic Light Emitted Diode, OLED) display, plasma display (P1asma Disp1ay Pane1, and Field Emission Display (Field Emission Display, FED) etc. PDP).
In prior art, there is larger difference in the track lengths of the wire of usual transmission sweep signal or data-signal, such as different integrated circuit (Integrated Circuit, IC) the corresponding same sweep signal of chip or data-signal, when source signal end (as gated sweep signal input part, data signal input etc.) is to different integrated circuit (IC) chip transmission scan signal or data-signal, the track lengths to integrated circuit (IC) chip is unequal.Because the track lengths of transmission each wire of scan signal line or each wire of transmission of data signals there are differences, therefore the resistance value of each wire is inconsistent, sweep signal or data-signal is made to arrive time delay of each integrated circuit (IC) chip inconsistent, scanning sequence or data-driven sequential is made to occur deviation, cause the phenomenon occurring that display brightness is uneven or image is not good, affect display quality.
Utility model content
The purpose of this utility model is to provide a kind of display panel and display device, inconsistent with the resistance value transmitting each wire of sweep signal or data-signal in the display panel solving prior art, sweep signal or data-signal is made to arrive time delay of each integrated circuit (IC) chip inconsistent, scanning sequence or data-driven sequential is made to occur deviation, cause the phenomenon occurring that display brightness is uneven or image is not good, affect the problem of display quality.
The purpose of this utility model is achieved through the following technical solutions:
The utility model embodiment provides a kind of display panel, comprise multiple source signals end, each source signal end correspondence at least two integrated circuit (IC) chip, described in each corresponding with same described source signal end, all same with this described source signal end of the input end of integrated circuit (IC) chip is electrically connected by wire, and in the multiple described integrated circuit (IC) chip corresponding with same described source signal end, the input end of integrated circuit (IC) chip described in each is electrically connected by wire with the input end of ic core described at least one outside self.
In the utility model embodiment, by each integrated circuit (IC) chip be connected with same described source signal end is all connected by wire with this source signal end, and connected by wire between each integrated circuit (IC) chip, form the structure of cabling in parallel, make the resistance between each integrated circuit (IC) chip with this source signal end roughly the same, thus reduce the difference of signal delay, make the deviation of scanning sequence or the appearance of data-driven sequential in less scope, thus reduce the phenomenon that display brightness is uneven or image is not good, improve display quality.
Preferably, in the multiple described integrated circuit (IC) chip corresponding with same described source signal end, the input end of integrated circuit (IC) chip described in each with outside self and adjacent at least one described in the input end of ic core be electrically connected by wire.In the utility model embodiment, described in another of input end one closer distance of integrated circuit (IC) chip described in each, the input end of integrated circuit (IC) chip is electrically connected by wire, can reduce taking of cabling space.
Preferably, described source signal end is pad; Or described source signal end is a signal pin in interface module; Or described source signal end is one group of signal pin of the signal of transmission identical characteristics.In the utility model embodiment, can according to different needs or different design needs, flexible providing source signal end.
Preferably, described source signal end comprises public voltage signal input end, gate drive signal input end, low level signal input end and high level signal input end.
Preferably, integrated circuit (IC) chip comprises grid drive chip and source driving chip.
Preferably, display panel also comprises printed circuit board (PCB) and array base palte, and described source signal end and integrated circuit (IC) chip are arranged on array base palte, and printed circuit board (PCB) is electrically connected with described source signal end by flexible PCB.
Preferably, array base palte comprises thin film transistor (TFT) array, for connecting the input end wire of described source signal end and described integrated circuit (IC) chip or arranging with layer for the wire of input end that is connected different described integrated circuit (IC) chip and the gate electrode of described thin film transistor (TFT), or arrange for the input end wire that connects described source signal end and described integrated circuit (IC) chip or for the wire of input end that is connected different described integrated circuit (IC) chip and the source electrode of described thin film transistor (TFT) and drain electrode with layer.In the utility model embodiment, wire and wire can be arranged with layer with the gate electrode of thin film transistor (TFT), source electrode or drain electrode respectively, and do not need to provide conductive layer separately, structure is simple; Accordingly, also can be combined with the preparation technology of the gate electrode of thin film transistor (TFT), source electrode or drain electrode, complete in identical preparation technology, not need to provide MASK separately.
The utility model embodiment also provides a kind of display device, comprises the display panel that as above embodiment provides.
The utility model is by being all connected each integrated circuit (IC) chip be connected with same source signal end by wire with this source signal end, and connected by wire between each integrated circuit (IC) chip, form the structure of cabling in parallel, make the resistance between each integrated circuit (IC) chip with this source signal end roughly the same, thus reduce the difference of signal delay, make the deviation of scanning sequence or the appearance of data-driven sequential in less scope, thus reduce the phenomenon that display brightness is uneven or image is not good, improve display quality.
Accompanying drawing explanation
In the first display panel that Fig. 1 provides for the utility model, signal letter enters the connection diagram of end and integrated circuit (IC) chip;
In the second display panel that Fig. 2 provides for the utility model, signal letter enters the connection diagram of end and integrated circuit (IC) chip;
The schematic diagram of a kind of more concrete display panel that Fig. 3 provides for the utility model.
Embodiment
Be described in detail below in conjunction with the implementation procedure of Figure of description to the utility model embodiment.It should be noted that same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the utility model, and can not being interpreted as restriction of the present utility model.
As shown in Figure 1, the utility model embodiment provides a kind of display panel 100, comprise multiple source signals end 1, each source signal end 1 correspondence at least two integrated circuit (IC) chip 2, all same with this source signal end 1 of input end of each integrated circuit (IC) chip 2 corresponding with same source signal end 1 is electrically connected by wire 3, and in multiple integrated circuit (IC) chip 2 corresponding with same source signal end 1, the input end of each integrated circuit (IC) chip 2 is electrically connected by wire 4 with the input end of at least one ic core 2 outside self.
It should be noted that, the connection between integrated circuit (IC) chip 2, can be only realize in respective input end, also can, according to the structure of integrated circuit (IC) chip 2 itself, select the port being suitable for the series connection of each integrated circuit (IC) chip 2 to realize.Diagram is for convenience of explanation clear, in the present embodiment, the wire 4 of the connection between integrated circuit (IC) chip 2 does not directly connect the input end of integrated circuit (IC) chip 2, but should be appreciated that, according to thought of the present utility model, its wire 4 can directly at the input end of integrated circuit (IC) chip 2.
Preferably, in multiple integrated circuit (IC) chip 2 corresponding with same source signal end 1, the input end of each integrated circuit (IC) chip 2 with outside self and the input end of at least one adjacent ic core 2 be electrically connected by wire.The input end of another integrated circuit (IC) chip 2 of input end one closer distance of each integrated circuit (IC) chip 2 is electrically connected by wire, can reduce taking of cabling space.
The connection diagram of two integrated circuit (IC) chip 2 and source signal end 1 is illustrate only in Fig. 1, according to thought of the present utility model, multiple integrated circuit (IC) chip 2 can be had to be connected by wire 3 with source signal end 1, and connected by wire 4 between each integrated circuit (IC) chip 2, concrete as shown in Fig. 2 (Reference numeral and Fig. 1 identical meanings), comprise three integrated circuit (IC) chip 2, source signal end 1 is electrically connected with the input end of three integrated circuit (IC) chip 2 respectively by wire, and the mode that three integrated circuit (IC) chip 2 are connected according to input end connects.
According to Fig. 1, the resistance between source signal end 1 and integrated circuit (IC) chip 2 is described as follows:
Source signal end 1 and two integrated circuit (IC) chip 2 are considered as an A, some B and some C respectively, and the resistance putting the wire 3 between A and some B is R
1, the resistance of the wire 3 between some A and some C is R
2, the resistance of the wire 4 between some B and some C is R
3, thus:
Equivalent resistance R between A point and B point
aBfor R
1with (R
2+ R
3) parallel resistance, can be obtained by formula (1):
Equivalent resistance R between A point and C point
aCfor R
2with (R
1+ R
3) parallel resistance, can be obtained by formula (2):
Resistance R
aBwith resistance R
aCratio be
due to R
2be greater than R
1, then R
2+ R
3r must be greater than
1+ R
3, therefore
compare
more be tending towards 1, make the resistance R of source signal end 1 to two integrated circuit (IC) chip 2
aBwith resistance R
aCsubstantially equal, reduce the difference of signal delay.Have more multiple ic chip 2 time (such as 3 integrated circuit (IC) chip, 2,4 integrated circuit (IC) chip 2, or more integrated circuit (IC) chip 2), meet this rule equally, and equivalent resistance between source signal end 1 to each integrated circuit (IC) chip 2 is all roughly equal.
In the utility model embodiment, by each integrated circuit (IC) chip 2 be connected with same source signal end 1 is all connected by wire 3 with this source signal end 1, and connected by wire 4 between each integrated circuit (IC) chip 2, form the structure of cabling in parallel, make the resistance between each integrated circuit (IC) chip 2 with this source signal end 1 roughly the same, thus reduce the difference of signal delay, make the deviation of scanning sequence or the appearance of data-driven sequential in less scope, thus reduce the phenomenon that display brightness is uneven or image is not good, improve display quality.
Preferably, source signal end 1 is pad; Or source signal end 1 is a signal pin in interface module; Or source signal end 1 is one group of signal pin of the signal of transmission identical characteristics.In the utility model embodiment, flexible providing source signal end 1 can be needed according to different needs or different designs.
Preferably, source signal end 1 comprises public voltage source signal end, raster data model source signal end, low level source signal end and high level source signal end.
Preferably, integrated circuit (IC) chip 2 comprises grid drive chip and source driving chip.
Certainly, display panel 100 can comprise other assembly, and such as, shown in Fig. 3, display panel 100 also comprises printed circuit board (PCB) 5 and array base palte 6, source signal end 1 and integrated circuit (IC) chip 2 are arranged on array base palte 6, and printed circuit board (PCB) 5 is electrically connected with source signal end 1 by flexible PCB 7.
Preferably, array base palte 6 comprises thin film transistor (TFT) array (not shown), and wire 3 and wire 4 are arranged with layer with the gate electrode of thin film transistor (TFT), or the source electrode of wire 3 and wire 4 and thin film transistor (TFT) and drain electrode are arranged with layer.In the utility model embodiment, wire (such as wire 3 and/or wire 4) can be arranged with layer with the gate electrode of thin film transistor (TFT), source electrode or drain electrode respectively, and do not need to provide conductive layer separately, structure is simple; Accordingly, also can be combined with the preparation technology of the gate electrode of thin film transistor (TFT), source electrode or drain electrode, complete in identical preparation technology, not need to provide MASK separately.
The utility model embodiment beneficial effect is as follows: by each integrated circuit (IC) chip be connected with same source signal end being all connected by wire with this source signal end, and connected by wire between each integrated circuit (IC) chip, form the structure of cabling in parallel, make the resistance between each integrated circuit (IC) chip with this source signal end roughly the same, thus reduce the difference of signal delay, make the deviation of scanning sequence or the appearance of data-driven sequential in less scope, thus reduce the phenomenon that display brightness is uneven or image is not good, improve display quality.
The utility model embodiment provides a kind of display device, comprises the display panel that as above embodiment provides.
The utility model embodiment beneficial effect is as follows: by each integrated circuit (IC) chip be connected with same source signal end being all connected by wire with this source signal end, and connected by wire between each integrated circuit (IC) chip, form the structure of cabling in parallel, make the resistance between each integrated circuit (IC) chip with this source signal end roughly the same, thus reduce the difference of signal delay, make the deviation of scanning sequence or the appearance of data-driven sequential in less scope, thus reduce the phenomenon that display brightness is uneven or image is not good, improve display quality.
Obviously, those skilled in the art can carry out various change and modification to the utility model and not depart from spirit and scope of the present utility model.Like this, if these amendments of the present utility model and modification belong within the scope of the utility model claim and equivalent technologies thereof, then the utility model is also intended to comprise these change and modification.
Claims (8)
1. a display panel, comprise multiple source signals end, each source signal end correspondence at least two integrated circuit (IC) chip, it is characterized in that, described in each corresponding with same described source signal end, all same with this described source signal end of the input end of integrated circuit (IC) chip is electrically connected by wire, and in the multiple described integrated circuit (IC) chip corresponding with same described source signal end, the input end of integrated circuit (IC) chip described in each is electrically connected by wire with the input end of ic core described at least one outside self.
2. display panel as claimed in claim 1, it is characterized in that, in the multiple described integrated circuit (IC) chip corresponding with same described source signal end, the input end of integrated circuit (IC) chip described in each with outside self and adjacent at least one described in the input end of ic core be electrically connected by wire.
3. display panel as claimed in claim 1 or 2, it is characterized in that, described source signal end is pad; Or described source signal end is a signal pin in interface module; Or described source signal end is one group of signal pin of the signal of transmission identical characteristics.
4. display panel as claimed in claim 3, it is characterized in that, described source signal end comprises public voltage signal input end, gate drive signal input end, low level signal input end and high level signal input end.
5. display panel as claimed in claim 1, it is characterized in that, described integrated circuit (IC) chip comprises grid drive chip and source driving chip.
6. display panel as claimed in claim 3, it is characterized in that, described display panel also comprises printed circuit board (PCB) and array base palte, and described source signal end and described integrated circuit (IC) chip are arranged on described array base palte, and described printed circuit board (PCB) is electrically connected with described source signal end by flexible PCB.
7. display panel as claimed in claim 6, it is characterized in that, described array base palte comprises thin film transistor (TFT) array, for connecting the input end wire of described source signal end and described integrated circuit (IC) chip or arranging with layer for the wire of input end that is connected different described integrated circuit (IC) chip and the gate electrode of described thin film transistor (TFT), or arrange for the input end wire that connects described source signal end and described integrated circuit (IC) chip or for the wire of input end that is connected different described integrated circuit (IC) chip and the source electrode of described thin film transistor (TFT) and drain electrode with layer.
8. a display device, is characterized in that, comprises the display panel as described in any one of claim 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520258216.8U CN204632309U (en) | 2015-04-24 | 2015-04-24 | A kind of display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520258216.8U CN204632309U (en) | 2015-04-24 | 2015-04-24 | A kind of display panel and display device |
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| Publication Number | Publication Date |
|---|---|
| CN204632309U true CN204632309U (en) | 2015-09-09 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105590613A (en) * | 2016-03-25 | 2016-05-18 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2017084143A1 (en) * | 2015-11-19 | 2017-05-26 | 深圳市华星光电技术有限公司 | Liquid crystal display device and liquid crystal display |
| CN107342060A (en) * | 2017-09-13 | 2017-11-10 | 京东方科技集团股份有限公司 | Driving chip and display device |
-
2015
- 2015-04-24 CN CN201520258216.8U patent/CN204632309U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017084143A1 (en) * | 2015-11-19 | 2017-05-26 | 深圳市华星光电技术有限公司 | Liquid crystal display device and liquid crystal display |
| CN105590613A (en) * | 2016-03-25 | 2016-05-18 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN107342060A (en) * | 2017-09-13 | 2017-11-10 | 京东方科技集团股份有限公司 | Driving chip and display device |
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