CN105807470A - Array substrate, display panel and display device - Google Patents

Array substrate, display panel and display device Download PDF

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Publication number
CN105807470A
CN105807470A CN201610370170.8A CN201610370170A CN105807470A CN 105807470 A CN105807470 A CN 105807470A CN 201610370170 A CN201610370170 A CN 201610370170A CN 105807470 A CN105807470 A CN 105807470A
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CN
China
Prior art keywords
frame region
signal output
output unit
array base
base palte
Prior art date
Application number
CN201610370170.8A
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Chinese (zh)
Inventor
许喜爱
刘冰萍
周秀峰
颜佳友
李俊谊
Original Assignee
厦门天马微电子有限公司
天马微电子股份有限公司
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Priority to CN201610370170.8A priority Critical patent/CN105807470A/en
Publication of CN105807470A publication Critical patent/CN105807470A/en

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    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/133308Support structures for LCD panels, e.g. frames or bezels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes

Abstract

The invention discloses an array substrate, a display panel and a display device.The array substrate comprises a display area, a frame area and a gate drive circuit, wherein the display area is provided with a plurality of gate lines data cables; the frame area is arranged around the display area; the gate drive circuit includes signal output units of multiple levels and buffer units of multiple levels; the signal output units are used for outputting transmission signals of at least one level and the transmission signal of each level is correspondingly connected to a buffer unit of one level; the buffer unit of each level is electrically connected with one gate line and the buffer units are used for outputting scanning start signals for scanning the gate lines; and the signal output units are positioned in the frame area while the buffer units are positioned in the display area.The buffer units of multiple levels in the gate drive circuit are arranged in the display area so that area occupied by the gate drive circuit in the frame area is reduced, and the area of the frame area is accordingly decreased, and narrow-frame design of the display device can be achieved.

Description

A kind of array base palte, display floater and display device
Technical field
The present invention relates to Display Technique field, more specifically, relate to a kind of array base palte, display floater and display device.
Background technology
Along with the development of electronic technology and improving constantly of people's living standard, liquid crystal indicator and organic light-emitting display device etc. have been widely used in the middle of people's routine work and life, concrete such as electronic equipments such as electronic computer, mobile phone, panel computers.Display in order to realize display device scans, and the frame region at the array base palte of display device can arrange gate driver circuit, and the scanning start signal produced by gate driver circuit realizes display scanning.But, gate driver circuit needs to take bigger space, and this can make the frame region area of array base palte relatively big, so that display device is difficulty with the design of narrow frame.
Summary of the invention
In view of this, the invention provides a kind of array base palte, display floater and display device, multi-buffer unit in gate driver circuit is arranged at viewing area, and then reduction gate driver circuit takies the area of frame region, and then the area of frame region can be reduced, it is achieved the design of the narrow frame of display device.
For achieving the above object, technical scheme provided by the invention is as follows:
A kind of array base palte, including viewing area, described viewing area is provided with a plurality of gate line and a plurality of data lines, and described a plurality of gate line and a plurality of data lines intersection limit multiple pixels;
And, around the frame region of described viewing area, also including gate driver circuit, described gate driver circuit includes:
Multilevel signal output unit and multi-buffer unit, described signal output unit is for exporting at least Primary Transmit signal one by one, every Primary Transmit signal correspondence accesses to first-level buffer unit, and often one-level buffer cell and gate line electrical connection, described buffer cell is for exporting the scanning start signal for scanning described gate line according to described transmission signal;
Wherein, described signal output unit is positioned at described frame region, and described buffer cell is positioned at described viewing area.
Optionally, described frame region includes frame region, first side and frame region, second side, frame region, described first side and frame region, second side and lays respectively at the two ends on the bearing of trend of described gate line;
Wherein, described multilevel signal output unit is arranged in any one side frame region in frame region, described first side and frame region, second side.
Optionally, described frame region includes frame region, first side and frame region, second side, frame region, described first side and frame region, second side and lays respectively at the two ends on the bearing of trend of described gate line;
Wherein, described multilevel signal output unit is divided into the first signal output unit group and secondary signal output unit group, and described first signal output unit group is positioned at described first frame region, and described secondary signal output unit group is positioned at frame region, second side.
Optionally, described signal output unit is shift register circuit, and described shift register circuit is used for exporting described transmission signal.
Optionally, described signal output unit includes at least one-level selection output circuit that latch cicuit electrically connects and the clock control end electrically connected with described selection output circuit with described latch cicuit;
Described latch cicuit is for latching output start signal and till the gate line that scanned and described signal output unit is corresponding, and described at least one-level selects output circuit for exporting described transmission signal according to described start signal one by one according to the control of corresponding clock control end.
Optionally, described selection output circuit is between described latch cicuit and viewing area.
Optionally, described multilevel signal output unit arranges along the bearing of trend of described data wire.
Optionally, described buffer cell gap between the plurality of pixel.
Optionally, the plurality of pixel is divided into multiple pixel row and the gap that described buffer cell is between adjacent two described pixel row along the bearing of trend of described data wire.
Optionally, described buffer cell is positioned at the gate line being connected electrically any side on described data wire bearing of trend.
Optionally, a described buffer cell is included between adjacent two described gate lines.
Optionally, the link of described buffer cell and described gate line is positioned at the midpoint of described gate line.
Accordingly, present invention also offers a kind of display floater, described display floater includes above-mentioned array base palte.
Accordingly, present invention also offers a kind of display device, described display device includes above-mentioned display floater.
Optionally, described display device is organic light-emitting display device or liquid crystal indicator.
Compared to prior art, technical scheme provided by the invention at least has the advantage that
The invention provides a kind of array base palte, display floater and display device, including viewing area, described viewing area is provided with a plurality of gate line and a plurality of data lines;And, frame region around described viewing area, also include gate driver circuit, described gate driver circuit includes: multilevel signal output unit and multi-buffer unit, described signal output unit is for exporting at least Primary Transmit signal one by one, every Primary Transmit signal correspondence accesses to first-level buffer unit, and every one-level buffer cell and a gate line electrically connect, and described buffer cell is for exporting the scanning start signal for scanning described gate line according to described transmission signal;Wherein, described signal output unit is positioned at described frame region, and described buffer cell is between described signal output unit and described gate line and is positioned at described viewing area.As shown in the above, technical scheme provided by the invention, is arranged at viewing area by the multi-buffer unit in gate driver circuit, and then reduction gate driver circuit takies the area of frame region, and then the area of frame region can be reduced, it is achieved the design of the narrow frame of display device.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme in the embodiment of the present invention, below the accompanying drawing used required during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other accompanying drawing according to the accompanying drawing provided.
The structural representation of a kind of array base palte that Fig. 1 provides for the embodiment of the present application;
The structural representation of the another kind of array base palte that Fig. 2 provides for the embodiment of the present application;
The structural representation of another array base palte that Fig. 3 provides for the embodiment of the present application;
The structural representation of another array base palte that Fig. 4 provides for the embodiment of the present application;
The structural representation of another array base palte that Fig. 5 provides for the embodiment of the present application;
The structural representation of another array base palte that Fig. 6 provides for the embodiment of the present application;
The structural representation of a kind of display floater that Fig. 7 provides for the embodiment of the present application;
The structural representation of a kind of display device that Fig. 8 provides for the embodiment of the present application.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under not making creative work premise, broadly fall into the scope of protection of the invention.
As described in background, the display in order to realize display device scans, and the frame region at the array base palte of display device can arrange gate driver circuit, and the scanning start signal produced by gate driver circuit realizes display scanning.But, gate driver circuit needs to take bigger space, and this can make the frame region area of array base palte relatively big, so that display device is difficulty with the design of narrow frame.
Based on this, the embodiment of the present application provides a kind of array base palte, display floater and display device, multi-buffer unit in gate driver circuit is arranged at viewing area, and then reduction gate driver circuit takies the area of frame region, and then the area of frame region can be reduced, it is achieved the design of the narrow frame of display device.For achieving the above object, the technical scheme that the embodiment of the present application provides is as follows, and specifically in conjunction with shown in Fig. 1 to Fig. 8, the technical scheme that the embodiment of the present application is provided is described in detail.
With reference to shown in Fig. 1, for the structural representation of a kind of array base palte that the embodiment of the present application provides, wherein, array base palte includes:
Viewing area 100, described viewing area 100 is provided with a plurality of gate line 110 and a plurality of data lines 120, and described a plurality of gate line 110 and a plurality of data lines 120 intersection limit multiple pixels 130;
And, around the frame region 200 of described viewing area 100;
And, array base palte also includes gate driver circuit 300, and described gate driver circuit 300 includes:
Multilevel signal output unit 310 and multi-buffer unit 320, described signal output unit 310 is for exporting at least Primary Transmit signal one by one, every Primary Transmit signal correspondence accesses to first-level buffer unit 320, and often one-level buffer cell 320 electrically connects with a gate line 110, described buffer cell 320 is for exporting the scanning start signal for scanning described gate line 110 according to described transmission signal;
Wherein, described signal output unit 310 is positioned at described frame region 200, and described buffer cell 320 is positioned at described viewing area 100.
It should be noted that the array base palte that the embodiment of the present application provides, all pixels are divided into a pixel point range along gate line bearing of trend, and are divided into multiple pixel row along data wire bearing of trend;Other structures of array base palte that the embodiment of the present application provides are same as the prior art, therefore do not repeat;As, a plurality of data lines that the embodiment of the present application provides, it electrically connects with the driving IC being positioned at frame region, and this is same as the prior art.
As shown in the above, the technical scheme that the embodiment of the present application provides, is arranged at viewing area by the multi-buffer unit in gate driver circuit, and then reduction gate driver circuit takies the area of frame region, and then the area of frame region can be reduced, it is achieved the design of the narrow frame of display device.
In the application one embodiment, gate driver circuit may be located at a side of array base palte, and do not do the setting of grid electrode drive circuit structure at another side, and shown in Fig. 1, the described frame region 200 that the embodiment of the present application provides includes:
Frame region, first side 210 and frame region, second side 220, frame region, described first side 210 and frame region, second side 220 lay respectively at the two ends on the bearing of trend of described gate line 110;
Wherein, described multilevel signal output unit 310 is arranged in any one side frame region in frame region, described first side 210 and frame region, second side 220.
Wherein, the gate driver circuit of embodiment offer corresponding to the application Fig. 1, it is possible to by being arranged at the multilevel signal output unit of side frame region, and gate line is scanned by buffer cell step by step that arrange corresponding connection in viewing area.
It addition, in another embodiment of the application, gate driver circuit is further divided into two parts, it is respectively arranged at the different sides of array base palte.Shown in Fig. 2, for the structural representation of the another kind of array base palte that the embodiment of the present application provides, wherein, the described frame region 200 that the embodiment of the present application provides includes:
Frame region, first side 210 and frame region, second side 220, frame region, described first side 210 and frame region, second side 220 lay respectively at the two ends on the bearing of trend of described gate line 110;
Wherein, described multilevel signal output unit 310 is divided into the first signal output unit group 301 and secondary signal output unit group 302, described first signal output unit group 301 is positioned at described first frame region 210, and described secondary signal output unit group 302 is positioned at frame region, second side 220
In the application one embodiment, gate driver circuit can the gate driver circuit of shift register circuit type, wherein, with reference to shown in Fig. 3, structural representation for another array base palte that the embodiment of the present application provides, wherein, the described signal output unit 310 that the embodiment of the present application provides is shift register circuit SR (shiftregister), described shift register circuit SR is used for exporting described transmission signal, then, after transmission signal being driven the raising of ability by buffer cell 320, output scans start signal and transmits to gate line 110, so that gate line 110 is scanned.
Additionally, in another embodiment of the application, gate driver circuit can also be the gate driver circuit of latch cicuit type, wherein, with reference to shown in Fig. 4, for the structural representation of another array base palte that the embodiment of the present application provides, the described signal output unit 310 that the embodiment of the present application provides includes at least one-level selection output circuit 312 that latch cicuit 311 electrically connects and the clock control end 313 electrically connected with described selection output circuit 312 with described latch cicuit 311;
Described latch cicuit 311 is for latching and export start signal and till the gate line 110 that scanned and described signal output unit 310 is corresponding, and described at least one-level selects output circuit 312 for exporting described transmission signal according to described start signal one by one according to the control of corresponding clock control end 313.
Wherein, in order to optimize the area occupied of signal output unit 310, the described selection output circuit 312 that the embodiment of the present application provides is between described latch cicuit 311 and viewing area 100.
With reference to shown in Fig. 5, for the structural representation of another array base palte that the embodiment of the present application provides, wherein, in the above-mentioned any one embodiment of the application, the described multilevel signal output unit 310 that the application provides arranges along the bearing of trend of described data wire 120.
It addition, in order to avoid the aperture opening ratio of the viewing area of array substrate impacts, the buffer cell 320 that the embodiment of the present application provides gap between the plurality of pixel 130.Further, the plurality of pixel 130 that the embodiment of the present application provides is divided into multiple pixel row 131 and the gap that described buffer cell 320 is between adjacent two described pixel row 131 along the bearing of trend of described data wire.
Owing to buffer cell is electrically connected by needs with gate line, for the ease of both electrical connections, the buffer cell 320 that the embodiment of the present application provides is positioned at the gate line 110 being connected electrically any side on described data wire 120 bearing of trend.Further, owing to the interval area being connected between two pixel row 131 is limited, in order to avoid there is affecting the situation of display device aperture opening ratio, between adjacent two described gate lines 110, a described buffer cell 320 is included.
Further, with reference to shown in Fig. 6, structural representation for another array base palte that the embodiment of the present application provides, wherein, when the buffer cell 320 gap between the plurality of pixel 130 that the embodiment of the present application provides, in order to ensure that on gate line 110, the uniformity of signal transmission is high, the described buffer cell 320 of the embodiment of the present application offer is positioned at the midpoint of described gate line 110 with the link of described gate line 110.
In addition, in another embodiment of the application, buffer cell may be located on the marginal area of viewing area, namely, when being arranged in frame region, described first side and any one side frame region, frame region, second side when the described multilevel signal output unit that the embodiment of the present application provides, the described multi-buffer unit that the embodiment of the present application provides is positioned at the described viewing area marginal area near described signal output unit side.Or, when the first signal output unit group is positioned at frame region, first side and secondary signal output unit group is positioned at frame region, second side, the buffer cell corresponding with each signal output unit in described first signal output unit group that the embodiment of the present application provides, is positioned at the described viewing area marginal area near described first signal output unit group side;And, the buffer cell corresponding with each signal output unit in described secondary signal output unit group, it is positioned at the described viewing area marginal area near described secondary signal output unit group side.It should be noted that the particular location that the embodiment of the present application is positioned at viewing area for buffer cell does not limit, it is necessary to carry out concrete design according to practical application.
Accordingly, the embodiment of the present application additionally provides a kind of display floater, and wherein, described display floater includes the array base palte that above-mentioned any one embodiment provides.
Optionally, the display floater that the application provides can be display panels, and shown in Fig. 7, for the structural representation of a kind of display floater that the embodiment of the present application provides, display floater includes:
The color membrane substrates 10 being oppositely arranged and array base palte 20, the array base palte that array base palte 20 provides for above-mentioned any one embodiment;
And, it is arranged at the liquid crystal layer 30 between color membrane substrates 10 and array base palte 20.
Additionally, the display floater that the embodiment of the present application provides can also be organic electroluminescence display panel, this application is not particularly limited.
Accordingly, the embodiment of the present application additionally provides a kind of display device, and described display device includes the display floater that above-described embodiment provides.
Optionally, the display device that the application provides can be liquid crystal indicator, and shown in Fig. 8, for the structural representation of a kind of display device that the embodiment of the present application provides, display device includes:
Display floater and for display
Panel provides the backlight source module 40 of light source (in Fig. 8 arrow);
Wherein, display floater includes:
The color membrane substrates 10 being oppositely arranged and array base palte 20, the array base palte that array base palte 20 provides for above-mentioned any one embodiment;
And, it is arranged at the liquid crystal layer 30 between color membrane substrates 10 and array base palte 20.
Additionally, the display device that the embodiment of the present application provides can also be organic light-emitting display device, this application is not particularly limited.Concrete, the display device that the embodiment of the present application provides can be mobile phone, electronic computer, panel computer etc..
The embodiment of the present application provides a kind of array base palte, display floater and display device, and including viewing area, described viewing area is provided with a plurality of gate line and a plurality of data lines;And, frame region around described viewing area, also include gate driver circuit, described gate driver circuit includes: multilevel signal output unit and multi-buffer unit, described signal output unit is for exporting at least Primary Transmit signal one by one, every Primary Transmit signal correspondence accesses to first-level buffer unit, and every one-level buffer cell and a gate line electrically connect, and described buffer cell is for exporting the scanning start signal for scanning described gate line according to described transmission signal;Wherein, described signal output unit is positioned at described frame region, and described buffer cell is between described signal output unit and described gate line and is positioned at described viewing area.As shown in the above, the technical scheme that the embodiment of the present application provides, is arranged at viewing area by the multi-buffer unit in gate driver circuit, and then reduction gate driver circuit takies the area of frame region, and then the area of frame region can be reduced, it is achieved the design of the narrow frame of display device.
Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses the present invention.The multiple amendment of these embodiments be will be apparent from for those skilled in the art, and generic principles defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention is not intended to be limited to the embodiments shown herein, and is to fit to the widest scope consistent with principles disclosed herein and features of novelty.

Claims (15)

1. an array base palte, including viewing area, described viewing area is provided with a plurality of gate line and a plurality of data lines, and described a plurality of gate line and a plurality of data lines intersection limit multiple pixels;
And, around the frame region of described viewing area, it is characterised in that also including gate driver circuit, described gate driver circuit includes:
Multilevel signal output unit and multi-buffer unit, described signal output unit is for exporting at least Primary Transmit signal one by one, every Primary Transmit signal correspondence accesses to first-level buffer unit, and often one-level buffer cell and gate line electrical connection, described buffer cell is for exporting the scanning start signal for scanning described gate line according to described transmission signal;
Wherein, described signal output unit is positioned at described frame region, and described buffer cell is positioned at described viewing area.
2. array base palte according to claim 1, it is characterised in that described frame region includes frame region, first side and frame region, second side, frame region, described first side and frame region, second side and lays respectively at the two ends on the bearing of trend of described gate line;
Wherein, described multilevel signal output unit is arranged in any one side frame region in frame region, described first side and frame region, second side.
3. array base palte according to claim 1, it is characterised in that described frame region includes frame region, first side and frame region, second side, frame region, described first side and frame region, second side and lays respectively at the two ends on the bearing of trend of described gate line;
Wherein, described multilevel signal output unit is divided into the first signal output unit group and secondary signal output unit group, and described first signal output unit group is positioned at described first frame region, and described secondary signal output unit group is positioned at frame region, second side.
4. array base palte according to claim 1, it is characterised in that described signal output unit is shift register circuit, described shift register circuit is used for exporting described transmission signal.
5. array base palte according to claim 1, it is characterised in that described signal output unit includes at least one-level selection output circuit that latch cicuit electrically connects and the clock control end electrically connected with described selection output circuit with described latch cicuit;
Described latch cicuit is for latching output start signal and till the gate line that scanned and described signal output unit is corresponding, and described at least one-level selects output circuit for exporting described transmission signal according to described start signal one by one according to the control of corresponding clock control end.
6. array base palte according to claim 5, it is characterised in that described selection output circuit is between described latch cicuit and viewing area.
7. array base palte according to claim 1, it is characterised in that described multilevel signal output unit arranges along the bearing of trend of described data wire.
8. the array base palte according to claim 1~7 any one, it is characterised in that described buffer cell gap between the plurality of pixel.
9. array base palte according to claim 8, it is characterised in that the plurality of pixel is divided into multiple pixel row and the gap that described buffer cell is between adjacent two described pixel row along the bearing of trend of described data wire.
10. array base palte according to claim 8, it is characterised in that described buffer cell is positioned at the gate line being connected electrically any side on described data wire bearing of trend.
11. array base palte according to claim 10, it is characterised in that include a described buffer cell between adjacent two described gate lines.
12. array base palte according to claim 8, it is characterised in that the link of described buffer cell and described gate line is positioned at the midpoint of described gate line.
13. a display floater, it is characterised in that described display floater includes the array base palte described in claim 1~12 any one.
14. a display device, it is characterised in that described display device includes the display floater described in claim 13.
15. display device according to claim 14, it is characterised in that described display device is organic light-emitting display device or liquid crystal indicator.
CN201610370170.8A 2016-05-27 2016-05-27 Array substrate, display panel and display device CN105807470A (en)

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CN104485085A (en) * 2015-01-04 2015-04-01 京东方科技集团股份有限公司 Array substrate and display device
CN104503632A (en) * 2015-01-26 2015-04-08 京东方科技集团股份有限公司 Buffer unit, touch drive circuit, display device and drive method of display device
CN204360353U (en) * 2015-01-26 2015-05-27 京东方科技集团股份有限公司 Buffer cell, touch drive circuit and display device
CN104599622A (en) * 2015-02-13 2015-05-06 上海天马有机发光显示技术有限公司 Dynamic logic circuit, grid driving circuit, display panel and display device

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WO2018028017A1 (en) * 2016-08-10 2018-02-15 武汉华星光电技术有限公司 Liquid-crystal display panel and liquid-crystal display device
US10114261B2 (en) 2016-08-10 2018-10-30 Wuhan China Star Optoelectronics Technology Co., Ltd Liquid crystal panels and liquid crystal devices
US10317760B2 (en) 2016-08-10 2019-06-11 Wuhan China Star Optoelectronics Technology Co., Ltd Liquid crystal panels and liquid crystal devices
CN106940991A (en) * 2017-04-25 2017-07-11 深圳市华星光电技术有限公司 Scan drive circuit and display device
CN106940991B (en) * 2017-04-25 2019-03-01 深圳市华星光电技术有限公司 Scan drive circuit and display device
CN108646484A (en) * 2018-05-04 2018-10-12 昆山国显光电有限公司 Display panel and display device
CN110265454A (en) * 2019-06-25 2019-09-20 上海天马微电子有限公司 A kind of display panel, its production method and display device

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