CN105976745B - Array substrate tests circuit, display panel and flat display apparatus - Google Patents
Array substrate tests circuit, display panel and flat display apparatus Download PDFInfo
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- CN105976745B CN105976745B CN201610580608.5A CN201610580608A CN105976745B CN 105976745 B CN105976745 B CN 105976745B CN 201610580608 A CN201610580608 A CN 201610580608A CN 105976745 B CN105976745 B CN 105976745B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Abstract
The present invention discloses a kind of array substrate test circuit, display panel and flat display apparatus.Array substrate test circuit includes chip, and chip includes the second pin for transmitting the first pin and transmission closing voltage end signal of cut-in voltage end signal；Unidirectionally controlled unit；Array substrate test cell including electrostatic protection device, transmits the first pad of cut-in voltage end signal and transmits the second pad for closing voltage end signal, first and second pad is separately connected a pin of electrostatic protection device；When the chip is working, unidirectionally controlled unit cut-off, the cut-in voltage end signal and closing voltage end signal of chip transmission cannot export and give first and second pad；When the work of array substrate test cell, unidirectionally controlled unit conducting, the cut-in voltage end signal received and closing voltage end signal are transferred to chip by first and second pad, it avoids impacting the signal in chip with this, and then increases product parsing duration and reduce the stability of product.
Description
Technical field
The present invention relates to field of display technology, more particularly to a kind of array substrate test circuit, display panel and plane
Display device.
Background technique
Scan drive circuit is used in current flat display apparatus, that is, is shown using existing thin film transistor (TFT) plane
Scan drive circuit is produced in array substrate by device array process, realizes the driving method to progressive scan, while in array
Array substrate is set on substrate and tests circuit, to carry out electrical testing to array substrate after array substrate is completed, however, existing
The signal of chip output is exposed in air by array substrate test cell in some array substrate test circuits, can be to chip
Interior signal impacts, and the jump of signal will lead to the failure of array substrate test cell in chip, so as to cause needs
The test parsing carried out by array substrate test cell can not carry out, so that increasing product parsing duration and reducing production
The stability of product.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of array substrate test circuit, display panel and planes to show
Device, it is exposed right in air by array substrate test cell with the signal for solving chip output in array substrate test circuit
Signal in chip impacts, and then increases the problem of product parses duration and reduces the stability of product.
In order to solve the above technical problems, one technical scheme adopted by the invention is that：A kind of array substrate test electricity is provided
Road, including：
Chip, the chip include the first pin and second pin, and first pin is used for transmission cut-in voltage end letter
Number, the second pin, which is used for transmission, closes voltage end signal；
Unidirectionally controlled unit connects the first pin and second pin of the chip, is used for transmission the cut-in voltage end
Signal and the closing voltage end signal；And
Array substrate test cell, the array substrate test cell include electrostatic protection device, the first pad and second
Pad, the electrostatic protection device connect the unidirectionally controlled unit, and first pad and second pad respectively correspond
A pin of the electrostatic protection device is connected, first pad is used for transmission cut-in voltage end signal, second weldering
Disk, which is used for transmission, closes voltage end signal；When the chip operation, the unidirectionally controlled unit cut-off, the first of the chip
The cut-in voltage end signal of pin transmission cannot be exported by the unidirectionally controlled unit and the electrostatic protection device to described
The closing voltage end signal of the second pin of first pad and chip transmission can not by the unidirectionally controlled unit and
The electrostatic protection device is exported to second pad；It is described unidirectionally controlled when array substrate test cell work
Unit conducting, first pad protect the cut-in voltage end signal received by the unidirectionally controlled unit and the electrostatic
Shield device transmission passes through the closing voltage end signal received to the first pin of the chip and second pad described
Unidirectionally controlled unit and the electrostatic protection device are transferred to the second pin of the chip.
Wherein, the unidirectionally controlled unit include the first controllable switch and the second controllable switch, it is described first and second can
Control switch respectively includes control terminal, first end and second end, and the control terminal of first controllable switch is controllably opened with described first
The first end of pass is connected and is connected to the first pin of the chip, and the second end of first controllable switch is connected to described quiet
One pin of electric protective component, the control terminal of second controllable switch are connected simultaneously with the first end of second controllable switch
It is connected to the second pin of the chip, the second end of second controllable switch is connected to one of the electrostatic protection device
Pin, first controllable switch be N-type TFT, second controllable switch be P-type TFT, described first
Control terminal, first end and the second end of switch respectively correspond the grid, source electrode and drain electrode of the N-type TFT, and described
Control terminal, first end and the second end of two switches respectively correspond the grid, source electrode and drain electrode of the P-type TFT.
Wherein, the unidirectionally controlled unit include the first controllable switch and the second controllable switch, it is described first and second can
Control switch respectively includes control terminal, first end and second end, and the control terminal of first controllable switch is controllably opened with described first
The first end of pass is connected and is connected to the first pin of the chip, and the second end of first controllable switch connects the electrostatic
A pin of device is protected, the first end of second controllable switch connects the second pin of the chip, and described second can
The control terminal of control switch is connected with the second end of second controllable switch and is connected to one of the electrostatic protection device and draws
Foot, first and second described controllable switch is N-type TFT, control terminal, the first end of first and second switch
And second end respectively corresponds the grid, source electrode and drain electrode of the N-type TFT.
Wherein, which is characterized in that the array substrate test cell further includes several third pads, each third pad pair
The pin that the electrostatic protection device should be connected, for providing signal for picture element display area and turntable driving region.
Wherein, the array substrate test circuit further includes the 4th pad and the 5th pad, and the 4th pad connects institute
The first pin for stating chip, is used for transmission the cut-in voltage end signal, and the 5th pad connects the second of the chip and draws
Foot is used for transmission the closing voltage end signal, covers insulant on the 4th and the 5th pad, when using the described 4th and
The insulant being covered on the 4th and the 5th pad is removed when five pads.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of display panel is provided, it is described
Display panel includes array substrate test circuit, and the array substrate test circuit includes：
Chip, the chip include the first pin and second pin, and first pin is used for transmission cut-in voltage end letter
Number, the second pin, which is used for transmission, closes voltage end signal；
Unidirectionally controlled unit connects the first pin and second pin of the chip, is used for transmission the cut-in voltage end
Signal and the closing voltage end signal；And
Array substrate test cell, the array substrate test cell include electrostatic protection device, the first pad and second
Pad, the electrostatic protection device connect the unidirectionally controlled unit, and first pad and second pad respectively correspond
A pin of the electrostatic protection device is connected, first pad is used for transmission cut-in voltage end signal, second weldering
Disk, which is used for transmission, closes voltage end signal；When the chip operation, the unidirectionally controlled unit cut-off, the first of the chip
The cut-in voltage end signal of pin transmission cannot be exported by the unidirectionally controlled unit and the electrostatic protection device to described
The closing voltage end signal of the second pin of first pad and chip transmission can not by the unidirectionally controlled unit and
The electrostatic protection device is exported to second pad；It is described unidirectionally controlled when array substrate test cell work
Unit conducting, first pad protect the cut-in voltage end signal received by the unidirectionally controlled unit and the electrostatic
Shield device transmission passes through the closing voltage end signal received to the first pin of the chip and second pad described
Unidirectionally controlled unit and the electrostatic protection device are transferred to the second pin of the chip.
Wherein, the unidirectionally controlled unit include the first controllable switch and the second controllable switch, it is described first and second can
Control switch respectively includes control terminal, first end and second end, and the control terminal of first controllable switch is controllably opened with described first
The first end of pass is connected and is connected to the first pin of the chip, and the second end of first controllable switch is connected to described quiet
One pin of electric protective component, the control terminal of second controllable switch are connected simultaneously with the first end of second controllable switch
It is connected to the second pin of the chip, the second end of second controllable switch is connected to one of the electrostatic protection device
Pin, first controllable switch be N-type TFT, second controllable switch be P-type TFT, described first
Control terminal, first end and the second end of switch respectively correspond the grid, source electrode and drain electrode of the N-type TFT, and described
Control terminal, first end and the second end of two switches respectively correspond the grid, source electrode and drain electrode of the P-type TFT.
Wherein, the unidirectionally controlled unit include the first controllable switch and the second controllable switch, it is described first and second can
Control switch respectively includes control terminal, first end and second end, and the control terminal of first controllable switch is controllably opened with described first
The first end of pass is connected and is connected to the first pin of the chip, and the second end of first controllable switch connects the electrostatic
A pin of device is protected, the first end of second controllable switch connects the second pin of the chip, and described second can
The control terminal of control switch is connected with the second end of second controllable switch and is connected to one of the electrostatic protection device and draws
Foot, first and second described controllable switch is N-type TFT, control terminal, the first end of first and second switch
And second end respectively corresponds the grid, source electrode and drain electrode of the N-type TFT.
Wherein, which is characterized in that the array substrate test cell further includes several third pads, each third pad pair
The pin that the electrostatic protection device should be connected, for providing signal for picture element display area and turntable driving region, institute
Stating array substrate test circuit further includes the 4th pad and the 5th pad, and the 4th pad connects the first of the chip and draws
Foot is used for transmission the cut-in voltage end signal, and the 5th pad connects the second pin of the chip, is used for transmission described
Voltage end signal is closed, insulant is covered on the 4th and the 5th pad, is removed when using the described 4th and five pads
The insulant being covered on the 4th and the 5th pad.
In order to solve the above technical problems, another technical solution used in the present invention is：A kind of flat display apparatus is provided,
The flat display apparatus includes any of the above-described array substrate test circuit.
The beneficial effects of the invention are as follows：It is in contrast to the prior art, the array substrate of the invention tests circuit
By the on or off of first and second controllable switch of the unidirectionally controlled unit, so that in the chip operation, institute
It states the cut-in voltage end signal of chip output and closes voltage end signal will not be transferred to the array substrate test cell the
Three and the 4th pad, thus avoid the cut-in voltage end signal and the closing voltage end signal exposed in air, and
When the array substrate test cell works, by the third and the 4th pad and the chip by cut-in voltage end signal and
It closes voltage end signal and is transferred to the panel, work normally the panel, avoid causing shadow to the signal in chip with this
It rings, and then increases product parsing duration and reduce the stability of product.
Detailed description of the invention
Fig. 1 is the circuit diagram of the array substrate test circuit of the prior art；
Fig. 2 is the circuit diagram of the first embodiment of array substrate test circuit of the invention；
Fig. 3 is the equivalent circuit diagram of the unidirectionally controlled unit in Fig. 2；
Fig. 4 is the circuit diagram of the second embodiment of array substrate test circuit of the invention；
Fig. 5 is the equivalent circuit diagram of the unidirectionally controlled unit in Fig. 4；
Fig. 6 is the circuit diagram of the 3rd embodiment of array substrate test circuit of the invention；
Fig. 7 is the circuit diagram of the fourth embodiment of array substrate test circuit of the invention；
Fig. 8 is the structural schematic diagram of display panel of the invention；
Fig. 9 is the structural schematic diagram of flat display apparatus of the invention.
Specific embodiment
Referring to Fig. 1, being the circuit diagram of array substrate test circuit in the prior art.In 1 work of array substrate test cell
When making, the output of 2 no signal of chip, the cut-in voltage end that the pad 3,4 in the array substrate test cell 1 will receive at this time
Signal VGH and closing voltage end signal VGL passes through the corresponding cabling connected between electrostatic protection device 5 and the chip 2 and passes
It transports in panel, other pads in the array substrate test cell 1 are turntable driving area (area GOA) and the picture of the panel
Plain viewing area (area AA) provides signal；In the chip 2 work, nothing on the pad 3 and 4 of the array substrate test cell 1
External signal, the cut-in voltage end signal VGH and closing voltage end signal VGL that the chip 2 exports at this time pass through the electrostatic
Protection device 5 and corresponding cabling are supplied to the pad 3 and 4 in the array substrate test cell 1, lead to 2 work of chip
When making the cut-in voltage end signal VGH with the closing voltage end signal VGL is exposed in air can be in the chip 2
Signal impacts, and then increases the problem of product parses duration and reduces the stability of product.
Referring to Fig. 2, being the circuit diagram of the first embodiment of array substrate test circuit of the invention.As shown in Fig. 2, institute
Stating array substrate test circuit includes chip 20, and the chip 20 includes the first pin 21 and second pin 22, and described first draws
Foot 21 is used for transmission cut-in voltage end signal VGH, and the second pin 22, which is used for transmission, closes voltage end signal VGL；Unidirectional control
Unit 30 processed connects the first pin 21 and second pin 22 of the chip 20, is used for transmission the cut-in voltage end signal VGH
And the closing voltage end signal VGL；Array substrate test cell 10, the array substrate test cell 10 include electrostatic protection
Device 13, the first pad 11 and the second pad 12, the electrostatic protection device 13 connect the unidirectionally controlled unit 30, and described
One pad 11 and second pad 12 are connected respectively a pin of the electrostatic protection device 13, first pad
11 are used for transmission cut-in voltage end signal VGH, and second pad 12, which is used for transmission, closes voltage end signal VGL；When the core
When piece 20 works, the unidirectionally controlled unit 30 ends, the cut-in voltage end signal of the first pin 21 transmission of the chip 20
VGH cannot be by the unidirectionally controlled unit 30 and the output of the electrostatic protection device 13 to first pad 11 and the core
The closing voltage end signal VGL that the second pin 22 of piece 20 is transmitted can not pass through the unidirectionally controlled unit 30 and the electrostatic
Protect the output of device 13 to second pad 12；When the array substrate test cell 10 work, the unidirectionally controlled list
Member 30 is connected, and the cut-in voltage end signal VGH received is passed through the unidirectionally controlled unit 30 and institute by first pad 11
State electrostatic protection device 13 be transferred to the chip 20 the first pin 21 and second pad 12 by the closing received electricity
Pressure side signal VGL is transferred to the second of the chip 20 and is drawn by the unidirectionally controlled unit 30 and the electrostatic protection device 13
Foot 22.
In the present embodiment, the unidirectionally controlled unit 30 includes the first controllable switch T1 and the second controllable switch T2, institute
It states first and second controllable switch T1, T2 and respectively includes control terminal, first end and second end, the control of the first controllable switch T1
End processed is connected with the first end of the first controllable switch T1 and is connected to the first pin 21 of the chip 20, and described first can
The second end of control switch T1 is connected to a pin of the electrostatic protection device 13, the control terminal of the second controllable switch T2
It is connected with the first end of the second controllable switch T2 and is connected to the second pin 22 of the chip 20, described second controllably opens
The second end for closing T2 is connected to a pin of the electrostatic protection device 13, and the first controllable switch T1 is that N-type film is brilliant
Body pipe, the second controllable switch T2 are P-type TFT, control terminal, first end and the second end of the first switch T1
Respectively correspond the grid, source electrode and drain electrode of the N-type TFT, control terminal, the first end and of the second switch T2
Two ends respectively correspond the grid, source electrode and drain electrode of the P-type TFT.
Specifically, this described column tester substrate unit 10 further includes several third pads 16, and each third pad 16 is corresponding
A pin of the electrostatic protection device 13 is connected, for being pixel display area (area AA) domain and turntable driving region (GOA
Area) signal is provided.Specifically, several third pads include five, in other embodiments, can according to need setting institute
State the quantity of third pad.
Referring to Fig. 3, being the equivalent of unidirectionally controlled unit in the first embodiment of array substrate test circuit of the invention
Circuit diagram.As shown in figure 3, first and second controllable switch T1, T2 of the unidirectionally controlled unit 30 are equivalent to two and reversely set
First and second diode D1, the D2 set, the cathode of the first diode D1 connect the first pin 21 of the chip 20, institute
The anode for stating first diode D1 connects a pin of the electrostatic protection device 13, and the anode of the second diode D2 connects
Connect the second pin 22 of the chip 20, the cathode of the second diode D2 connect the electrostatic protection device 13 one draws
Foot.When described first or described second diode D1, D2 work, had on the described first or second diode D1, D2
Voltage drop Vth, therefore at the outer plus cut-in voltage end on pad 11,12 of the first of the array substrate test cell 10 and two
When the signal VGH and closing voltage end signal VGL, need plus the voltage drop Vth, to guarantee to be supplied to the panel
The cut-in voltage end signal VGH and closing voltage end signal VGL is able to satisfy the normal work demand of the panel.
The working principle of the circuit of the present embodiment is as follows：In the chip 20 work, because described first is controllable
Switch T1 is equivalent to the first diode D1, and the second controllable switch T2 is equivalent to the second diode D2, i.e., quite
It is turned off in described first and second controllable switch T1, T2, therefore the cut-in voltage end signal VGH that the chip 20 exports
And the closing voltage end signal VGL cannot pass through described first and second controllable switch T1, T2 and the electrostatic protector
Part 13 is transferred to first and second pad 11,12 in the array substrate test cell 10, to avoid the cut-in voltage
End signal VGH and the closing voltage end signal VGL are exposed in air in the chip 20 when the chip 20 works
Signal impact；In the array substrate test cell 10 work, because the first controllable switch T1 is equivalent to institute
First diode D1 is stated, the second controllable switch T2 is equivalent to the second diode D2, that is, described first and
Two controllable switch T1, T2 are both turned on, therefore first and second pad 11,12 of the array substrate test cell 10 receives
Cut-in voltage end signal VGH and close voltage end signal VGL by the electrostatic protection device 13 and it is described first and second can
Control switch T1, T2 are transferred in the panel, so that the panel works normally.
Referring to Fig. 4, being the circuit diagram of the second embodiment of array substrate test circuit of the invention.The array substrate
The difference place of the second embodiment and above-mentioned first embodiment of testing circuit is：The unidirectionally controlled unit 30 includes first
Controllable switch T1 and the second controllable switch T2, described first and second controllable switch T1, T2 respectively include control terminal, first end and
Second end, the control terminal of the first controllable switch T1 are connected with the first end of the first controllable switch T1 and are connected to described
First pin 21 of chip 20, the second end of the first controllable switch T1 connect the electrostatic protection device 13 one draw
Foot, the first end of the second controllable switch T2 connect the second pin 22 of the chip 20, the second controllable switch T2's
Control terminal is connected with the second end of the second controllable switch T2 and is connected to a pin of the electrostatic protection device 13, institute
Stating first and second controllable switch T1, T2 is N-type TFT, the control terminal of described first and second switch T1, T2,
One end and second end respectively correspond the grid, source electrode and drain electrode of the N-type TFT.
Referring to Fig. 5, be in the second embodiment of this column substrate test circuit of the invention unidirectionally controlled unit 30 etc.
Imitate circuit diagram.As shown in figure 5, first and second controllable switch T1, T2 of the unidirectionally controlled unit 30 are equivalent to two reversely
First and second diode D1, the D2 being arranged, the cathode of the first diode D1 connect the first pin 21 of the chip 20,
The anode of the first diode D1 connects a pin of the electrostatic protection device 13, the anode of the second diode D2
The second pin 22 of the chip 20 is connected, the cathode of the second diode D2 connects one of the electrostatic protection device 13
Pin.When described first or described second diode D1, D2 work, meeting on the described first or second diode D1, D2
There is voltage drop Vth, therefore the outer plus described unlatching electricity on first and second pad 11,12 of the array substrate test cell 10
When the pressure side signal VGH and closing voltage end signal VGL, need plus the voltage drop Vth, to guarantee to be supplied to the face
The cut-in voltage end signal VGH of the plate and closing voltage end signal VGL is able to satisfy the normal work demand of the panel.
The working principle of the circuit of the present embodiment is as follows：In the chip 20 work, because described first is controllable
Switch T1 is equivalent to the first diode D1, and the second controllable switch T2 is equivalent to the second diode D2, i.e., quite
It is turned off in described first and second controllable switch T1, T2, therefore the cut-in voltage end signal VGH that the chip 20 exports
And the closing voltage end signal VGL cannot pass through described first and second controllable switch T1, T2 and the electrostatic protector
Part 13 is transferred to first and second pad 11,12 in the array substrate test cell 10, to avoid the cut-in voltage
End signal VGH and the closing voltage end signal VGL are exposed in air in the chip 20 when the chip 20 works
Signal impact；In the array substrate test cell 10 work, because the first controllable switch T1 is equivalent to institute
First diode D1 is stated, the second controllable switch T2 is equivalent to the second diode D2, that is, described first and
Two controllable switch T1, T2 are both turned on, therefore first and second pad 11,12 of the array substrate test cell 10 receives
Cut-in voltage end signal VGH and close voltage end signal VGL by the electrostatic protection device 13 and it is described first and second can
Control switch T1, T2 are transferred in the panel, so that the panel works normally.
Referring to Fig. 6, being the circuit diagram of the 3rd embodiment of array substrate test circuit of the invention.The array substrate
The difference place of the 3rd embodiment and above-mentioned first embodiment of testing circuit is：The array substrate tests circuit
4th pad 14 and the 5th pad 15, the 4th pad 14 connect the first pin 21 of the chip 20, are used for transmission described
Cut-in voltage end signal VGH, the 5th pad 15 connect the second pin 22 of the chip 20, are used for transmission the closing electricity
Pressure side signal VGL covers insulant on the 4th and the 5th pad 14,15, prevents that the 4th and the 5th weldering is being not used
The cut-in voltage end signal VGH and the closing voltage end signal VGL are exposed in air when disk 14,15, and are needing to make
The cut-in voltage end signal VGH and closing voltage end signal VGL is measured with the 4th and the 5th pad 14,15
When, the insulant being covered on the 4th and the 5th pad need to only be removed by external force.
Referring to Fig. 7, being the circuit diagram of the fourth embodiment of array substrate test circuit of the invention.The array substrate
The difference place of the fourth embodiment and above-mentioned second embodiment of testing circuit is：The array substrate tests circuit
4th pad and the 5th pad 14,15, the 4th pad 14 connect the first pin 21 of the chip 20, are used for transmission described
Cut-in voltage end signal VGH, the 5th pad 15 connect the second pin 22 of the chip 20, are used for transmission the closing electricity
Pressure side signal VGL covers insulant on the 4th and the 5th pad 14,15, prevents that the 4th and the 5th weldering is being not used
The cut-in voltage end signal VGH and the closing voltage end signal VGL are exposed in air when disk 14,15, and are needing to make
The cut-in voltage end signal VGH and closing voltage end signal VGL is measured with the 4th and the 5th pad 14,15
When, the insulant being covered on the 4th and the 5th pad need to only be removed by external force.
Referring to Fig. 8, being a kind of structural schematic diagram of display panel of the present invention.The display panel includes array above-mentioned
Substrate test circuit, is arranged in the area WOA of the bottom of the display panel, and the display panel further includes the area AA, the area GOA,
The area Fanout, the area WOA, the area IC, the area FPC.Wherein, array substrate test circuit is used for after array substrate completion, to array
The electrical property of substrate is tested；The area AA is used for the display of pixel；The area GOA, i.e. Gate On Array, it is thin in panel for generating
The gate drive signal of film transistor TFT；The area Fanout is connect for chip with the cabling of the area AA data line；The area WOA, i.e. Wire
On Array, the connection for cabling around panel；The area IC, for the welding of chip, by circuit in chip drives panel and
Thin film transistor (TFT) TFT；The area FPC connects cell phone mainboard by flexible circuit board for the welding of flexible circuit board.
Referring to Fig. 9, for a kind of structural schematic diagram of flat display apparatus of the present invention.Before the flat display apparatus includes
The array substrate stated tests circuit and display panel, other devices and function and existing plane in the flat display apparatus are aobvious
The device and function of showing device are identical, and details are not described herein.Wherein, the flat display apparatus is LCD or OLED.
Array substrate test circuit by the conducting of first and second controllable switch of the unidirectionally controlled unit or
Cut-off, so that the cut-in voltage end signal and closing voltage end signal of the chip output will not pass in the chip operation
It is defeated by the third and the 4th pad of the array substrate test cell, to avoid the cut-in voltage end signal and the closing
Voltage end signal is exposed in air, and in array substrate test cell work, passes through the third and the 4th pad
And cut-in voltage end signal and closing voltage end signal are transferred to the panel by the chip, work normally the panel,
It avoids impacting the signal in chip with this, and then increases product parsing duration and reduce the stability of product.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (10)
1. a kind of array substrate tests circuit, which is characterized in that the array substrate tests circuit and includes：
Chip, the chip include the first pin and second pin, and first pin is used for transmission cut-in voltage end signal, institute
It states second pin and is used for transmission closing voltage end signal；
Unidirectionally controlled unit connects the first pin and second pin of the chip, is used for transmission the cut-in voltage end signal
And the closing voltage end signal；And
Array substrate test cell, the array substrate test cell include electrostatic protection device, the first pad and the second pad,
The electrostatic protection device connects the unidirectionally controlled unit, and first pad and second pad are connected respectively institute
A pin of electrostatic protection device is stated, first pad is used for transmission cut-in voltage end signal, and second pad is used for
Voltage end signal is closed in transmission；When the chip operation, the unidirectionally controlled unit cut-off, the first pin of the chip is passed
Defeated cut-in voltage end signal cannot be exported by the unidirectionally controlled unit and the electrostatic protection device to first weldering
The closing voltage end signal of the second pin of disk and chip transmission can not be by the unidirectionally controlled unit and described quiet
Electric protective component is exported to second pad；When array substrate test cell work, the unidirectionally controlled unit is led
Logical, the cut-in voltage end signal received is passed through the unidirectionally controlled unit and the electrostatic protection device by first pad
The closing voltage end signal received is passed through the unidirectional control by the first pin and second pad for being transferred to the chip
Unit processed and the electrostatic protection device are transferred to the second pin of the chip.
2. array substrate according to claim 1 tests circuit, which is characterized in that the unidirectionally controlled unit includes first
Controllable switch and the second controllable switch, first and second described controllable switch respectively include control terminal, first end and second end, institute
The control terminal for stating the first controllable switch is connected with the first end of first controllable switch and is connected to the first of the chip and draws
Foot, the second end of first controllable switch are connected to a pin of the electrostatic protection device, second controllable switch
Control terminal be connected with the first end of second controllable switch and be connected to the second pin of the chip, described second is controllable
The second end of switch is connected to a pin of the electrostatic protection device, and first controllable switch is N-type TFT,
Second controllable switch is P-type TFT, and the control terminal of first controllable switch, first end and second end are right respectively
Answer the grid, source electrode and drain electrode of the N-type TFT, control terminal, first end and the second end of second controllable switch
Respectively correspond the grid, source electrode and drain electrode of the P-type TFT.
3. array substrate according to claim 1 tests circuit, which is characterized in that the unidirectionally controlled unit includes first
Controllable switch and the second controllable switch, first and second described controllable switch respectively include control terminal, first end and second end, institute
The control terminal for stating the first controllable switch is connected with the first end of first controllable switch and is connected to the first of the chip and draws
Foot, the second end of first controllable switch connect a pin of the electrostatic protection device, second controllable switch
First end connects the second pin of the chip, the control terminal of second controllable switch and the second of second controllable switch
End is connected and is connected to a pin of the electrostatic protection device, first and second described controllable switch is that N-type film is brilliant
Body pipe, control terminal, first end and the second end of first and second controllable switch respectively correspond the N-type TFT
Grid, source electrode and drain electrode.
4. array substrate according to claim 1 or 2 or 3 tests circuit, which is characterized in that the array substrate test is single
Member further includes several third pads, and each third pad is correspondingly connected with a pin of the electrostatic protection device, for being picture
Plain display area and turntable driving region provide signal.
5. array substrate according to claim 4 tests circuit, which is characterized in that the array substrate test circuit also wraps
The 4th pad and the 5th pad are included, the 4th pad connects the first pin of the chip, is used for transmission the cut-in voltage
End signal, the 5th pad connect the second pin of the chip, are used for transmission the closing voltage end signal, and the described 4th
And the 5th cover insulant on pad, removal is covered on the 4th and the 5th pad when using the described 4th and five pads
On insulant.
6. a kind of display panel, which is characterized in that the display panel includes array substrate test circuit, and the array substrate is surveyed
Trying circuit includes：
Chip, the chip include the first pin and second pin, and first pin is used for transmission cut-in voltage end signal, institute
It states second pin and is used for transmission closing voltage end signal；
Unidirectionally controlled unit connects the first pin and second pin of the chip, is used for transmission the cut-in voltage end signal
And the closing voltage end signal；And
Array substrate test cell, the array substrate test cell include electrostatic protection device, the first pad and the second pad,
The electrostatic protection device connects the unidirectionally controlled unit, and first pad and second pad are connected respectively institute
A pin of electrostatic protection device is stated, first pad is used for transmission cut-in voltage end signal, and second pad is used for
Voltage end signal is closed in transmission；When the chip operation, the unidirectionally controlled unit cut-off, the first pin of the chip is passed
Defeated cut-in voltage end signal cannot be exported by the unidirectionally controlled unit and the electrostatic protection device to first weldering
The closing voltage end signal of the second pin of disk and chip transmission can not be by the unidirectionally controlled unit and described quiet
Electric protective component is exported to second pad；When array substrate test cell work, the unidirectionally controlled unit is led
Logical, the cut-in voltage end signal received is passed through the unidirectionally controlled unit and the electrostatic protection device by first pad
The closing voltage end signal received is passed through the unidirectional control by the first pin and second pad for being transferred to the chip
Unit processed and the electrostatic protection device are transferred to the second pin of the chip.
7. display panel according to claim 6, which is characterized in that the unidirectionally controlled unit includes the first controllable switch
And second controllable switch, first and second described controllable switch respectively include control terminal, first end and second end, described first can
The control terminal of control switch is connected with the first end of first controllable switch and is connected to the first pin of the chip, and described the
The second end of one controllable switch is connected to a pin of the electrostatic protection device, the control terminal of second controllable switch with
The first end of second controllable switch is connected and is connected to the second pin of the chip, and the second of second controllable switch
End is connected to a pin of the electrostatic protection device, and first controllable switch is N-type TFT, and described second can
Control switch is P-type TFT, and control terminal, first end and the second end of first controllable switch respectively correspond the N-type
Grid, source electrode and the drain electrode of thin film transistor (TFT), control terminal, first end and the second end of second controllable switch respectively correspond institute
State the grid, source electrode and drain electrode of P-type TFT.
8. display panel according to claim 6, which is characterized in that the unidirectionally controlled unit includes the first controllable switch
And second controllable switch, first and second described controllable switch respectively include control terminal, first end and second end, described first can
The control terminal of control switch is connected with the first end of first controllable switch and is connected to the first pin of the chip, and described the
The second end of one controllable switch connects a pin of the electrostatic protection device, the first end connection of second controllable switch
The second pin of the chip, the control terminal of second controllable switch are connected and connect with the second end of second controllable switch
It is connected to a pin of the electrostatic protection device, first and second described controllable switch is N-type TFT, and described
One and second controllable switch control terminal, first end and second end respectively correspond the grid of the N-type TFT, source electrode and
Drain electrode.
9. display panel described according to claim 6 or 7 or 8, which is characterized in that the array substrate test cell further includes
Several third pads, each third pad are correspondingly connected with a pin of the electrostatic protection device, for being pixel display area
Domain and turntable driving region provide signal, and the array substrate test circuit further includes the 4th pad and the 5th pad, and described the
Four pads connect the first pin of the chip, are used for transmission the cut-in voltage end signal, described in the 5th pad connection
The second pin of chip is used for transmission the closing voltage end signal, covers insulant on the 4th and the 5th pad, when making
With the insulant that removal is covered on the 4th and the 5th pad when the described 4th and five pads.
10. a kind of flat display apparatus, which is characterized in that the flat display apparatus includes as described in claim 1-5 is any
Array substrate test circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610580608.5A CN105976745B (en) | 2016-07-21 | 2016-07-21 | Array substrate tests circuit, display panel and flat display apparatus |
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| CN201610580608.5A CN105976745B (en) | 2016-07-21 | 2016-07-21 | Array substrate tests circuit, display panel and flat display apparatus |
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| CN105976745B true CN105976745B (en) | 2018-11-23 |
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| CN108873506B (en) * | 2017-05-10 | 2021-01-22 | 京东方科技集团股份有限公司 | Motherboard and test method of motherboard |
| CN109147630A (en) * | 2018-09-25 | 2019-01-04 | 武汉华星光电半导体显示技术有限公司 | A kind of GOA detection circuit and its test method |
| CN114333681B (en) * | 2018-09-27 | 2023-08-18 | 武汉天马微电子有限公司 | Display panel and display device |
| CN112992022A (en) * | 2020-09-24 | 2021-06-18 | 重庆康佳光电技术研究院有限公司 | Display panel and detection method |
| GB2614817B (en) * | 2021-10-14 | 2024-02-14 | Hkc Corp Ltd | Test circuit of display panel and display device |
| CN113643636B (en) * | 2021-10-14 | 2022-01-07 | 惠科股份有限公司 | Test circuit of display panel and display device |
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