CN109192120B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN109192120B CN109192120B CN201811129565.4A CN201811129565A CN109192120B CN 109192120 B CN109192120 B CN 109192120B CN 201811129565 A CN201811129565 A CN 201811129565A CN 109192120 B CN109192120 B CN 109192120B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and aims to adjust the number and arrangement mode of electrostatic protection circuits so as to be better suitable for a narrow-frame display panel. The display panel comprises a display area and a non-display area, the non-display area comprises an upper side non-display area and a lower side non-display area which are arranged along a first direction, and the lower side non-display area is provided with a driving chip; a data line; the gating circuit is arranged on one side, close to the display area, of the driving chip in the non-display area on the lower side, connected with the data signal input wiring and the at least two data lines, and connected with the driving chip; the electrostatic protection circuit is arranged between the driving chip and the gating circuit; the electrostatic protection circuit comprises a first diode and a second diode, the first diode and the second diode are connected with the data signal input wiring, and the first diode and the second diode are arranged along the second direction. The display panel is used for realizing picture display.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a display panel and a display device.
[ background of the invention ]
The display panel comprises a display area and a non-display area, and a plurality of data lines are distributed in the display area. In the production process of the display panel, a large amount of static charges are accumulated in the display panel due to some external factors, and then the electrostatic discharge phenomenon is caused. During electrostatic discharge, static charges are transferred in a short time, so that extremely high electrostatic current is generated, and further, data signals transmitted on the data lines are influenced. In order to overcome the above problems, a plurality of electrostatic discharge protection circuits are disposed in the non-display region of the display panel.
In the related art, the electrostatic discharge protection circuit is generally disposed in the non-display area of the lower side, and one data line corresponds to one electrostatic discharge protection circuit. However, as the current display panels are more and more designed with narrow frames, the arrangement space of the electrostatic protection circuit is insufficient when the width of the non-display area on the lower side is compressed.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a display panel and a display device, which are used to adjust the number and arrangement of the electrostatic protection circuits so as to better adapt to a display panel with a narrow frame.
In one aspect, an embodiment of the present invention provides a display panel, where the display panel includes:
the display device comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises an upper non-display area and a lower non-display area which are arranged along a first direction, and a driving chip is arranged in the lower non-display area;
the data lines are arranged in the display area;
the gating circuits are arranged on one side, close to the display area, of the driving chip in the lower non-display area, and are electrically connected with data signal input wires and at least two data wires respectively, and the data signal input wires are electrically connected with the driving chip;
the electrostatic protection circuits are arranged between the driving chip and the gating circuit; each electrostatic protection circuit comprises a first diode and a second diode, wherein the first diode and the second diode are respectively electrically connected with the data signal input wiring, the first diode and the second diode are sequentially arranged along a second direction, and the second direction is intersected with the first direction.
In another aspect, an embodiment of the present invention provides a display device, which includes the above display panel.
One of the above technical solutions has the following beneficial effects:
in the technical solution provided in the embodiment of the present invention, based on the connection relationship between the data line, the gate circuit, the data signal input trace, and the electrostatic protection circuit, when the voltage signal is transmitted to the data line through the data signal input trace, if the voltage signal is greater than the first threshold voltage signal or less than the second threshold voltage signal, it indicates that the voltage signal is an abnormal electrostatic voltage signal, and at this time, the abnormal electrostatic voltage signal may be conducted away by the electrostatic protection circuit, thereby preventing the abnormal electrostatic voltage signal from being transmitted to the data line, causing interference to the data signal transmitted on the data line, and causing damage to devices in the display panel. If the voltage signal is smaller than the first threshold voltage signal and larger than the second threshold voltage signal, the voltage signal is a normal data voltage signal, at this time, the electrostatic protection circuit does not work, and the data voltage signal is transmitted to the corresponding data line through the gating circuit to charge the data line.
Further, compared with the prior art in which one data line corresponds to one electrostatic protection circuit, in the embodiment of the present invention, one electrostatic protection circuit is electrically connected to one data signal input trace by disposing the electrostatic protection circuit between the gate circuit and the driving chip, so that when each gate circuit includes n switching units, only one electrostatic protection circuit needs to be disposed corresponding to n data lines, and the number of electrostatic protection circuits can be reduced to a great extent on the premise of ensuring that each data line is subjected to electrostatic protection. Therefore, in the layout design of the electrostatic protection circuit, the first diode and the second diode are sequentially arranged along the second direction, and the space length occupied by the film layer where the electrostatic protection circuit is located in the second direction can be increased, so that the space length occupied by the film layer where the electrostatic protection circuit is located in the first direction is reduced.
In summary, with the technical solution provided by the embodiments of the present invention, based on the connection relationship and the position relationship among the gate circuit, the data signal input trace, and the esd protection circuit, the number of the esd protection circuits disposed in the lower non-display area can be reduced to a great extent. And, through further making first diode and second diode in the electrostatic protection circuit arrange along the second direction in proper order, can reduce the space length that the rete that the electrostatic protection circuit is located took in the first direction to reduce the width that the electrostatic protection circuit took up in the non-display area of downside, make its display panel who is better adapted to narrow frame design.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a gate circuit and an ESD protection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a corresponding structure of the film layer of FIG. 2;
fig. 4 is a schematic circuit diagram of an esd protection structure according to an embodiment of the present invention;
FIG. 5 is a schematic view of the corresponding film structure of FIG. 4;
FIG. 6 is a schematic circuit diagram of an ESD protection structure according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a corresponding film structure of FIG. 6;
FIG. 8 is a schematic view of another corresponding film structure of FIG. 6;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that although the terms first and second may be used to describe the diodes in the embodiments of the present invention, the diodes should not be limited to these terms. These terms are only used to distinguish the diodes from each other. For example, the first diode may also be referred to as a second diode, and similarly, the second diode may also be referred to as a first diode, without departing from the scope of embodiments of the present invention.
An embodiment of the present invention provides a display panel, as shown in fig. 1, fig. 1 is a schematic circuit structure diagram of the display panel provided in the embodiment of the present invention, and the display panel includes a display area 1 and a non-display area 2 surrounding the display area 1, where the non-display area 2 includes an upper non-display area 3 and a lower non-display area 4 arranged along a first direction, and a driving chip 5 is disposed in the lower non-display area 4.
The display panel further includes a plurality of Data lines Data, a plurality of gate circuits 6, and a plurality of electrostatic discharge protection circuits 7. Wherein, the Data line Data is arranged in the display area 1; the gating circuit 6 is arranged on one side, close to the display area 1, of the driving chip 5 IN the non-display area 4 on the lower side, the gating circuit 6 is electrically connected with the Data signal input wiring IN and the at least two Data lines Data respectively, and the Data signal input wiring IN is electrically connected with the driving chip 5; the electrostatic protection circuit 7 is arranged between the driving chip 5 and the gating circuit 6; each electrostatic protection circuit 7 includes a first diode 8 and a second diode 9, wherein the first diode 8 and the second diode 9 are electrically connected to the data signal input trace IN, the first diode 8 and the second diode 9 are sequentially arranged along a second direction, and the second direction intersects with the first direction.
As shown in fig. 2 and fig. 3, fig. 2 is a schematic circuit structure diagram of a gate circuit and an electrostatic protection circuit according to an embodiment of the present invention, and fig. 3 is a schematic film structure diagram corresponding to fig. 2, each gate circuit 6 includes n switch units 10, and each switch unit 10 includes a control terminal, an input terminal, and an output terminal. The input ends of n switch units 10 IN each gate circuit 6 are electrically connected to a Data signal input trace IN, the output end of each switch unit 10 is electrically connected to a Data line Data, and the control end of the ith switch unit 10 IN the gate circuits 6 is electrically connected to a switch control trace SWi. Specifically, the switching unit 10 may include one or more thin film transistors connected in series.
Taking as an example that each gate circuit 6 shown in fig. 2 includes two switching units 10, one charge cycle of the Data line Data includes the 1 st period and the 2 nd period.
IN the 1 st period, the 1 st switch unit 10 IN the plurality of gate circuits 6 is turned on by the turn-on control signal provided by the switch control trace SW1, and when the voltage signal transmitted on the data signal input trace IN is greater than the first threshold voltage signal or less than the second threshold voltage signal, the first diode 8 or the second diode 9 IN the electrostatic protection circuit 7 is turned on, and the voltage signal is conducted away through the turned-on first diode 8 or the turned-on second diode 9; when the voltage signal transmitted on the Data signal input trace IN is smaller than the first threshold voltage signal and larger than the second threshold voltage signal, the first diode 8 and the second diode 9 IN the electrostatic protection circuit 7 are not turned on, and the voltage signal is transmitted to the Data line Data electrically connected to the first diode through the 1 st switch unit 10 to charge the Data line Data.
IN the period 2, the 2 nd switch unit 10 IN the plurality of gate circuits 6 is turned on by the turn-on control signal provided by the switch control trace SW2, and when the voltage signal transmitted on the data signal input trace IN is greater than the first threshold voltage signal or less than the second threshold voltage signal, the first diode 8 or the second diode 9 IN the electrostatic protection circuit 7 is turned on, and the voltage signal is conducted away through the turned-on first diode 8 or the turned-on second diode 9; when the voltage signal transmitted on the Data signal input trace IN is smaller than the first threshold voltage signal and larger than the second threshold voltage signal, the first diode 8 and the second diode 9 IN the electrostatic protection circuit 7 are not turned on, and the voltage signal is transmitted to the Data line Data electrically connected to the voltage signal through the 2 nd switch unit 10 to charge the Data line Data.
As can be seen from the above, IN the display panel provided IN the embodiment of the present invention, based on the connection relationship between the Data line Data, the gate circuit 6, the Data signal input trace IN and the electrostatic protection circuit 7, when the voltage signal is transmitted to the Data line Data through the Data signal input trace IN, if the voltage signal is greater than the first threshold voltage signal or less than the second threshold voltage signal, it indicates that the voltage signal is an abnormal electrostatic voltage signal, and at this time, the abnormal electrostatic voltage signal can be conducted away through the electrostatic protection circuit 7, so as to prevent the abnormal electrostatic voltage signal from being transmitted to the Data line Data, causing interference to the Data signal transmitted on the Data line Data, and causing damage to devices IN the display panel. If the voltage signal is smaller than the first threshold voltage signal and larger than the second threshold voltage signal, it indicates that the voltage signal is a normal Data voltage signal, and at this time, the electrostatic protection circuit 7 does not operate, and the Data voltage signal is transmitted to the corresponding Data line Data through the gate circuit 6, so as to charge the Data line Data.
Further, compared with the prior art IN which one Data line Data corresponds to one electrostatic protection circuit 7, IN the embodiment of the present invention, one electrostatic protection circuit 7 is electrically connected to one Data signal input trace IN by disposing the electrostatic protection circuit 7 between the gate circuit 6 and the driving chip 5, so that when each gate circuit 6 includes n switching units 10, only one electrostatic protection circuit 7 needs to be disposed corresponding to n Data lines Data, and the number of electrostatic protection circuits 7 can be reduced to a great extent on the premise of ensuring that each Data line Data is subjected to electrostatic protection. Based on this, with reference to fig. 3, in the layout design of the electrostatic protection circuit 7, by sequentially arranging the first diode 8 and the second diode 9 along the second direction, the spatial length occupied by the film layer on which the electrostatic protection circuit 7 is located in the second direction can be increased, so as to reduce the spatial length occupied by the film layer on which the electrostatic protection circuit 7 is located in the first direction.
IN summary, with the display panel according to the embodiment of the present invention, based on the connection relationship and the position relationship between the gate circuit 6, the data signal input trace IN and the esd protection circuit 7, the number of the esd protection circuits 7 disposed IN the lower non-display area 4 can be reduced to a great extent. Moreover, by further arranging the first diode 8 and the second diode 9 in the electrostatic protection circuit 7 in sequence along the second direction, the space length occupied by the film layer where the electrostatic protection circuit 7 is located in the first direction can be reduced, so that the width occupied by the electrostatic protection circuit 7 in the lower non-display area 4 is reduced, and the display panel is better adapted to a narrow-frame design.
Optionally, referring to fig. 2 and fig. 3 again, the first diode 8 and the second diode 9 may be respectively disposed at two sides of the data signal input trace IN electrically connected thereto.
Compared with the first diode 8 and the second diode 9 which are arranged at the same side of the data signal input line IN electrically connected with the first diode 8 and the second diode 9, the first diode 8 and the second diode 9 are respectively arranged at two sides of the data signal input line IN, so that the wiring length electrically connected with the data signal input line IN IN the first diode 8 and the second diode 9 can be reduced IN the layout design of the first diode 8 and the second diode 9, namely, the space occupied by the wiring is reduced, and the space length occupied by the film layer where the electrostatic protection circuit 7 is arranged IN the first direction is further reduced.
Optionally, as shown in fig. 4 and 5, fig. 4 is a schematic circuit structure diagram of an electrostatic protection structure provided in an embodiment of the present invention, fig. 5 is a schematic film structure diagram corresponding to fig. 4, and each of the first diode 8 and the second diode 9 includes a gate G, a first pole S, and a second pole D. A first pole S of the first diode 8 is electrically connected with the data signal input line IN, and a gate G and a second pole D of the first diode 8 are both electrically connected with the first electrostatic transmission line PL 1; the first pole S of the second diode 9 is electrically connected to the second electrostatic transmission line PL2, and the gate G and the second pole D of the second diode 9 are both electrically connected to the data signal input line IN. The first pole S is a source, and the second pole D is a drain.
It should be noted that, in the embodiment of the present invention, the first diode 8 and the second diode 9 are substantially diode structures formed by short-circuiting thin film transistors by gates G and second poles D, the short-circuited gates G and second poles D in the thin film transistors form one poles of the diodes, and the first pole S in the thin film transistors forms the other pole of the diodes.
When the voltage signal transmitted on the data signal input line IN is greater than the first threshold voltage signal on the first electrostatic transmission line PL1, the voltage signal is an abnormal electrostatic voltage signal, at this time, the first diode 8 is turned on, and the abnormal electrostatic voltage signal is transmitted to the first electrostatic transmission line PL1 through the first electrode S and the second electrode D of the first diode 8 and is released through the first electrostatic transmission line PL 1. When the voltage signal transmitted on the data signal input line IN is smaller than the second threshold voltage signal on the second electrostatic transmission line PL2, the voltage signal is an abnormal electrostatic voltage signal, at this time, the second diode 9 is turned on, and the abnormal electrostatic voltage signal is transmitted to the second electrostatic transmission line PL2 through the second pole D and the first pole S of the second diode 9 and is released through the second electrostatic transmission line PL 2. When the voltage signal transmitted on the Data signal input line IN is smaller than the first threshold voltage signal and larger than the second threshold voltage signal, the voltage signal is a normal Data voltage signal, at this time, the first diode 8 and the second diode 9 IN the electrostatic protection circuit 7 are not conductive, and the Data voltage signal is transmitted to the corresponding Data line Data through the gating circuit 6 to charge the Data line Data.
By adopting the arrangement mode, based on the specific structures of the first diode 8 and the second diode 9 and the connection relation with the Data signal input line IN, the first electrostatic transmission line PL1 and the second electrostatic transmission line PL2, when the voltage signal transmitted on the Data signal input line IN is an abnormal electrostatic voltage signal, the abnormal electrostatic voltage signal can be released out through the first diode 8 and the first electrostatic transmission line PL1 or through the second diode 9 and the second electrostatic transmission line PL2, thereby avoiding the transmission of the abnormal electrostatic voltage signal to the Data line Data and influencing the Data signal transmitted on the Data line Data and the devices IN the display panel. When the voltage signal transmitted on the Data signal input line IN is a normal Data voltage signal, the first diode 8 and the second diode 9 are not turned on, and therefore, the first diode 8 and the second diode 9 do not affect the normal charging of the Data line Data.
Alternatively, as shown in fig. 6, fig. 6 is a schematic circuit diagram of another electrostatic protection structure according to an embodiment of the present invention, and the gates G of the first diode 8 and the second diode 9 each include a first gate G1 and a second gate G2 electrically connected to each other. That is, the first diode 8 and the second diode 9 are each formed by a double-gate thin film transistor shorted by the first gate G1, the second gate G2, and the second diode D.
The channel length, i.e., the aspect ratio, of a double-gate transistor is larger than that of a single-gate thin film transistor
Smaller according to the formula of leakage current
The width to length ratio is known
The smaller the leakage current of the transistor, the lower the active carrier concentration in the transistor and thus the more stable the performance of the transistor. Therefore, the first diode 8 and the second diode 9 are formed by using the double-gate thin film transistor, so that the working stability of the first diode 8 and the second diode 9 can be improved, and the working stability of the electrostatic protection circuit 7 is further ensured.
Alternatively, as shown in fig. 7, fig. 7 is a schematic diagram of the film structure corresponding to fig. 6, the first gate G1 and the second gate G2 of the first diode 8 are arranged along a first direction, and the first gate G1 and the second gate G2 of the second diode 9 are arranged along the first direction.
The first diode 8 and the second diode 9 are arranged along the second direction, and the first gate G1 and the second gate G2 in the first diode 8 and the second diode 9 are arranged along the first direction, so that the space length occupied by the film layer where the electrostatic protection circuit 7 is located in the first direction can be reduced on the premise of improving the working stability of the first diode 8 and the second diode 9, and the display panel is better adapted to narrow-frame design.
Referring to FIG. 7 again, the dimension of the ESD protection circuit 7 in the first direction is Y1, Y1 is 50 μm ≦ 70 μm. It should be noted that the size of the electrostatic protection circuit 7 in the first direction refers to a length of a space occupied by a film layer where the electrostatic protection circuit 7 is located in the first direction in layout design.
In the prior art, since one electrostatic protection circuit 7 is correspondingly disposed on each Data line Data, the size of each electrostatic protection circuit 7 in the second direction is very small, and is only close to the size of a half of a sub-pixel in the second direction, so that the size of the electrostatic protection circuit 7 in the first direction can only be increased, and generally, the size of the current electrostatic protection circuit 7 in the first direction is larger than 70 μm, and generally ranges from 70 μm to 100 μm. In the embodiment of the present invention, since the number of the esd protection circuits 7 can be reduced to a great extent, by improving the layout of the esd protection circuit 7, the first diode 8 and the second diode 9 are arranged along the second direction, and the first gate G1 and the second gate G2 of the first diode 8 and the second diode 9 are arranged along the first direction, the size of the esd protection circuit 7 in the first direction can be reduced to 50 μm to 70 μm, and thus, the esd protection circuit can be better suitable for a display panel with a narrow frame.
Alternatively, as shown in fig. 8, fig. 8 is another schematic diagram of the film structure corresponding to fig. 6, in which the first gate G1 and the second gate G2 of the first diode 8 are arranged along the second direction, and the first gate G1 and the second gate G2 of the second diode 9 are arranged along the second direction.
Referring to fig. 8 again, when the gate G includes the first gate G1 and the second gate G2, in the layout process of the gate G, the region where the gate G is located is rectangular. By arranging the first gate G1 and the second gate G2 along the second direction, the longer edge of the region where the gate G film is located can be extended along the second direction, and the shorter edge can be extended along the first direction. Therefore, with such a configuration, on the premise of improving the working stability of the first diode 8 and the second diode 9, the space length occupied by the film layer where the gate G is located in the first direction can be further reduced, so that the space length occupied by the electrostatic protection circuit 7 in the first direction is further reduced, and the electrostatic protection circuit can be applied to a display panel with a narrower frame.
Referring again to FIG. 8, the ESD protection circuit 7 has a dimension Y2 in the first direction, Y2 < 50 μm. In the embodiment of the present invention, the first diode 8 and the second diode 9 in the esd protection circuit 7 are arranged along the second direction, and the first gate G1 and the second gate G2 in the first diode 8 and the second diode 9 are arranged along the second direction, so that the size of the esd protection circuit 7 in the first direction can be further reduced to less than 50 μm, and thus, the space occupied by the esd protection circuit 7 in the lower non-display area 4 is narrower, the width of the lower non-display area 4 of the display panel can be further reduced, and the narrow-frame design can be better realized.
Of course, in other alternative embodiments of the present invention, the first gate G1 and the second gate G2 of the first diode 8 may be arranged along the first direction, and the first gate G1 and the second gate G2 of the second diode 9 may be arranged along the second direction, or the first gate G1 and the second gate G2 of the first diode 8 may be arranged along the second direction, and the first gate G1 and the second gate G2 of the second diode 9 may be arranged along the first direction. Compared with the prior art, in the embodiment of the invention, the size of the esd protection circuit 7 in the first direction can be reduced by arranging the first diode 8 and the second diode 9 in the second direction, and therefore, when the first gate G1 and the second gate G2 of the first diode 8 and the second diode 9 adopt the above two arrangements, the size of the esd protection circuit 7 in the first direction can be reduced compared with the prior art.
It is understood that the non-display area 2 of the display panel is generally provided with a first fixed voltage signal terminal (not shown) and a second fixed voltage signal terminal (not shown). Optionally, the first electrostatic transmission line PL1 is electrically connected to the first fixed voltage signal terminal, and the second electrostatic transmission line PL2 is electrically connected to the second fixed voltage signal terminal, at this time, the first threshold voltage signal is a voltage signal provided by the first fixed voltage signal terminal, and the second threshold voltage signal is a voltage signal provided by the second fixed voltage signal terminal.
The first electrostatic transmission line PL1 is electrically connected to the first fixed voltage signal terminal, and when the abnormal electrostatic voltage signal is released through the first electrostatic transmission line PL1, the abnormal electrostatic voltage signal can be specifically transmitted to the first fixed voltage signal terminal through the first electrostatic transmission line PL1, and then transmitted to the circuit board, and finally flows into the ground through the casing of the display panel. The second electrostatic transmission line PL2 is electrically connected to the second fixed voltage signal terminal, and when the abnormal electrostatic voltage signal is released through the second electrostatic transmission line PL2, the abnormal electrostatic voltage signal can be specifically transmitted to the second fixed voltage signal terminal through the second electrostatic transmission line PL2, then transmitted to the circuit board, and finally flows into the ground through the housing of the display panel, so that the abnormal electrostatic voltage signal is prevented from flowing into the display panel through the data line, and the electrostatic protection capability of the display panel is improved.
Optionally, the first fixed voltage signal terminal is a high level signal terminal, and the second fixed voltage signal terminal is a low level signal terminal. The high level signal terminal and the low level signal terminal are used for supplying power to a driving circuit in the display panel, such as a gate scanning circuit.
Optionally, the data signal input trace IN corresponding to each gate circuit 6 is electrically connected to one electrostatic protection circuit 7. Each Data signal input line IN is correspondingly provided with one electrostatic protection circuit 7, so that when the Data signal input line IN is charged to the Data line Data corresponding to the Data signal input line IN IN a time-sharing manner, the electrostatic protection circuit 7 can perform electrostatic protection on all the Data lines Data IN the display panel, and the electrostatic protection capability of the display panel is further improved.
As shown in fig. 9, fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device includes the display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments, and is not described herein again. Of course, the display device shown in fig. 9 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
Since the display device provided by the embodiment of the invention includes the display panel 100, the display device can reduce the number of the electrostatic protection circuits arranged in the lower non-display area to a great extent, and reduce the space length occupied by the film layer of the electrostatic protection circuit in the first direction, thereby reducing the width occupied by the electrostatic protection circuit in the lower non-display area, and being better suitable for the display device with a narrow-frame design.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (11)
1. A display panel, comprising:
the display device comprises a display area and a non-display area surrounding the display area, wherein the non-display area comprises an upper non-display area and a lower non-display area which are arranged along a first direction, and a driving chip is arranged in the lower non-display area;
the data lines are arranged in the display area;
the gating circuits are arranged on one side, close to the display area, of the driving chip in the lower non-display area, and are electrically connected with data signal input wires and at least two data wires respectively, and the data signal input wires are electrically connected with the driving chip;
the electrostatic protection circuits are arranged between the driving chip and the gating circuit;
each electrostatic protection circuit comprises a first diode and a second diode, wherein the first diode and the second diode are respectively electrically connected with the data signal input wiring, the first diode and the second diode are sequentially arranged along a second direction, and the second direction is intersected with the first direction;
the first diode and the second diode both comprise a grid electrode, a first electrode and a second electrode, and both the first diode and the second diode are double-grid transistors;
the first pole of the first diode is electrically connected with the data signal input wiring, and the grid electrode and the second pole of the first diode are both electrically connected with the first electrostatic transmission wiring;
the first pole of the second diode is electrically connected with the second electrostatic transmission wiring, and the grid electrode and the second pole of the second diode are both electrically connected with the data signal input wiring.
2. The display panel according to claim 1, wherein the first diode and the second diode are respectively disposed at two sides of the data signal input trace electrically connected thereto.
3. The display panel according to claim 1, wherein the gate electrode comprises a first gate electrode and a second gate electrode which are electrically connected;
the first and second gates of the first diode are arranged along the first direction, and the first and second gates of the second diode are arranged along the first direction.
4. The display panel according to claim 3, wherein the electrostatic protection circuit has a size of Y1, 50 μm Y1 μm 70 μm in the first direction.
5. The display panel according to claim 1, wherein the gate electrode comprises a first gate electrode and a second gate electrode which are electrically connected;
the first and second gates of the first diode are arranged along the second direction, and the first and second gates of the second diode are arranged along the second direction.
6. The display panel according to claim 5, wherein the electrostatic protection circuit has a size of Y2 in the first direction, Y2 < 50 μm.
7. The display panel of claim 1, wherein the first electrode is a source electrode and the second electrode is a drain electrode.
8. The display panel of claim 1, wherein the first electrostatic transmission trace is electrically connected to a first fixed voltage signal terminal, and the second electrostatic transmission trace is electrically connected to a second fixed voltage signal terminal.
9. The display panel according to claim 8, wherein the first fixed voltage signal terminal is a high level signal terminal, and the second fixed voltage signal terminal is a low level signal terminal.
10. The display panel according to claim 1, wherein the data signal input trace corresponding to each of the gate circuits is electrically connected to one of the esd protection circuits.
11. A display device comprising the display panel according to any one of claims 1 to 10.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210160197.XA CN114333682B (en) | 2018-09-27 | 2018-09-27 | Display panel and display device |
| CN202210160192.7A CN114333681B (en) | 2018-09-27 | 2018-09-27 | Display panel and display device |
| CN201811129565.4A CN109192120B (en) | 2018-09-27 | 2018-09-27 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811129565.4A CN109192120B (en) | 2018-09-27 | 2018-09-27 | Display panel and display device |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210160197.XA Division CN114333682B (en) | 2018-09-27 | 2018-09-27 | Display panel and display device |
| CN202210160192.7A Division CN114333681B (en) | 2018-09-27 | 2018-09-27 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
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| CN109192120A CN109192120A (en) | 2019-01-11 |
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| CN114333682A (en) * | 2018-09-27 | 2022-04-12 | 武汉天马微电子有限公司 | Display panel and display device |
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| CN110969943A (en) * | 2019-11-27 | 2020-04-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN110941125B (en) * | 2019-12-16 | 2022-11-04 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
| CN111243429B (en) * | 2020-02-13 | 2021-11-09 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN111562704A (en) * | 2020-05-06 | 2020-08-21 | Oppo（重庆）智能科技有限公司 | Display module assembly, electronic equipment and display screen assembly |
| CN113570989B (en) * | 2021-07-30 | 2024-04-05 | 友达光电（昆山）有限公司 | Test circuit and display panel |
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| Publication number | Publication date |
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| CN109192120A (en) | 2019-01-11 |
| CN114333681B (en) | 2023-08-18 |
| CN114333681A (en) | 2022-04-12 |
| CN114333682A (en) | 2022-04-12 |
| CN114333682B (en) | 2023-08-18 |
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