KR20190140629A - Light emttting display device - Google Patents

Abstract

The present application provides a light emitting display device for preventing the spread of burnt and fall melting phenomenon by detecting a crack and short in a display panel. According to the present application, the light emitting display device comprises: a display panel on which a plurality of scan lines and a plurality of data lines are disposed and a plurality of pixels defined by the plurality of scan lines and data lines are arranged; and a defect detection unit disposed adjacent to the edge of the display panel. The defect detection unit is electrically connected to ESD wire disposed at the edge of the display panel.

Description

Light-emitting display device {LIGHT EMTTTING DISPLAY DEVICE}

The present application relates to a light emitting display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. As a display device, various display devices such as a liquid crystal display (LCD) and a light emitting display (LED) are used. The light emitting display device may be classified into an organic light emitting display device using an organic light emitting layer as a light emitting element, a light emitting diode display device using a micro light emitting diode as a light emitting element, and the like. The light emitting display device is capable of driving low voltage, has a thin shape, has an excellent viewing angle, and has a fast response speed.

The light emitting display device includes a display panel in which a plurality of pixels are arranged in a matrix form. The display panel receives scan signals from the scan driver circuit and drives data voltages from the data driver circuit to drive each of the pixels. In addition, the display panel receives a plurality of power voltages from a power supply.

When a crack occurs in the light emitting display device due to an external shock, power lines of the display panel may be short circuited to each other. For example, the high potential voltage line supplied with the high potential voltage from the power supply and the low potential voltage line supplied with the low potential voltage from the power supply may be shorted to each other. In this case, an overcurrent flows from the high potential power line to the low potential power line, and a burnt may occur due to the overcurrent.

An object of the present application is to provide a light emitting display device which detects crack generation and short generation of a display panel and prevents spreading of burnt and pole melting phenomena.

In the light emitting display device according to the present application, a plurality of scan lines and a plurality of data lines are disposed, and a display panel in which a plurality of pixels defined by the plurality of scan lines and the plurality of data lines are arranged is disposed adjacent to an edge of the display panel. And a defect detection unit, wherein the defect detection unit is electrically connected to an ESD wiring disposed at an edge of the display panel.

The light emitting display device according to the present application has an effect of preventing the spread of the burnt phenomenon and the fall melt phenomenon.

1 is a perspective view illustrating a light emitting display device according to a first embodiment of the present application.
2 is a block diagram illustrating a light emitting display device according to a first embodiment of the present application.
FIG. 3 is a circuit diagram for describing a connection structure of the defect detector illustrated in FIG. 1.
4A and 4B are circuit diagrams for describing a normal driving mode and a sensing mode of the first defect detection unit illustrated in FIG. 3.
5A and 5B are circuit diagrams for describing a normal driving mode and a sensing mode of the second defect detection unit illustrated in FIG. 3.
6 is a circuit diagram illustrating a defect detector according to a second embodiment of the present application.

Advantages and features of the present application, and a method of accomplishing the same will be apparent with reference to the examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below, but may be implemented in various different forms, only examples of the present application are intended to complete the disclosure of the present application, and the general knowledge in the art to which the present application belongs. It is provided to fully inform the person having the scope of the invention, this application is defined only by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the example of the present application are exemplary, and thus the present application is not limited to the illustrated items. Like reference numerals refer to like elements throughout. In addition, in describing the present application, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present application, the detailed description thereof will be omitted.

In the case where 'comprises', 'haves', 'consists of' and the like mentioned in the present application are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of the two parts is described as 'on', 'upon', 'lower', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

In the case of a description of a temporal relationship, for example, if the temporal after-term relationship is described as 'after', 'following', 'after', 'before', or the like, 'directly' or 'direct' This may include cases that are not continuous unless used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be a second component within the technical spirit of the present application.

The "first horizontal axis direction", the "second horizontal axis direction" and the "vertical axis direction" are not to be interpreted only as geometric relationships in which the relationship between each other is vertical, and the range in which the configuration of the present application can function. It may mean having a wider direction than within.

The term "at least one" should be understood to include all combinations which can be presented from one or more related items. For example, the meaning of "at least one of a first item, a second item, and a third item" means two items of the first item, the second item, and the third item, as well as two of the first item, the second item, and the third item, respectively. It can mean a combination of all items that can be presented from more than one.

Each of the features of the various examples of the present application may be combined or combined with each other, in part or in whole, various technically interlocking and driving, each of the examples may be implemented independently of each other or may be implemented together in an association. .

Hereinafter, a preferred example of a light emitting display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are shown in different drawings.

1 is a perspective view illustrating a light emitting display device according to a first embodiment of the present application, and FIG. 2 is a block diagram illustrating a light emitting display device according to a first embodiment of the present application.

1 and 2, a light emitting display device according to a first embodiment of the present application may be an organic light emitting display device using an organic light emitting device as a light emitting device or a micro light emitting display device using a micro light emitting diode as a light emitting device. .

The light emitting display device according to the first exemplary embodiment of the present application includes the display panel 110, the data driver 120, the source drive IC 121, the flexible film 122, the scan driver 130, and the source circuit board 140. , A defect detector 141, a flexible cable 150, a control circuit board 160, a timing controller 170, a memory 180, and a voltage supply unit 190.

The display panel 110 includes a first substrate 111 and a second substrate 112. The first substrate 111 may be formed of a glass substrate or a plastic film, and the second substrate 112 may be formed of a glass substrate, a plastic film, an encapsulation film, or a barrier film.

The display panel 110 includes a display area AA and a non-display area NA provided around the display area AA. The display area AA is an area in which a plurality of pixels P are formed to display an image. The display panel 110 includes a plurality of data lines (D1 to Dm, m is a positive integer of 2 or more), a plurality of reference voltage lines (R1 to Rp, p is a positive integer of 2 or more), and a plurality of scan lines (S1 to Sn and n are positive integers of 2 or more) and a plurality of sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may cross the scan lines S1 to Sn and the sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing signal lines SE1 to SEn may be parallel to each other.

Each of the plurality of pixels P may be any one of the plurality of data lines D1 to Dm, any one of the plurality of reference voltage lines R1 to Rp, any one of the plurality of scan lines S1 to Sn, and a plurality of pixels. It may be connected to any one of the sensing signal lines SE1 to SEn. Each of the plurality of pixels P of the display panel 10 may include a light emitting device and a plurality of transistors for supplying current to the light emitting device. A detailed description of each of the plurality of pixels P of the display panel 10 will be described later.

The data driver 120 may include at least one source drive integrated circuit (IC) 121. In FIG. 2, the data driver 120 includes eight source drive ICs 121, but the number of source drive ICs 121 is not limited thereto.

The source drive IC 121 may be mounted on the flexible film 122. The flexible film 122 may be a tape carrier package or a chip on film. The flexible film 122 may be bent or bent. The flexible film 122 may be attached to the lower substrate 111 and the source circuit board 140. The flexible film 122 may be attached onto the first substrate 111 by a tape automated bonding (TAB) method using an anisotropic conductive film, and thus, the source drive IC 121 may connect to the data line ( D1 ~ Dm).

The source drive IC 121 receives compensation video data in the display mode, converts the compensation video data into emission data voltages according to the data timing control signal DCS, and applies the compensation video data to the plurality of data lines D1 to Dm. The display mode is a mode in which the pixels P emit light to display an image. The light emission data voltage is a voltage for emitting the light emitting element of the pixel P with a predetermined brightness.

The scan driver 130 includes a scan signal output unit 131 and a sensing signal output unit 132.

The scan signal output unit 131 is connected to the plurality of scan lines S1 to Sn to apply a scan signal. The scan signal output unit 131 generates a scan signal according to the scan timing control signal SCS input from the timing controller 170 and applies the scan signal to the scan lines S1 to Sn.

The sensing signal output unit 132 is connected to the plurality of sensing signal lines SE1 to SEn to apply a sensing signal. The sensing signal output unit 132 generates a sensing signal according to the sensing timing control signal SENCS input from the timing controller 170 and applies the sensing signal to the sensing signal lines SE1 to SEn.

The scan signal output unit 131 and the sensing signal output unit 132 may be directly formed in the non-display area NA of the display panel 110 by using a gate driver in panel (GIP) method including a plurality of transistors. Alternatively, the scan signal output unit 131 and the sensing signal output unit 132 may be formed in the form of a driving chip and mounted on the gate flexible film attached to the first substrate 111 of the display panel 110. have. In this case, the scan signal output unit 131 and the sensing signal output unit 132 may be formed in a chip form like an integrated circuit.

The source circuit board 140 includes a first connector 151 for connecting to the flexible cable 150. The source circuit board 140 may be connected to the flexible cable 150 through the first connector 151. The source circuit board 50 may be a flexible printed circuit board or a printed circuit board.

The defect detector 141 may be disposed on the source circuit board 140. The defect detector 141 is formed to detect a crack or a short that occurs in the display panel 110 and to prevent burnt phenomenon that the display panel burns out. Herein, the crack may be a phenomenon in which the display panel 110 is cracked or a part of the display panel 110 is cracked due to an external impact, and the display panel 110 is cracked. It can be seen as a broad concept that includes all of these phenomena. In addition, the power lines disposed on the display panel 110 may be shorted or opened due to a short crack or the like, and an overcurrent or abnormal current may flow through the wiring. A detailed principle of detecting the crack or the short that occurs in the display panel 110 by the defect detector 141 will be described later.

The control circuit board 160 includes a second connector 152 for connecting to the flexible cable 150. The control circuit board 160 may be connected to the flexible cable 150 through the second connector 152.

In FIG. 1, the source circuit board 140 and the control circuit board 160 are connected to the plurality of flexible cables 150 through the plurality of first connectors 151 and the plurality of second connectors 152. It is not limited. That is, each of the source circuit board 140 and the control circuit board 160 may be connected to one flexible cable 150 through one first connector 151 and one second connector 152.

The timing controller 170 receives digital video data and timing signals from a system on chip. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 170 generates control signals for controlling the operation timing of the source drive IC 121, the scan signal output unit 131, and the sensing signal output unit 132. The control signals include a data timing control signal DCS for controlling the operation timing of the source drive IC 121, a scan timing control signal SCS for controlling the operation timing of the scan signal output unit 131, and a sensing signal output. And a sensing timing control signal SENCS for controlling the operation timing of the unit 132.

The voltage supply unit 180 generates a reference voltage VREF from the main power applied from the main power supply of the system circuit board and supplies the reference voltage VREF to the source drive IC 121 of the data driver 120. In addition, the power supply unit 180 may generate and supply the first power voltage EVDD corresponding to the high potential voltage and the second power voltage EVSS corresponding to the low potential voltage from the main power supply to the display panel 110. The driving voltages may be supplied to the source drive IC 121, the scan signal output unit 131, the sensing signal output unit 132, and the timing controller 170.

The timing controller 170 and the voltage supply unit 180 may be mounted on the control circuit board 160. In this case, the timing controller 170 and the voltage supply unit 180 may be formed in a chip form like an integrated circuit. The control circuit board 160 may be a flexible printed circuit board or a printed circuit board.

FIG. 3 is a circuit diagram for describing a connection structure of the defect detector of FIG. 1.

Referring to FIG. 3, the defect detector 141 is electrically connected to an ESD wiring 310 disposed at an edge of the display panel 110.

The ESD wiring 310 is disposed at an edge of the display panel 110, specifically, in the non-display area NA of the display panel 110. The ESD wiring 310 may be formed to surround the outer edge of the display panel 110 in order to prevent a defect in the display panel 110 due to static electricity. Since the ESD wiring 310 may take out a charge to the ground, the display panel 110 may be improved by emitting external static electricity or static electricity generated internally. The ESD wiring 310 includes a first ESD wiring 310a and a second ESD wiring 310b.

The first ESD wiring 310a is disposed to surround the edge of the display panel 110. The first ESD wire 310a may be disposed to surround the outermost edge of the non-display area NA of the display panel 110 to emit static electricity generated in the display panel 110.

The second ESD wiring 310b is disposed between the first ESD wiring 310a and the plurality of pixels. In detail, the second ESD wiring 310b is disposed in the non-display area NA of the display panel 110, and is disposed between the first ESD wiring 310a and the active area AA of the display panel 110. It may surround the edge of the panel 110.

As such, the ESD wire 310 may effectively discharge static electricity by utilizing two wires surrounding the edge of the display panel 110, that is, the first ESD wire 310a and the second ESD wire 310b. .

The defect detector 141 may be disposed to be adjacent to the edge of the display panel 110 and electrically connected to the ESD wiring 310 disposed at the edge of the display panel 110. As described above, the defect detector 141 may be disposed on the source circuit board 140, and the ESD wiring 310 may pass through the flexible film 122 and the defect detector 141 disposed on the source circuit board 140. Is electrically connected to the The defect detector 141 includes a first defect detector 141a and a second defect detector 141b.

The first defect detector 141a is electrically connected to the first ESD wiring 310a. The first defect detector 141a may be electrically connected to the first ESD wiring 310a disposed at the outermost edge of the display panel 110 to detect cracks occurring in the display panel 110. Since the bezel area at the outermost edge of the display panel 110 is relatively vulnerable to external shock, the first ESD wiring 310a is likely to be disconnected. The first defect detection unit 141a is configured to generate a defect signal when the first ESD wire 310a is disconnected, so that the burnt phenomenon and the polarization film melt as the crack occurs in the display panel 110. This diffusion can be prevented beforehand. The first defect detector 141a may include a first floating transistor FET1, a second floating transistor FET2, a first resistor R1, a second resistor R2, a first voltage source V1, and a first capacitor C1. ) And a first zener diode Z1.

The first floating transistor FET1 and the second floating transistor FET2 are turned on / off by a turn-on / off signal applied to the gate electrode, and the first defect detection unit 141a is first and second floating. As the transistors FET1 and FET2 are turned on / off, the transistors FET1 and FET2 may operate in a normal driving mode and a sensing mode. The gate electrode of the first floating transistor FET1 is connected to a switching electrode (not shown) for applying a turn-on / off signal, the source electrode is connected to ground, and the drain electrode is connected to the first ESD wiring 310a. do. The gate electrode of the second floating transistor FET2 is connected to a switching electrode (not shown) that applies a turn-on / off signal, the source electrode is connected to ground, and the drain electrode is connected to the first ESD wiring 310a. do.

The first resistor R1 is connected to the first voltage source V1 and the first ESD wiring 310a, and the second resistor R2 is connected to the ground and the first ESD wiring 310a. The first defect detector 141a may detect whether or not a crack has occurred by comparing a voltage value between both ends of the first resistor R1 and the second resistor R2 in the sensing mode.

The first voltage source V1 is connected to ground and the first resistor R1. Since the first voltage source V1 applies a constant voltage in the sensing mode, the first defect detector 141a may measure voltage values of both ends of the first resistor R1 and the second resistor R2.

The first capacitor C1 is connected to the ground and the first ESD wiring 310a and stores a voltage applied to the second resistor R2 in the sensing mode.

The first xenodiode Z1 may be connected to the ground and the first ESD wiring 310a and may protect the device by preventing a current from flowing in an overvoltage.

The second defect detection unit 141b is electrically connected to the second ESD wiring 310b. The second defect detection unit 141b is electrically connected to the first ESD wiring 310a disposed at the outermost edge of the display panel 110 and the second ESD wiring 310b disposed between the plurality of pixels, thereby to display the display panel ( The short of the wirings provided in the 110 may be detected. For example, the second ESD wiring 310b is disposed between the first power supply voltage EVDD wire and the second power supply voltage EVSS wire, and thus, the first power supply voltage EVDD wire and the second power supply voltage EVSS wire. The short of the liver can be detected. The second defect detection unit 141b is configured to generate a defect signal when a short occurs between the first power supply voltage EVDD wiring and the second power supply voltage EVSS wiring, and thus, may generate a defect signal. As the short between the second power supply voltage EVSS wires occurs, the spreading of the burnt phenomenon and the pole melting phenomenon in which the polarizing film is melted may be prevented. The second defect detector 141b includes a third floating transistor FET3, a third resistor R3, a second capacitor C2, and a second zener diode Z2.

The third floating transistor FET3 may cause the second defect detection unit 141b to operate in a normal driving mode and a sensing mode by a turn-on / off signal applied to the gate electrode. The gate electrode of the third floating transistor FET3 is connected to a switching electrode (not shown) that applies a turn-on / off signal, the source electrode is connected to ground, and the drain electrode is connected to the second ESD wiring 310b. do.

The third resistor R3 is connected to the ground and the second ESD wiring 310b, and the second defect detector 141b measures the voltage value of both ends of the third resistor R3 in the sensing mode to detect whether a short occurs. can do.

The second capacitor C2 is connected to the ground and the second ESD wiring 310b and stores a voltage applied to the third resistor R3 in the sensing mode.

The second xenodiode Z2 is connected to the ground and the second ESD wiring 310b and may protect the device by preventing a current from flowing in an overvoltage.

4A and 4B are circuit diagrams for describing a normal driving mode and a sensing mode of the first defect detection unit.

 4A shows the normal driving mode of the first defect detection unit 141a. The first defect detector 141a turns on the first floating transistor FET1 and the second floating transistor FET2 in the normal driving mode. When the first floating transistor FET1 and the second floating transistor FET2 are turned on, current flows to the first floating transistor FET1 and the second floating transistor FET2 having very small resistances, as shown. The first ESD wiring 310a forms a closed circuit and is connected to the ground. At this time, since the first ESD wire 310a can take out the charge to the ground, it is possible to effectively discharge the static electricity.

4B illustrates a sensing mode of the first defect detector 141a. The first defect detector 141a turns off the first floating transistor FET1 and the second floating transistor FET2 in the sensing mode. When the first floating transistor FET1 and the second floating transistor FET2 are turned off, as illustrated, the first resistor R1 and the second resistor R2 are connected in series. In this case, when a constant voltage is applied from the first voltage source V1, a voltage value applied to the first resistor R1 and the second resistor R2 according to the resistance values of the first resistor R1 and the second resistor R2. This may appear constant. However, when a crack occurs in the display panel 110 and the first ESD wiring 310a is disconnected, a voltage value applied to the first resistor R1 and the second resistor R2 may change. The first defect detector 141a measures a voltage value applied to the first resistor R1 and the second resistor R2, and generates a first defect signal when there is a variation in the voltage value. As such, when the crack occurs in the display panel 110, the first defect detection unit 141a may generate the first defect signal. Thus, the crack occurs in the display panel 110, thereby causing burnt or pole melting. It can be prevented from occurring and spreading.

5A and 5B are circuit diagrams for describing a normal driving mode and a sensing mode of the second defect detection unit.

 5A shows a normal driving mode of the second defect detection unit 141b. The first defect detector 141b turns on the third floating transistor FET3 in the normal driving mode. When the third floating transistor FET3 is turned on, current flows to the third floating transistor FET3 having a very low resistance, and as shown, the second ESD wiring 310b forms a closed circuit and is connected to ground. do. At this time, since the second ESD wire 310b can take out the charge to the ground, it is possible to effectively discharge the static electricity.

5B illustrates a sensing mode of the second defect detector 141b. The second defect detector 141b turns off the third floating transistor FET3 in the sensing mode. When the third floating transistor FET3 is turned off, the third resistor R1, the second capacitor C1, and the second genodiode Z1 are disposed between the second ESD wiring 310b and the ground as shown. Are connected in parallel. At this time, the voltage value of both ends of the first resistor (R1) may be measured as 0V in the normal range. However, when a short occurs due to a foreign matter between the first power supply voltage EVDD wiring and the second power supply voltage EVSS wiring, the short circuit is disposed between the first power supply voltage EVDD wiring and the second power supply voltage EVSS. A specific voltage may be applied to the second ESD wiring 310b. When a specific voltage is applied to the second ESD wiring 310b, the voltage value of the third resistor R3 may be measured to have a voltage value other than 0V. In this case, the second defect detector 141b may detect the second defect signal. Create As described above, since the second defect detection unit 141b can generate the second defect signal when a short occurs, the second defect detection unit 141b can prevent the burnt phenomenon and the fall melt phenomenon from occurring due to the short.

As such, the light emitting display device according to the exemplary embodiment of the present application may detect that a defect occurs in the display panel 110 through the defect detector 141. In this case, the first defect detection signal generated by the first defect detection unit 141a and the second defect detection signal generated by the second defect detection unit 141b are transmitted to the timing controller 170. The timing controller 170 generates an abnormal signal when the first defect detection signal or the second defect detection signal is received. The abnormal signal generated by the timing controller 170 is transferred to the main power supply to block the main power supply from outputting the main power. Therefore, the light emitting display device according to an exemplary embodiment of the present application may block the output of the main power supply through the defect detection unit 141 when a crack occurs in the display panel 110 or a short circuit occurs. The spreading of the melting phenomenon can be prevented.

In addition, since the light emitting display device according to an example of the present application is designed to prevent static electricity in a normal driving mode without adding a separate mask, and to prevent spreading of burnt phenomenon and pole melting phenomenon in a sensing mode, in terms of manufacturing cost It is advantageous.

6 is a circuit diagram illustrating a defect detector according to a second embodiment of the present application.

Referring to FIG. 6, the defect detector according to the second embodiment of the present application includes a data voltage detector 125 and a reference voltage detector 126 included in the drive IC 121. Before describing the configuration of the data voltage detector 125 and the reference voltage detector 126, the pixel P and the source drive IC 121 will be described.

The source drive IC 121 receives compensation video data in the display mode, converts the compensation video data into emission data voltages according to the data timing control signal DCS, and applies the compensation video data to the plurality of data lines D1 to Dm. The source drive IC 121 includes a buffer 123, a data voltage detector 125, and a reference voltage detector 126.

The buffer 123 applies a data voltage to the plurality of data lines D1 to Dm. In this case, the buffer 123 may allow data voltages to be simultaneously applied to the plurality of data lines D1 to Dm.

The data voltage detector 125 detects an abnormality of the data voltage, and the reference voltage detector 126 detects an abnormality of the reference voltage. Detailed description thereof will be described later.

 The pixel P may be connected to the data line D, the reference voltage line R, the scan line S, and the sensing signal line S. The pixel P includes a light emitting element EL, a driving transistor Tdr, a switching transistor Tsw, a sensing transistor Tse, and a third capacitor C3.

The light emitting element EL emits light according to a current supplied through the driving transistor Tdr. The light emitting device EL may be implemented as an organic light emitting diode or a micro light emitting diode. When the light emitting device EL is formed of an organic light emitting diode, the light emitting device EL includes an anode electrode, a hole transporting layer, an organic light emitting layer, and an electron transporting layer. ), And a cathode electrode. When voltage is applied to the anode electrode and the cathode electrode, the light emitting device EL moves to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combines and emits light in the organic light emitting layer. The anode electrode of the light emitting device EL may be connected to the source electrode of the driving transistor Tdr, and the cathode electrode may be connected to the second power supply voltage EVDD wiring to which a low potential voltage lower than the high potential voltage is supplied.

The driving transistor Tdr adjusts the current flowing from the first power supply voltage EVDD wiring to which the first power supply voltage EVDD is supplied to the light emitting device EL according to the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor Tdr is connected to the first electrode of the switching transistor Tsw, the source electrode is connected to the anode electrode of the light emitting element EL, and the drain electrode is a first power supply voltage to which a high potential voltage is applied. (EVDD) wiring can be connected.

The switching transistor Tsw is turned on by the scan signal to connect the data line D to the gate electrode of the driving transistor Tdr.

The sensing transistor Tse is turned on by the sensing signal to connect the reference voltage line R to the source electrode of the driving transistor Tdr.

The third capacitor C3 is formed between the gate electrode and the source electrode of the driving transistor Tdr. The third capacitor C3 stores the difference voltage between the gate voltage and the source voltage of the driving transistor Tdr.

The data voltage detector 125 detects whether or not the voltage of the data line D is abnormal. The data voltage detector 125 senses and compares the voltage V2 of the input terminal of the buffer 123 with the voltage V3 of the output terminal of the buffer 123. If it is in the normal range, a high signal comes out of the comparator, and the high signal does not pass through the low pass filter (LPF) and is not written to the horizontal synchronization reference counter (HBC). However, when a crack occurs in the display panel 110 due to an external shock and the first power voltage EVDD wiring, the data line D, and the reference voltage line R are connected, the output terminal of the buffer 123, that is, the data line, is connected. Excessive voltage is applied to (D). Therefore, the low signal is output from the comparator, and the low signal passes through the low pass filter LPF and is recorded in the horizontal synchronous reference counter HBC. At this time, the horizontal synchronization reference counter (HBC) may generate a third defect signal when the number of times recorded in the counter based on one horizontal synchronization period is more than a predetermined range.

The reference voltage detector 126 detects whether or not the voltage of the reference voltage line R is abnormal. The reference voltage detector 126 senses the voltage of the reference voltage line R and compares the voltage with the preset voltage V4. When in the normal range, a high signal is output from the comparator, and the high signal does not pass through the low pass filter (LPF) and is not written to the frame reference counter (FBC). However, when a crack occurs in the display panel 110 due to an external shock and the first power voltage EVDD wiring, the data line D, and the reference voltage line R are connected, excessive voltage is applied to the reference voltage line R. Is approved. Therefore, the low signal is output from the comparator, and the low signal passes through the low pass filter LPF and is written to the frame reference counter FBC. In this case, the frame reference counter FBC may generate the fourth defect signal when the number of times written in the counter based on one frame period is greater than or equal to a predetermined range.

As described above, the light emitting display device according to the second exemplary embodiment of the present application may detect that a defect occurs in the display panel 110 through the data voltage detector 125 and the reference voltage detector 126. At this time, the source drive IC 121 generates an error signal even if only one of the third defect detection signal and the fourth defect detection signal occurs. The error signal generated by the source drive IC 121 is transferred to the timing controller 170, and when the error controller receives the error signal, the timing controller 170 generates an abnormal signal. The abnormal signal generated by the timing controller 170 is transferred to the main power supply to block the main power supply from outputting the main power. Therefore, the light emitting display device according to the second exemplary embodiment of the present application may block the output of the main power supply through the defect detection unit when a crack occurs in the display panel 110 or a short circuit occurs. The phenomenon can be prevented from spreading.

The present application described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical details of the present application. It will be evident to those who have knowledge of. Therefore, the scope of the present application is represented by the following claims, and it should be construed that all changes or modifications derived from the meaning and scope of the claims and equivalent concepts thereof are included in the scope of the present application.

110: display panel 111: lower substrate
112: upper substrate 120: data driver
121: source drive IC 122: flexible film
130: scan driver 131: scan signal output unit
132: sensing signal output unit 140: source circuit board
150: flexible cable 160: control circuit board
170: timing controller 180: voltage supply unit

Claims (9)

A display panel in which a plurality of scan lines and a plurality of data lines are disposed and a plurality of pixels defined by the plurality of scan lines and the plurality of data lines are arranged;
A defect detector for detecting a crack or a short circuit of the display panel; And
An ESD wiring for dissipating static electricity generated in the display panel,
And the defect detector is electrically connected to the ESD wiring to detect a crack or a short circuit of the ESD wiring generated in the non-display area of the display panel. The method of claim 1,
A source drive IC applying a data voltage to the plurality of data lines;
A flexible film mounting the source drive IC; And
Further comprising a source circuit board connected to the flexible film,
And the defect detector is disposed on the source circuit board. The method of claim 1,
The ESD wiring,
First ESD wires surrounding edges of the display panel; And
A second ESD wire disposed between the first ESD wire and the plurality of pixels,
And the defect detection unit is electrically connected to the first ESD wiring and the second ESD wiring. The method of claim 3, wherein
The defect detection unit,
A first defect detector including first and second floating transistors; And
A second defect detection unit including a third floating transistor,
The first defect detection unit is electrically connected to the first ESD wiring,
And the second defect detector is electrically connected to the second ESD wiring. The method of claim 4, wherein
The first defect detector generates a first defect signal by detecting a crack of the display panel in a sensing mode,
And the second defect detector detects a short of the wiring of the display panel in a sensing mode and generates a second defect signal. The method of claim 5,
A timing controller for controlling an operation timing of the source drive IC;
And the timing controller generates an abnormal signal when the first defect signal or the second defect signal is applied. The method of claim 2,
The source drive IC,
A buffer for applying a data voltage to the plurality of data lines;
A data voltage detector configured to sense and compare a voltage at an input terminal and an output terminal of the buffer; And
And a reference voltage detector configured to sense a voltage supplied to the reference voltage line. The method of claim 7, wherein
The data voltage detector generates a third defect signal when an excessive voltage is applied to the data line,
And the reference voltage detector generates a fourth defect signal when an excessive voltage is applied to the reference voltage line. The method of claim 8,
A timing controller for controlling an operation timing of the source drive IC;
And the timing controller generates an abnormal signal when the third defect signal or the fourth defect signal is applied.

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