KR102613421B1 - Chip on film and display device having the same - Google Patents

Abstract

The present invention relates to a chip-on film that can prevent short circuits from occurring due to migration of wires due to moisture permeation between wires, and a display device using the same. First bonding parts are disposed at a certain distance at opposite ends of the wires. and a base layer including a second bonding portion; IC mounted on the base layer and disposed between the first and second bonding parts: a plurality of signals arranged side by side in the base layer to pass through the first bonding part, the IC, and the second bonding part lines; at least one power voltage supply line disposed in parallel with the plurality of signal lines outside the IC of the base layer and passing through the first bonding part and the second bonding part; and a chip-on-film formed on the base layer and including a separation element disposed in at least some areas between neighboring ones of the plurality of signal lines and the at least one power supply voltage line.

Description

Chip on film and display device having the same {CHIP ON FILM AND DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a chip-on-film and a display device equipped with the same. In particular, it relates to a chip-on-film that can prevent short circuits between wires due to migration of wires, and a display device equipped with the same. .

Flat panel display devices (FPD) are used in various types of electronic products, including mobile phones, tablet PCs, and laptops. Flat panel displays include Liquid Crystal Display Devices (LCDs), Plasma Display Devices (PDPs), and Light Emitting Display Devices, and recently, electrophoretic displays (EPDs: Electrophoretic Display Device) is also widely used.

These flat display devices generally include a display panel for displaying images, a control PCB (Printed Circuit Board, PCB) having a control unit for controlling the display panel, a source PCB, and a chip-on-film (chip-on-film) connecting the display panel and the source PCB. Includes Chip On Film (COF).

Hereinafter, a conventional display device will be described in more detail with reference to FIGS. 1 to 4.

FIG. 1 is a block diagram schematically showing a conventional display device, FIG. 2 is an equivalent circuit diagram for one pixel of the display device of FIG. 1, and FIG. 3 shows the wiring arrangement of a portion of the chip-on-film shown in FIG. 1. It is a schematic plan view, and FIG. 4 is a cross-sectional view taken along line II' of FIG. 3. 1 to 4 show a conventional organic light emitting display device as an example, but hereinafter, for convenience, the display device will be used.

Referring to FIG. 1, a conventional display device includes a control PCB 20, a source PCB 22, a cable 21 connected to the source PCB 22 and the control PCB 20, the source PCB 22, and a liquid crystal display panel. It contains multiple source COFs (24) connected to (25).

The source COF 24 is electrically connected to the pads of the source PCB 22 and the data pads of the display panel 25. A data integrated circuit (hereinafter referred to as “IC”) 23 is mounted on the source COF 24.

Signal lines SL for transmitting digital video data and timing control signals from the control PCB 20 are formed on the source PCB 22.

Control circuits and data transmission circuits are mounted on the control PCB (20). This control PCB (20) supplies timing control signals for controlling the operation of the data IC (23) along with data to the data IC (23) of the source COF (24) through the cable (21) and the source PCB (22). do.

Recently, in accordance with the high-resolution requirements of display devices, power wiring along with various signal wiring are arranged at high density in a small area in the source COF 24. In particular, in the case of an organic light emitting display device, as shown in FIG. 2, not only a data signal transmission line (Vdata) for transmitting video data, but also a high potential supply line (Vdd) that supplies a high potential power voltage and a base potential. A base potential supply line (Vss) that supplies is also formed.

Referring to FIG. 2, in a conventional organic light emitting display device, pixels are formed in each area where gate lines GL and data lines DL intersect, and a pixel circuit is formed in each pixel.

The pixel circuit includes a switching transistor (ST), a driving transistor (DT), a capacitor (C), and a light emitting element (OLED).

The switching transistor (ST) is switched according to the scan signal supplied to the gate line (GL) and supplies the data voltage (Vdata) supplied to the data line (DL) to the driving transistor (DT).

The driving transistor (DT) switches according to the data voltage (Vdata) supplied from the switching transistor (ST) and controls the current (Ioled) flowing from the high-potential power supply voltage (Vdd) to the light emitting device (OLED).

The capacitor C is connected to the gate terminal of the driving transistor DT, stores a voltage corresponding to the data voltage Vdata supplied to the gate terminal of the driving transistor DT, and operates the driving transistor DT with the stored voltage. Turn it on.

The light emitting element (OLED) is electrically connected between the driving transistor (DT) and the low-potential power supply voltage (Vss) and emits light by the current (Ioled) supplied from the driving transistor (DT). At this time, the current (Ioled) flowing through the light emitting device (OLED) is determined according to the voltage between the gate and source of the driving transistor (DT), that is, the threshold voltage and data voltage (Vdata) of the driving transistor (DT).

As described above, the pixel circuit of a conventional organic light emitting display device generates a current flowing from the high potential power supply voltage (Vdd) to the light emitting element (OLED) according to the data voltage (Vdata) supplied to the gate terminal of the driving transistor (DT). By controlling the size of the (Ioled), the light emitting element (OLED) is made to emit light, and accordingly, the image is displayed on the display panel.

Referring to Figures 3 and 4, a data signal supply line (Vdata) that supplies a data signal, and power supply lines (hereinafter referred to as Vdd and Vss) that supply a high potential power supply voltage (Vdd) and a base potential power supply voltage (Vss). ) are arranged at very narrow intervals on the same plane of the base layer (BL).

Accordingly, in the chip-on-film applied to a conventional display device, moisture penetration may occur through the opening exposed by removing the protective layer for connection to the pads of the display panel and the pads of the source PCB. Due to this moisture permeation, adjacent signal supply lines and power supply lines may unintentionally come into contact with each other due to migration, etc., and in this case, there is a problem that damage due to short circuit may occur.

Therefore, the present invention is intended to solve the above problems in which short circuits between wires may occur due to migration due to moisture permeation. The purpose of the present invention is to provide a chip-on-film that can prevent short-circuits between highly integrated wires on the chip-on-film and a display device using the same. do.

In order to achieve the above-described object, the chip-on-film according to the present invention includes a base layer including a first bonding portion and a second bonding portion, respectively disposed at a predetermined distance on both ends opposing each other; IC mounted on the base layer and disposed between the first and second bonding parts: a plurality of signals arranged side by side in the base layer to pass through the first bonding part, the IC, and the second bonding part lines; at least one power voltage supply line disposed in parallel with the plurality of signal lines outside the IC of the base layer and passing through the first bonding part and the second bonding part; and separation elements formed on the base layer and disposed in at least some areas between neighboring ones of the plurality of signal lines and the at least one power supply voltage line.

In the above configuration, the separation element may be at least one of a concave portion and a convex portion formed in the base layer.

In addition, the base layer is between the first bonding part and the second bonding part having an opening area exposing the plurality of signal lines and the at least one power voltage line, and the plurality of signal lines and the at least one power voltage line. It may further include a non-opening area having a protective layer covering at least one power voltage line.

Additionally, the separation element may be disposed in at least one area of the first bonding part and the second bonding part.

Alternatively, the separation element may be disposed in an opening area outside the first bonding part and the second bonding part.

Additionally, the separation element may be disposed in at least one area of the first bonding part and the second bonding part, and in an opening area outside the first bonding part and the second bonding part.

In order to achieve the above-described object, the chip-on film according to the present invention also includes a base layer including a first bonding portion and a second bonding portion respectively disposed at a predetermined distance on both ends opposing each other; An IC mounted on the base layer and disposed between the first and second bonding portions: a plurality of signal lines arranged in parallel with each other to pass through the IC in the base layer; a plurality of first pads disposed on the first bonding portion and each extending from one end of the plurality of signal lines; a plurality of second pads disposed on the second bonding portion and each extending from other ends of the plurality of signal lines; at least one power voltage supply line disposed in parallel with the plurality of signal lines outside the IC of the base layer; a third pad disposed on the first bonding portion and extending from one end of the at least one power supply line; a fourth pad disposed on the second bonding portion and extending from the other end of the at least one power supply line; and separation elements formed on the base layer and disposed in at least some areas between neighboring ones of the plurality of signal lines and the at least one power supply voltage line.

In the above configuration, the separation element may be at least one of a concave portion and a convex portion formed in the base layer.

In order to achieve the above-described object, a display device according to the present invention includes a display panel including a display area and a non-display area, and the display area including a plurality of pixels; A chip-on film according to any one of claims 1 to 8, wherein one side is electrically coupled to a non-display portion of the display panel to supply at least one power voltage and a plurality of data signals to the plurality of pixels; It is electrically coupled to the other side of the chip-on-film and includes a source PCB on which a power supply unit for supplying the at least one power voltage to the chip-on-film and a timing controller for supplying the plurality of data signals are mounted.

According to the chip-on-film and the display device equipped with the same according to the present invention, a separation element capable of preventing migration is disposed between adjacent signal supply lines and power voltage supply lines, so that even if they are moved due to moisture permeation. The separation element prevents them from contacting each other. Accordingly, it is possible to prevent unintentional short circuits between adjacent signal supply lines and power voltage supply lines of the chip-on-film.

1 is a block diagram schematically showing a conventional display device;
Figure 2 is an equivalent circuit diagram for one pixel of the display device of Figure 1;
Figure 3 is a plan view schematically showing the wiring arrangement of a portion of the chip-on-film shown in Figure 1;
Figure 4 is a cross-sectional view taken along line II' of Figure 3;
5 is a block diagram schematically showing an organic light emitting display device according to an embodiment of the present invention;
FIG. 6 is an equivalent circuit diagram schematically showing one pixel area of the display panel of the organic light emitting display device of FIG. 5;
FIG. 7 is a plan view schematically showing the chip-on-film applied to the organic light emitting display device shown in FIG. 5;
Figure 8 is a cross-sectional view taken along line II' of Figure 7;
Figure 9a is a plan view showing a first example showing a partial area of the chip-on-film shown in Figure 7;
Figure 9b is a plan view showing a second example showing a partial area of the chip-on-film shown in Figure 7;
Figure 9c is a plan view showing a third example showing a partial area of the chip-on-film shown in Figure 7;
Figure 9d is a plan view showing a third example showing a partial area of the chip-on-film shown in Figure 7;
Figure 9e is a plan view showing a fifth example showing a partial area of the chip-on-film shown in Figure 7;
Figure 10a is a cross-sectional view of the first example taken along line II-II' of Figures 9a to 9e;
Figure 10B is a cross-sectional view of a second example taken along line II-II' of Figures 9A to 9E.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Additionally, the names of components used in the following description may have been selected in consideration of the ease of preparing specifications, and may be different from the names of parts of the actual product.

Hereinafter, with reference to FIGS. 5 and 6, an organic light emitting display device according to an embodiment of the present invention will be described in detail. In the description of the embodiment of the present invention, an organic light emitting display device is used as an example as a display device, but it should be understood that the present invention is not limited thereto and also includes other flat panel display devices.

FIG. 5 is a block diagram schematically showing an organic light emitting display device according to an embodiment of the present invention, and FIG. 6 is an equivalent circuit diagram schematically showing one pixel area of the display panel of the organic light emitting display device of FIG. 5.

5 and 6, the organic light emitting display device according to the present invention includes a display panel (DP), a gate drive IC (GIC) disposed on one side of the display panel (DP), and a gate drive IC (GIC) disposed on one side of the display panel (DP). Chip on film (COF), which is attached to one end and has a source drive IC (DIC) mounted on it, and a source that is attached to the other end of the chip on film and has a timing controller (TC) and power supply (PS) mounted on it. Includes Printed Circuit Board (PCB) (SPCB).

The source drive IC (DIC) converts digital video data (RGB) input from the timing controller (TC) and generates a data voltage. The data voltage output from the source drive IC (DIC) is supplied to the data lines (DL).

The gate drive IC (GIC) sequentially supplies gate pulses synchronized with the data voltage to the gate lines (GL) to select pixels of the display panel (DP) to which the data voltage is written.

The timing controller (TC) receives timing signals such as vertical synchronization signal, horizontal synchronization signal, data enable signal, and main clock from the host system (not shown) and operates the data driver (DD) and gate driver (GD). Synchronize timing. Data timing control signals for controlling the source drive IC (DIC) include a source sampling clock and a source output enable signal. Gate timing control signals for controlling the gate drive IC (GIC) include gate start pulse, gate shift clock, gate output enable signal, etc.

The host system (not shown) can be implemented as any one of a television system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), home theater system, or phone system. there is. The host system includes a system on chip (SoC) with a built-in scaler and converts digital video data (RGB) of the input image into a format suitable for display on a display panel (DP). The host system transmits timing signals along with digital video data to a timing controller (TC).

The pixel array of the display panel DP includes a plurality of gate lines GL and a plurality of data lines DL arranged to intersect each other, and pixels arranged in each intersection area.

Referring to FIG. 6, each pixel may include an organic light emitting diode (OLED), a driving TFT (DT), a storage capacitor (Cst), a first switching TFT (ST), and a second switching TFT (ST2).

TFTs constituting a pixel may be implemented as p-type or n-type. Additionally, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or oxide. An organic light emitting diode (OLED) includes an anode electrode, a cathode electrode, and an organic light emitting layer (not shown) interposed between the anode electrode and the cathode electrode (CAT).

Organic light-emitting diodes (OLEDs) include an organic compound layer located between an anode electrode and a cathode electrode. The organic compound layer includes an emission layer (EML), and with the emission layer in between, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and An electron injection layer (EIL) may be disposed.

The anode electrode of the organic light emitting diode (OLED) is connected to the second node (N2), and the cathode electrode is connected to the input terminal of the low-potential power supply voltage (Vss).

The driving TFT (DT) controls the current flowing through the OLED according to the gate-source voltage (Vgs). The driving TFT (DT) has a gate electrode connected to the first node (N1), a drain electrode connected to the input terminal of the high potential power supply voltage (Vdd), and a source electrode connected to the second node (N2).

The storage capacitor Cst is connected between the first node N1 and the second node N2.

The first switching TFT (ST1) is turned on in response to the first gate pulse (SCAN) supplied through the first gate line (GL1), thereby transmitting the data voltage (Vdata) charged in the data voltage supply line to the first node ( Applies to N1). The first switching TFT (ST1) includes a gate electrode connected to the first gate line (GL1), a drain electrode connected to the data voltage supply line (DL), and a source electrode connected to the first node (N1).

The second switching TFT (ST2) is turned on in response to the second gate pulse (SEN) supplied through the second gate line (GL2), thereby controlling the reference voltage (Vref) charged in the reference voltage supply line (RL). 2 Applies to node (N2). The gate electrode of the second switching TFT (ST2) is connected to the second gate line (GL2), the drain electrode of the second switching TFT (ST2) is connected to the second node (N2), and the second switching TFT (ST2) The source electrode of is connected to the reference voltage supply line (RL).

The driving TFT (DT) controls the amount of light emitted by the organic light-emitting diode (OLED) by controlling the amount of current supplied to the organic light-emitting diode (OLED) according to the level of voltage charged in the storage capacitor. The amount of light emitted by an organic light emitting diode (OLED) is proportional to the amount of current supplied from the driving TFT (DT).

Each pixel receives a high potential power supply voltage (Vdd), a reference potential power supply voltage (Vref), and a low potential power supply voltage (Vss) from the power supply unit (PS).

Next, with reference to FIGS. 7 and 8 , a chip-on-film (COF) applied to an organic light emitting display device according to an embodiment of the present invention will be described.

FIG. 7 is a plan view schematically showing the chip-on-film applied to the organic light emitting display device shown in FIG. 5, and FIG. 8 is a cross-sectional view taken along line II' of FIG. 7.

Referring to FIGS. 7 and 8, the chip-on-film (COF) according to an embodiment of the present invention has first pads (PAD1a to PAD1d) contacting pads (not shown) of the source PCB (SPCB) on one side. A first pad area PA1 is formed, a second pad area PA2 is formed with second pads PAD2a to PAD2d contacting pads (not shown) of the display panel DP on the other side, and a second pad area PA2 is formed. It includes a source IC (DIC) mounted between the first pad area (PA1) and the second pad area (PA2). The first pad area (PA1) and the second pad area (PA2) are areas where the protective layer (PL) is removed and have openings where the first pads (PAD1a to PAD1d) and the second pads (PAD2a to PAD2d) are exposed. form First and second openings OP1 and OP2 are formed on both sides of the first pad area PA1 and the second pad area PA2, respectively, as spare areas where the protective layer PL is removed.

The first pads (PAD1a to PAD1d) include a data signal input pad (PAD1a), a high potential power supply voltage input pad (PAD1b), a reference potential power supply voltage input pad (PAD1c), and a low potential power supply voltage input pad (PAD1d). do.

The second pads (PAD2a to PAD2d) include a data signal output pad (PAD2a), a high potential power supply voltage output pad (PAD2b), a reference potential power supply voltage output pad (PAD2c), and a low potential power supply voltage output pad (PAD2d). do.

The high potential power supply voltage input pad (PAD1b), the reference potential power supply voltage input pad (PAD1c), and the low potential power supply voltage input pad (PAD1d) are each connected to the high potential power supply voltage output pad (PAD1d) through the wires (Vss1, Vref1, Vdd1). PAD2b), the reference potential power supply voltage output pad (PAD2c), and the low potential power supply voltage output pad (PAD2d).

As shown in FIG. 8, the second pads (PAD2a to PAD2d) have the protective layer (PL) removed as described above for connection to the pads (Dpad) of the display panel (DP), and the first The pads (PAD1a to PAD1d) also have their protective layer (PL) removed for connection to the pads of the source PCB (SPCB). The second pads PAD2a to PAD2d may be connected to the pads Dpad of the display panel DP through an anisotropic conductive film (ACF) containing conductive balls. Although not shown in FIG. 8, the first pads PAD1a to PAD1d may also be connected to pads of the source PCB (SPCB) through an anisotropic conductive film (ACF) containing conductive balls.

The first pad area (PA1), where the first pads (PAD1a to PAD1d) are connected to the pads of the source PCB (SPCB), becomes the first bonding area (BA1), and the second pads (PAD12 to PAD2d) are displayed. The second pad area PA2 connected to the pads Dpad of the panel DP becomes the second bonding area BA2. First and second openings OP1 and OP2 exist in front and behind the first bonding area BA1 and the second bonding area BA2 as spare areas where the protective layer PL is removed. Between the inner spare area of the first bonding area (BA1) and the inner spare area (OP2) of the second bonding area (BA2), a signal line (Vdata1) and power supply lines (Vss1, Vref1, Vdd1) are covered. A protective layer (Pl) is formed to form a non-opening portion (NOP).

Next, with reference to FIGS. 9A to 9E, 10A, and 10B, the chip-on-film (COF) according to an embodiment of the present invention attached to the display panel DP will be described in more detail.

FIG. 9A is a plan view showing a first example showing a partial area of the chip-on film shown in FIG. 7, and FIG. 9B is a plan view showing a second example showing a partial area of the chip-on film shown in FIG. 7. FIG. 9C is a plan view showing a third example showing a partial area of the chip-on film shown in FIG. 7, and FIG. 9D is a plan view showing a fourth example showing a partial area of the chip-on film shown in FIG. 7. Figure 9e is a plan view showing a fifth example showing a partial area of the chip-on-film shown in Figure 7. FIG. 10A is a cross-sectional view showing an example of a separation element taken along line II-II' of FIGS. 9A to 9E, and FIG. 10B is a cross-sectional view showing another example of a separation element taken along line II-II' of FIGS. 9A to 9E. This is a cross-sectional view.

In FIGS. 9A to 9E, 10A and 10B, the second pads (PAD2a to PAD2d) shown in FIG. 7 are a data signal supply line (PAD2a), a high potential power supply voltage supply line (Vdd1), and a reference potential power supply voltage. It is a part that extends from the supply line (Vref1) and the low-potential power voltage supply line (Vss1) and is expanded to have a larger area.

Referring to FIGS. 9A, 10A, and 10B, red (R), green (G), blue (B), and white colors are spaced at regular intervals on the base layer (BL) of the chip-on-film (COF) according to the first example. A data signal supply line (Vdata1) including data signal supply lines (Vr, Vg, Vb, Vw) for supplying data signals to each of the subpixels (W) is disposed. On one side (e.g., the left side) of the data signal supply line (Vdata1), a low-potential power supply voltage supply line (Vss1) and a reference potential power supply voltage supply line (Vref1) are arranged at a certain distance from the data signal supply line (Vdata1). On the other side (for example, the right side) of the data signal supply line (Vdata1), a high-potential power supply voltage supply line (Vdd1) is disposed at a certain distance from the data signal supply line (Vdata1).

Additionally, between the data signal supply lines (Vr, Vg, Vb, Vw), between the high potential power supply voltage supply line (Vdd1) and the data signal supply line (Vw), and between the reference potential power supply voltage supply line (Vref1) and the data signal supply. Between the lines (Vr), at least one between the reference potential power supply voltage supply line (Vref1) and the low potential power supply voltage supply line (Vss1), adjacent signal supply lines (Vr, Vg) as shown in FIG. 10A , Vb, Vw) and power supply lines (Vdd1, Vref1, Vss1), a concave portion is formed as a separation element (SE1) to prevent contact due to migration, or a convex portion is formed as shown in FIG. 10b. can be formed.

As shown in FIGS. 9A, 10A, and 10B, the concave portion and the convex portion as the separation element (SE1) of the chip-on-film (COF) according to the first example are the second bonding portion (BA2) facing the display panel (DP). ) It may be formed in the first opening OP1, which is the outer area.

Referring to FIGS. 9B, 10A, and 10B, red (R), green (G), blue (B), and white colors are spaced at regular intervals on the base layer (BL) of the chip-on-film (COF) according to the second example. A data signal supply line (Vdata1) including data signal supply lines (Vr, Vg, Vb, Vw) for supplying data signals to each of the subpixels (W) is disposed. On one side (e.g., the left side) of the data signal supply line (Vdata1), a low-potential power supply voltage supply line (Vss1) and a reference potential power supply voltage supply line (Vref1) are arranged at a certain distance from the data signal supply line (Vdata1). On the other side (for example, the right side) of the data signal supply line (Vdata1), a high-potential power supply voltage supply line (Vdd1) is disposed at a certain distance from the data signal supply line (Vdata1).

Additionally, between the data signal supply lines (Vr, Vg, Vb, Vw), between the high potential power supply voltage supply line (Vdd1) and the data signal supply line (Vw), and between the reference potential power supply voltage supply line (Vref1) and the data signal supply. Between the lines (Vr), at least one between the reference potential power supply voltage supply line (Vref1) and the low potential power supply voltage supply line (Vss1), adjacent signal supply lines (Vr, Vg) as shown in FIG. 10A , Vb, Vw) and power supply lines (Vdd1, Vref1, Vss1), a concave portion is formed as a separation element (SE2) to prevent contact due to migration, or a convex portion is formed as shown in FIG. 10b. can be formed.

As shown in FIGS. 9B, 10A, and 10B, the concave portion and the convex portion as the separation element SE2 according to the second example are the outer area from the second bonding portion BA2 toward the display panel DP. Up to 1 opening (OP1) can be formed.

Referring to FIGS. 9C, 10A, and 10B, red (R), green (G), blue (B), and white colors are spaced at regular intervals on the base layer (BL) of the chip-on-film (COF) according to the third example. A data signal supply line (Vdata1) including data signal supply lines (Vr, Vg, Vb, Vw) for supplying data signals to each of the subpixels (W) is disposed. On one side (e.g., the left side) of the data signal supply line (Vdata1), a low-potential power supply voltage supply line (Vss1) and a reference potential power supply voltage supply line (Vref1) are arranged at a certain distance from the data signal supply line (Vdata1). On the other side (for example, the right side) of the data signal supply line (Vdata1), a high-potential power supply voltage supply line (Vdd1) is disposed at a certain distance from the data signal supply line (Vdata1).

Additionally, between the data signal supply lines (Vr, Vg, Vb, Vw), between the high potential power supply voltage supply line (Vdd1) and the data signal supply line (Vw), and between the reference potential power supply voltage supply line (Vref1) and the data signal supply. Between the lines (Vr), at least one between the reference potential power supply voltage supply line (Vref1) and the low potential power supply voltage supply line (Vss1), adjacent signal supply lines (Vr, Vg) as shown in FIG. 10A , Vb, Vw) and power supply lines (Vdd1, Vref1, Vss1), a concave portion is formed as a separation element (SE3) to prevent contact due to migration, or a convex portion is formed as shown in FIG. 10c. can be formed.

As shown in FIGS. 9C, 10A, and 10B, the concave portion and the convex portion as the separation element SE3 according to the third example are outside the second bonding portion BA2 facing in the opposite direction of the display panel DP. It may be formed in the second opening OP2 area.

Referring to FIGS. 9D, 10A, and 10B, red (R), green (G), blue (B), and white colors are spaced at regular intervals on the base layer (BL) of the chip-on-film (COF) according to the fourth example. A data signal supply line (Vdata1) including data signal supply lines (Vr, Vg, Vb, Vw) for supplying data signals to each of the subpixels (W) is disposed. On one side (e.g., the left side) of the data signal supply line (Vdata1), a low-potential power supply voltage supply line (Vss1) and a reference potential power supply voltage supply line (Vref1) are arranged at a certain distance from the data signal supply line (Vdata1). On the other side (for example, the right side) of the data signal supply line (Vdata1), a high-potential power supply voltage supply line (Vdd1) is disposed at a certain distance from the data signal supply line (Vdata1).

Additionally, between the data signal supply lines (Vr, Vg, Vb, Vw), between the high potential power supply voltage supply line (Vdd1) and the data signal supply line (Vw), and between the reference potential power supply voltage supply line (Vref1) and the data signal supply. Between the lines (Vr), at least one between the reference potential power supply voltage supply line (Vref1) and the low potential power supply voltage supply line (Vss1), adjacent signal supply lines (Vr, Vg) as shown in FIG. 10A , Vb, Vw) and power supply lines (Vdd1, Vref1, Vss1), a concave portion is formed as a separation element (SE4) to prevent contact due to migration, or a convex portion is formed as shown in FIG. 10b. can be formed.

As shown in FIGS. 9D, 10A, and 10B, the concave portion and the convex portion as the separation element SE4 according to the fourth example are formed from the second bonding portion BA2 toward the display panel DP. It can be formed up to the first opening (OP1), which is the outer area.

Referring to FIGS. 9E, 10A, and 10B, red (R), green (G), blue (B), and white colors are spaced at regular intervals on the base layer (BL) of the chip-on-film (COF) according to the fifth example. A data signal supply line (Vdata1) including data signal supply lines (Vr, Vg, Vb, Vw) for supplying data signals to each of the subpixels (W) is disposed. On one side (e.g., the left side) of the data signal supply line (Vdata1), a low-potential power supply voltage supply line (Vss1) and a reference potential power supply voltage supply line (Vref1) are arranged at a certain distance from the data signal supply line (Vdata1). On the other side (for example, the right side) of the data signal supply line (Vdata1), a high-potential power supply voltage supply line (Vdd1) is disposed at a certain distance from the data signal supply line (Vdata1).

Additionally, between the data signal supply lines (Vr, Vg, Vb, Vw), between the high potential power supply voltage supply line (Vdd1) and the data signal supply line (Vw), and between the reference potential power supply voltage supply line (Vref1) and the data signal supply. Between the lines (Vr), at least one between the reference potential power supply voltage supply line (Vref1) and the low potential power supply voltage supply line (Vss1), adjacent signal supply lines (Vr, Vg) as shown in FIG. 10A , Vb, Vw) and power supply lines (Vdd1, Vref1, Vss1), a concave portion is formed as a separation element (SE5) to prevent contact due to migration, or a convex portion is formed as shown in FIG. 10b. can be formed.

As shown in FIGS. 9E, 10A, and 10B, the concave portion and the convex portion as the separation element SE5 according to the fifth example are the second bonding portion from the second bonding portion BA2 toward the display panel DP. A first opening OP1, which is an outer area of BA2, and a second opening OP2, which is an outer area of the second bonding part BA2 facing in the opposite direction of the display panel DP, may be formed.

The chip-on-film (COF) according to the first to fifth examples of the present invention described above allows migration ( Since the concave or convex parts are provided as separation elements (SE1, SE2, SE3, SE4, SE5) that can prevent migration, even if they move due to moisture permeation, they do not contact each other due to the separation elements. Therefore, it is possible to prevent unintentional short circuits between adjacent signal supply lines (Vr, Vg, Vb, Vw) and power supply voltage supply lines (Vdd1, Vref1, Vss1) of the chip-on-film (COF). You can.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. For example, in the description of the embodiment of the present invention described above, a concave portion or Although the description focuses on the convex portion, the first bonding portion BA1 bonded to the source PCB (SPCB) also has concave portions or convex portions as separation elements (SE1, SE2, SE3, SE4, SE5) like the second bonding portion (BA2). Wealth can be created equally.

In addition, in the embodiment of the present invention, the first to second examples of FIGS. 9A to 9E and the first to second examples of FIGS. 10A and 10B are independently applied, but the present invention is not limited thereto. , it should be understood that combining these configurations with each other also belongs to the present invention.

In addition, although the embodiment of the present invention has been described as an example in which a chip-on-film is applied to an organic light emitting display device, the present invention is not limited to this and can also be applied to other flat panel displays using a chip-on-film.

Accordingly, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

COF: Chip-on-Film DIC: Source Drive IC
DP: Display panel OP1, OP2: Opening
BA1, BA2: Bonding area PA1, PA2: Pad area
SPCB: Source PCB PS: Power supply
Vdd: High potential power supply voltage Vref: Reference potential power supply voltage
Vss: low potential power supply voltage

Claims (9)

A base layer including a first bonding portion and a second bonding portion disposed at a certain distance from each other at both ends facing each other;
an IC mounted on the base layer and disposed between the first and second bonding parts;
a plurality of signal lines arranged in parallel with each other in the base layer to pass through the first bonding part, the IC, and the second bonding part;
at least one power voltage supply line disposed in parallel with the plurality of signal lines outside the IC of the base layer and passing through the first bonding part and the second bonding part;
A first opening area disposed on the base layer to expose the plurality of signal lines and the at least one power voltage line in the first bonding part, the plurality of signal lines in the second bonding part, and the A second opening area exposing at least one power supply voltage line, a first opening exposing one side of the first opening area, the plurality of signal lines and the at least one between the other side of the first opening area and the IC a second opening exposing the power supply voltage line, and a third opening exposing the plurality of signal lines and the at least one power supply voltage line between one side of the second opening area and the IC, the second opening area a protective layer having a fourth opening exposing the other side and a non-opening area between the second opening and the third opening covering the plurality of signal lines and the at least one power voltage line; and
Separators formed in the first and second opening regions and the first to fourth openings of the base layer, respectively, are disposed between adjacent ones of the plurality of signal lines and the at least one power supply voltage line. Chip-on-film containing devices. According to claim 1,
A chip-on film wherein the separation element is at least one of a concave portion and a convex portion formed in the base layer. delete delete delete delete delete delete A display panel including a display area and a non-display area, the display area including a plurality of pixels;
A chip-on film according to claim 1 or 2, one side of which is electrically coupled to a non-display portion of the display panel to supply at least one power voltage and a plurality of data signals to the plurality of pixels;
A display device electrically coupled to the other side of the chip-on-film and including a source PCB on which a power supply unit for supplying the at least one power voltage to the chip-on-film and a timing controller for supplying the plurality of data signals are mounted. .

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