KR20230034843A - Emission Control Driver, Display Panel, and Display Device - Google Patents

Abstract

The present specification relates to a light emission control driver capable of reducing a bezel area. According to one embodiment, in the light emission control driver, each light emission control stage includes: an output buffer outputting a light emission control signal to an output line using a clock signal and outputting a first scan signal to a scan output line by control of a Q node, and outputting a high-potential power voltage to the output line and outputting a low-potential power voltage to the scan output line by control of QB node; a charging/discharging part charging the Q node by using a scan signal supplied from a scan driver, and discharging the Q node by control of the QB node; and an inverter charging and discharging the QB node opposite to the Q node.

Description

Emission Control Driver, Display Panel, and Display Device

The present specification relates to a light emission control driver capable of reducing a bezel area, a display panel, and a display device.

The light emitting display device uses a self-emitting device that emits light through an organic light emitting layer by recombination of electrons and holes, and has advantages of high luminance, low driving voltage, ultra-thin film, and free shape.

A light emitting display device includes a panel that displays an image through a pixel matrix and a driving circuit that drives the panel. Each of the pixels constituting the pixel matrix is independently driven by a thin film transistor (TFT).

A gate driver controlling TFTs of pixels may be disposed in a bezel area of a display panel. Since the gate driver includes a plurality of scan drivers that control the switching TFTs of each pixel and a light emission control driver that controls the light emission control TFTs, a bezel area can be increased.

The content of the background art described above is technical information that the inventor of the present specification possesses to derive examples of the present specification or acquired in the course of deriving examples of the present specification, and must be disclosed to the general public prior to filing the present specification. It cannot be said that it is a well-known technology.

The present specification provides a light emission control driver, a display panel, and a display device capable of reducing a bezel area.

The problems to be solved in various embodiments of the present specification are not limited to the above-mentioned problems, and other problems not mentioned are clear to those skilled in the art from the description below. will be understandable.

In the emission control driver according to an exemplary embodiment, each emission control stage outputs an emission control signal to an output line using a clock signal and outputs a first scan signal to a scan output line using a clock signal under control of a Q node, and outputs a first scan signal to a scan output line. An output buffer that outputs a high-potential power supply voltage to an output line under the control of and a low-potential power supply voltage to a scan output line, charges the Q node by using the scan signal supplied from the scan driver, and controls the QB node. It may include a charging/discharging unit that discharges the Q node, and an inverter that charges and discharges the QB node opposite to the Q node.

A display panel according to an embodiment includes a display area displaying an image through subpixels, a bezel area surrounding the display area, and second gate lines arranged in the bezel area and connected to the subpixels in a second scan. A scan driver for supplying a signal, disposed in the bezel area, supplying a first scan signal to each of the first gate lines connected to the subpixels, and providing a light emission control signal to each of the third gate lines connected to the subpixels It may include the emission control driver that supplies.

A display device according to an embodiment includes a display panel displaying an image through subpixels, a scan driver embedded in the display panel and supplying a second scan signal to each of second gate lines connected to the subpixels, and a display device. the emission control driver, which is built into the panel, supplies a first scan signal to each of the first gate lines connected to the subpixels, and supplies a light emission control signal to each of the third gate lines connected to the subpixels; can include

Specific details according to various embodiments other than the means for solving the problems mentioned above are included in the description and drawings below.

In the emission control driver according to an exemplary embodiment, each emission control stage outputs an emission control signal and a first scan signal using a second scan signal output from the scan driver, thereby reducing the circuit configuration and size of the gate driver.

Accordingly, the light emission control driver, the display panel, and the display device according to an exemplary embodiment may reduce a bezel area.

Since the contents of the problem to be solved, the means for solving the problem, and the effect mentioned above do not specify essential features of the claims, the scope of the claims is not limited by the matters described in the contents of the invention.

The accompanying drawings are provided to aid understanding of the embodiments of the present specification, and provide embodiments along with detailed descriptions. However, the technical features of this embodiment are not limited to specific drawings, and features disclosed in each drawing may be combined with each other to form a new embodiment.
1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment.
2 is an equivalent circuit diagram illustrating a configuration of a pixel circuit according to an exemplary embodiment.
FIG. 3 is a driving waveform diagram of the pixel circuit shown in FIG. 2 .
4 is a block diagram schematically illustrating configurations of some stages of an emission control driver according to an exemplary embodiment.
5 is an equivalent circuit diagram showing a circuit configuration of one emission control stage in an emission control driver according to an exemplary embodiment.
FIG. 6 is a driving waveform diagram of the emission control stage shown in FIG. 5 .
7 is a cross-sectional view illustrating a partial TFT structure of an emission control driver according to an exemplary embodiment.
8 is a diagram illustrating operation and driving waveforms during a first period of an emission control stage according to an exemplary embodiment.
9 is a diagram illustrating operation and driving waveforms during a second period of an emission control stage according to an exemplary embodiment.
10 is a diagram illustrating operation and driving waveforms during a third period of an emission control stage according to an exemplary embodiment.
11 is a diagram illustrating an operation and a same waveform during a fourth period of an emission control stage according to an exemplary embodiment.

Advantages and features of this specification, and methods of achieving them, will become clear with reference to embodiments described below in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments make the disclosure of this specification complete, and common knowledge in the art to which this specification belongs. It is provided to completely inform the person who has the scope of the invention, and this specification is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, so this specification is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description will be omitted. When "comprises," "has," "consists of," etc. mentioned in this specification is used, other parts may be added unless "only" is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description of the error range, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as “on top,” “upper,” “lower,” “next to,” etc., for example, “right” Or, unless "directly" is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, when a temporal precedence relationship is described with “after,” “next to,” “next to,” “before,” etc., unless “immediately” or “directly” is used, it is not continuous. cases may be included.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present specification.

In describing the components of the present specification, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being "connected," "coupled to," or "connected to" another element, that element is directly connected or capable of being connected to the other element, but indirectly unless specifically stated otherwise. It should be understood that other components may be “interposed” between each component that is or can be connected.

“At least one” should be understood to include all combinations of one or more of the associated elements. For example, "at least one of the first, second, and third elements" means not only the first, second, or third elements, but also two of the first, second, and third elements. It can be said to include a combination of all components of one or more.

Each feature of the various embodiments of the present specification can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each embodiment can be implemented independently of each other or can be implemented together in an association relationship. may be

Hereinafter, looking at the embodiments of the present specification through the accompanying drawings and embodiments are as follows. Since the scales of the components shown in the drawings have different scales from actual ones for convenience of explanation, they are not limited to the scales shown in the drawings.

1 is a block diagram schematically showing the configuration of a display device according to an embodiment of the present invention.

A display device according to an embodiment includes an organic light emitting diode (OLED) display device, a quantum-dot light emitting diode display device, or an inorganic light emitting diode display device. It may be an electroluminescent display including

Referring to FIG. 1 , a display device may include a display panel 100 , a gate driver 200 and a data driver 300 built into the display panel 100 .

The display panel 100 displays an image through a display area DA in which a plurality of subpixels P are arranged in a matrix form. The subpixel P is a red (R) subpixel emitting red light, a green (G) subpixel emitting green light, a blue (B) subpixel emitting blue light, and a white (W) subpixel emitting white light. It can be any one. A unit pixel may include at least two subpixels having different emission colors. Each subpixel P may include a light emitting element and a plurality of TFTs independently driving the light emitting element. A plurality of signal lines including data lines DL, gate lines GL1 , GL2 , and GL3 , power lines, and other signal lines connected to each subpixel P may be disposed in the display panel 100 .

The display panel 100 may further include a touch sensor screen disposed in the display area DA to sense a user's touch.

The gate driver 200 may be disposed in at least one of the bezel areas BZ1 to BZ2 surrounding the display area DA in the display panel 100 and located on the outer edge. For example, the gate driver 200 is disposed in one of the first and second bezel areas BZ1 and BZ2 facing the display area DA, or the first and second bezel areas BZ1. , BZ2) can be placed on both sides. The gate driver 200 may be a gate in panel (GIP) type composed of TFTs formed in the same process as the TFT array disposed in the display area DA.

The gate driver 200 includes a scan driver 220 that drives a second gate line GL2 among the first to third gate lines GL1, GL2, and GL3 connected to the pixels P of each horizontal line; An emission control driver 230 driving the first gate line GL1 and the third gate line GL3 may be included.

Each of the scan driver 220 and the emission control driver 230 may operate by receiving a gate control signal supplied from a timing controller (not shown) through a level shifter (not shown).

The scan driver 220 may include a plurality of second scan stages that individually supply second scan signals to the plurality of second gate lines GL2 . The second scan signal may control the second switching TFT of each of the plurality of subpixels P connected to the second gate line GL2 .

The emission control driver 230 individually supplies first scan signals to a plurality of first gate lines GL1 and a plurality of emission control stages that individually supplies emission control signals to a plurality of third gate lines GL3. can include The first scan signal may control the first switching TFT of each of the plurality of subpixels P connected to the first gate line GL1. The emission control signal may control the emission control TFT of each of the plurality of subpixels P connected to the third gate line GL3 . A detailed description of this will be described later.

The emission control driver 230 outputs the emission control signal and the first scan signal using the second scan signal output from the scan driver 220, thereby reducing the circuit configuration and size of the gate driver. Accordingly, the bezel areas BZ1 and BZ2 of the display panel can be reduced.

The data driver 300 may convert digital data supplied from a timing controller (not shown) into an analog data signal and supply each data voltage signal to each data line DL of the display panel 100 . The data driver 300 may convert digital data into an analog data voltage signal using grayscale voltages in which a plurality of reference gamma voltages supplied from a gamma voltage generator (not shown) are subdivided.

The data driver 300 may include a plurality of data drive integrated circuits (ICs) 310 that divide and drive the plurality of data lines DL disposed on the display panel 100 . Each of the plurality of data drive ICs 310 may be individually mounted on each circuit film 320 like a COF (Chip On Film) type. The plurality of COFs 320 on which the data drive IC 310 is mounted may be bonded to the bezel area BZ3 of the display panel 100 through an anisotropic conductive film (ACF).

A plurality of TFTs disposed in the display area DA of the display panel 100 and the bezel areas BZ1 to BZ4 including the gate driver 200 include an amorphous TFT using an amorphous silicon semiconductor layer and a polysilicon semiconductor layer using a polysilicon semiconductor layer. At least one of a TFT and an oxide TFT using a metal oxide semiconductor layer may be applied.

For example, the display panel 100 may employ oxide TFTs that have higher mobility than amorphous silicon TFTs, can be processed at a lower temperature than polysilicon TFTs, and can be easily applied to a large area, and have good TFT characteristics. ) type oxide TFT can be applied. The oxide TFT may further include a light blocking layer disposed under the oxide semiconductor layer with a buffer layer interposed therebetween to prevent light from entering the oxide semiconductor layer.

FIG. 2 is an equivalent circuit diagram illustrating a configuration of a pixel circuit according to an exemplary embodiment, and FIG. 3 is a driving waveform diagram of the pixel circuit shown in FIG. 2 .

Referring to FIG. 2 , the pixel circuit of each subpixel P includes a driving TFT (DT) supplying current to the light emitting element (ED), a switching TFT (ST1), an initialization TFT (ST2), and an emission control TFT (ET). , a 4T2C structure including storage capacitors Cst1 and Cst2 may be provided.

Each subpixel P includes first to third gate lines GL1 , GL2 , and GL3 , data lines DL, first and second power lines PL1 , PL2 disposed on the display panel 100 , and It may be connected to the initialization voltage line IL.

The scan driver 220 may supply the second scan signal SCAN2 to the second gate line GL3. The emission control driver 230 may supply the first scan signal SCAN1 to the first gate line GL1 and the emission control signal EM to the third gate line GL3. The data driver 300 may supply the data voltage Vdata to the data line DL. The power circuit (not shown) applies the first high-potential power supply voltage ELVDD to the first power line PL, the low-potential power supply voltage ELVSS to the second power line PL2, and the initialization voltage line IL. An initialization voltage Vini may be supplied.

Referring to FIG. 3 , each subpixel P may be driven to include an initial period, a sampling period, a program period, and an emission period for each frame.

Referring to FIGS. 2 and 3 , the switching TFT ST1 is controlled by the first gate line GL1 and is connected to the data line DL and the gate electrode G of the driving TFT DT. (N1) can be connected. During the initialization period, sampling period, and program period, the switching TFT (ST1) is turned on by the high-potential power supply voltage of the first scan signal (SCAN1) of the first gate line (GL1), through the data line (DL) The supplied reference voltage Vref and data voltage Vdata may be sequentially supplied to the first node N1.

The initialization TFT ST2 is controlled by the second gate line GL2 and includes a second node N2 commonly connected to the source electrode S of the driving TFT DT and the anode of the light emitting element ED, and an initialization voltage The line IL may be connected. During the initialization period, the initialization TFT ST2 is turned on by the high-potential power supply voltage of the second scan signal SCAN2 of the second gate line GL2 to set the initialization voltage Vini of the initialization voltage line IL. It can be supplied to the second node N2.

The emission control TFT (ET) is controlled by the third gate line (GL3) and may connect the first power line (PL1) and the drain electrode (D) of the driving TFT (DT). During the initialization period and the emission period, the emission control TFT (ET) is turned on by the high-potential power supply voltage of the emission control signal EM of the third gate line GL3, and the first power supply voltage of the first power line PL1 is turned on. The power supply voltage ELVDD may be supplied to the drain electrode D of the driving TFT DT.

The first storage capacitor Cst1 is connected between the first node N1 and the second node N2 to charge the data voltage Vdata-Vth compensated for by the threshold voltage Vth of the driving TFT DT. there is.

The second storage capacitor Cst2 is connected between the first power line 103 and the second node N2 commonly connected to the source electrode S of the driving TFT DT and the anode of the light emitting element ED. , it is possible to stably maintain the potential of the second node N2 during the light emission period.

The driving TFT DT controls the current Ids flowing to the light emitting element ED according to the driving voltage Vdata-Vth charged in the storage capacitor Cst1, thereby controlling the light emitting intensity of the light emitting element ED. .

The light emitting element ED has an anode connected to the source electrode S of the driving TFT DT, a cathode connected to the second power supply line PL2 supplying the low potential power supply voltage ELVSS, and an anode and a cathode. It may be provided with an organic light emitting layer of. The light emitting element ED may generate light of brightness proportional to the current value of the driving current supplied from the driving TFT DT.

Referring to FIG. 3 , during the initialization period, the first node N1 is initialized to the reference voltage Vref through the data line DL and the switching TFT ST1, and the second node N2 is the initialization voltage line ( IL) and the initialization TFT (ST2) to the initialization voltage (Vini), and the drain electrode (D) of the driving TFT (DT) has a high potential voltage through the first power line (PL1) and the emission control TFT (ET). A voltage ELVDD may be supplied.

During the sampling period, the voltage of the source electrode (S) rises until the gate-source voltage (Vgs) reaches the threshold voltage (Vth) by the source follow operation of the driving TFT (DT), and the storage capacitor ( Cst1) can charge the threshold voltage (Vth) of the driving TFT (DT).

During the program period, the data voltage Vdata is supplied to the first node N1 so that the storage capacitor Cst1 can be charged with the data voltage Vdata+Vth compensated for by the threshold voltage Vth of the driving TFT DT. there is. Accordingly, a characteristic deviation due to the threshold voltage of the driving TFT DT between the subpixels P in the subsequent light emitting period may be compensated.

During the light emitting period, the driving TFT DT drives the light emitting device ED according to the driving voltage Vdata+Vth charged in the storage capacitor Cst1 to control the light emitting intensity.

4 is a block diagram schematically illustrating the configuration of an emission control driver 230 according to an exemplary embodiment.

Referring to FIG. 4 , the emission control driver 230 according to an exemplary embodiment sequentially outputs a plurality of emission control signals EM(N) to EM(N+4) (where N is a positive integer). Emission control stages EM_ST(N) to EM_ST(N+4) may be included. In FIG. 4, for convenience, only five emission control stages EM_ST(N) to EM_ST(N+4) are shown.

The plurality of emission control stages EM_ST(N) to EM_ST(N+4) may receive any one clock signal among a plurality of clock signals CLK1 to CLK4 having different phases. The plurality of emission control stages EM_ST(N) to EM_ST(N+4) may receive a high-potential power supply voltage VDD and a low-potential power supply voltage VSS in common.

Each of the plurality of emission control stages EM_ST(N) to EM_ST(N+4) may receive a plurality of second scan signals output from the scan driver 220 as first and second input signals.

For example, the N-th emission control stage EM_ST(N) is supplied from the N-1-th scan stage of the scan driver 220 to the second gate line GL2 of the N-1-th horizontal line. -1) The scan signal SCAN2(N-1) and the second (N+2) scan signal SCAN2 supplied to the second gate line GL2 of the N+2 th horizontal line from the N+2 th scan stage. (N+2)) may be supplied as the first and second input signals to charge and discharge the Q node and the QB node.

The N+1 th emission control stage EM_ST(N+1) generates the second (N) scan signal SCAN2(N) from the N th scan stage of the scan driver 220 and the N+3 th scan stage. The Q node and the QB node may be charged and discharged by receiving the second (N+3) scan signal SCAN2(N+3) as the first and second input signals.

The N+2 th emission control stage EM_ST(N+2) is connected to the 2nd (N+1) scan signal SCAN2(N+1) from the N+1 th scan stage of the scan driver 220 and the N+ The Q node and the QB node may be charged and discharged by receiving the second (N+4) scan signal SCAN2 (N+4) from the fourth scan stage as the first and second input signals.

The N+3 light emission control stage EM_ST(N+3) is connected to the second (N+2) scan signal SCAN2(N+2) from the N+2 scan stage of the scan driver 220 and the N+ The Q node and the QB node may be charged and discharged by receiving the second (N+5) scan signal SCAN2 (N+5) from the fifth scan stage as the first and second input signals.

The N+4 th emission control stage EM_ST(N+4) is connected to the second (N+3) scan signal SCAN2(N+3) from the N+3 scan stage of the scan driver 220 and the N+ The Q node and the QB node may be charged and discharged by receiving the second (N+6) scan signal SCAN2 (N+6) from the sixth scan stage as the first and second input signals.

FIG. 5 is an equivalent circuit diagram showing the configuration of each light emission control stage in the light emission control driver according to an exemplary embodiment, and FIG. 6 is a driving waveform diagram of the light emission control stage shown in FIG. 5 .

Referring to FIG. 5 , each emission control stage EM_STn has a first stage to which the second (N−1) scan signal SCAN2(N−1) from the N−1 th scan stage of the scan driver 220 is supplied. An input line 21, a second input line 22 to which the second (N+2) scan signal SCAN2(N+2) from the N+2 th scan stage of the scan driver 220 is supplied, and a clock signal A clock line 23 supplied with (CLK(N)), a first power line 24 supplied with a high-potential power supply voltage VDD, and a second power line 25 supplied with a low-potential power supply voltage VSS , the output line 26 outputting the emission control signal EM(N), and the scan output line 27 outputting the first scan signal SCAN1(N).

The high potential supply voltage VDD may be defined as a gate high voltage or a gate on voltage. The low potential power supply voltage VSS lower than the high potential power supply voltage VDD may be defined as a gate low voltage or a gate off voltage.

The clock signal CLK(N) may be any one of a plurality of clock signals having different phases. Each clock signal CLK(N) may be supplied in a pulse form in which a gate-on (high) level of a specific horizontal period and a gate-off (low) level of a specific horizontal period alternate. The gate-on level of each clock signal CLK(N) may be the same as the high-potential power supply voltage VDD, and the gate-off level may be the same as the low-potential power supply voltage VSS.

In FIG. 6 , the first to fourth periods t1 , t2 , t3 , and t4 are an initialization period of the pixel circuit to which the first scan signal SCAN1(N) and the emission control signal EM(N) are supplied, sampling Each of the period, program period, and light emission period can be corresponded to.

Each emission control stage EM_ST(N) has a gate-off voltage in a first period t1 corresponding to an initialization period and a third period t2 corresponding to a program period, and has a gate-off voltage in a second period corresponding to a sampling period ( t) and during the fourth period t4 corresponding to the light emission period, the light emission control signal EM(N) in the form of a pulse having a gate-on voltage may be output.

Each emission control stage EM_ST(N) has a gate-on voltage for the second period (t), and a gate-off voltage for the first, third, and fourth periods (t1, t3, and t4). A scan signal SCAN1(N) may be output.

Each emission control stage EM_ST(N) may include a charging/discharging unit 232 , an inverter 234 , and an output buffer 236 . The charge/discharge unit 232 is defined as a first node controller that controls the Q node, which is the first control node of the output buffer 236, and the inverter 234 controls the QB node, which is the second control node of the output buffer 236. It can be defined as a second node control unit. Both the charging/discharging unit 232 and the inverter 234 may be defined as control units that control the Q node and the QB node.

The charging/discharging unit 232 may include charging transistors T1a and T1b for charging the Q node and a discharging transistor T3 for discharging the Q node. The inverter 234 may include a charging transistor T4 for charging the QB node and discharging transistors T5a, T5b, and T5q for discharging the QB node. The output buffer 236 includes output transistors T6 and T7 for charging and inverting the output line 28 outputting the emission control signal EM(N) and scan outputting the first scan signal SCAN1(N). Output transistors T62 and T72 for charging and discharging the output line 27 and a capacitor CE may be included.

The charging/discharging unit 232 may charge the Q node in response to the second (N−1) scan signal SCAN2(N−1) of the scan driver 220 supplied to the first input line 21, The Q node may be charged in response to the second (N+2) scan signal SCAN2(N+2) of the scan driver 220 supplied to the second input line 22 . The charging/discharging unit 232 may discharge the Q node to the low potential power supply voltage VSS in response to the control of the QB node.

The charging/discharging unit 232 may include a first charging transistor T1a having a gate electrode and a drain electrode connected to the first input line 21 in a diode structure and a source electrode connected to the Q node. The first charging transistor T1a is connected to the second (N-1) scan signal SCAN2(N-1) during a period t1 in which the second (N-1) scan signal SCAN2(N-1) is activated to an on level. The Q node can be charged with an on level of -1)). The first charging transistor T1a may be defined as a first charging diode.

The charging/discharging unit 232 may include a second charging transistor T1b having a gate electrode and a drain electrode connected to the second input line 22 in a diode structure and a source electrode connected to the Q node. The second charging transistor T1b outputs the second (N+2) scan signal SCAN2(N+2) during a period t3 in which the second (N+2) scan signal SCAN2(N+2) is activated to an on level. It is possible to charge the Q node with an on level of +2)). The second charging transistor T1b may be defined as a second charging diode.

The charge/discharge unit 232 may include a first discharge transistor T3 having a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to the second power line 25 . The first discharge transistor T3 may discharge the Q node to the low-potential power supply voltage VSS during the period t4 in which the QB node is activated to an on level.

Inverter 234 may control the QB node as opposed to the Q node. The inverter 234 may include a third charging transistor T4 connected in a diode structure between the first power line 24 and the QB node. The third charging transistor T4 is turned on by the high-potential power supply voltage VDD to charge the QB node with the high-potential power supply voltage VDD. The third charging transistor T4 may be defined as a third charging diode.

The inverter 234 is controlled by the second (N−1) scan signal SCAN2(N−1) supplied to the first input line 21 to discharge the QB node to the low potential power supply voltage VSS. Two discharge transistors T5a may be included. The second discharge transistor T5a discharges the QB node to the low-potential supply voltage VSS during a period t1 in which the second (N-2) scan signal SCAN2 (N-2) is activated to an on level. can

The inverter 234 is controlled by the second (N+2) scan signal SCAN2(N+2) supplied to the second input line 22 to discharge the QB node to the low potential supply voltage VSS. 3 discharge transistor T5b may be included. The third discharge transistor T5b discharges the QB node to the low potential supply voltage VSS during the period t3 in which the second (N+2) scan signal SCAN2(N+2) is activated to an on level. can

The inverter 234 may include a fourth discharge transistor T5q that is controlled by the Q node to discharge the QB node to the low potential power supply voltage VSS. The fourth discharge transistor T5q may discharge the QB node to the low-potential power supply voltage VSS during periods t1 , t2 , and t3 in which the Q node is activated to an on level.

The output buffer 236 includes a first output transistor T6 for outputting the clock signal CLK(N) supplied to the clock line 23 to the output line 26 in response to control of the Q node, and a clock signal A second output transistor T62 outputting (CLK(N)) to the scan output line 27 may be included. The first output transistor T6 outputs the clock signal CLK(N) to the emission control signal EM(N) through the output line 26 during periods (t1, t2, t3) when the Q node is activated to an on level. ) can be output with an off level and an on level. The second output transistor T62 transmits the clock signal CLK(N) through the scan output line 27 to the first scan signal SCAN1( N)) can be output with an off level and an on level.

The output buffer 236 includes a third output transistor T7 for outputting the high-potential power voltage VDD supplied to the first power line 24 to the output line 26 in response to control of the QB node; A fourth output transistor T72 may be included to output the low-potential power supply voltage VSS supplied to the second power supply line 25 to the scan output line 27 . The third output transistor T7 stabilizes the high-potential power supply voltage VDD through the output line 26 to the on-level of the emission control signal EM during most of the period t4 when the QB node is activated to the on-level. can be supplied with The fourth output transistor T72 transmits the low-potential power supply voltage VSS to the first scan signal SCAN1(N) through the scan output line 27 during most of the period t4 when the QB node is activated to an on level. can be supplied stably with an off level of

As shown in FIG. It may be a coplanar type oxide TFT including

7 is a diagram showing a simplified cross-sectional structure of some TFFs, eg, output transistors T6 and T7, of a light emission control driver according to an exemplary embodiment.

The output transistors T6 and T7 include a light blocking layer 112 disposed on the substrate 110, a buffer film 114 covering the light blocking layer 112, and a semiconductor layer 116 disposed on the buffer film 114. , Gate insulating film 118 covering the semiconductor layer 116, gate electrode 120 disposed on the gate insulating film 118, interlayer insulating film 122 covering the gate electrode 120, disposed on the interlayer insulating film 112 and a source electrode 126 and a drain electrode 124 respectively connected to the conductive region of the semiconductor layer 116 through the contact holes 101 and 103. The remaining transistors T1a, T1b, T3, T4, T5a, T5b, T5q, T62, and T72 of the emission control driver 230 may also have structures similar to those of the output transistors T6 and T7.

The emission control driver 230 includes an inorganic insulating film 130 and an organic insulating film 132 stacked covering the source electrode 126 and the drain electrode 124, the clock line 23 disposed on the organic insulating film 132, and The power line 24, the clock line 23, and the power line 24 are formed by an organic insulating film 138, an inorganic insulating film 142, an organic insulating film 144, and an inorganic insulating film 146 stacked on the organic insulating film 138. It may further include an encapsulation layer 140 having a. The clock line 23 is connected to the drain electrode 124 of the output transistor T6 through the contact hole 107, and the power line 24 is connected to the source electrode of the output transistor T7 through the contact hole 109 ( 126) can be connected. Another power line 25 may be disposed on the same layer as the clock line 23 and the power line 24 .

The semiconductor layer 116 is disposed on both sides of the channel region overlapping the gate electrode 120 with the gate insulating film 118 interposed therebetween and makes ohmic contact with the source electrode 126 and the drain electrode 124, respectively. The semiconductor layer 116 may include an oxide semiconductor material, such as IZO (InZnO), IGO (InGaO), It may include at least one of ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, and ITZO (InSnZnO)-based.

The light blocking layer 112 is made of an opaque metal and absorbs external light or internal light, thereby preventing light from entering the oxide semiconductor layer 116 .

The light-blocking layer 112 of the transistors T1a, T1b, T3, T4, T5a, T5b, T5q, T6, and T7 constituting each stage EM_ST(N) is floated, or the gate electrode 120 or the source electrode (126) can be connected.

8 to 11 are diagrams illustrating operations and driving waveforms of the emission control stage EM_ST(N) shown in FIG. 5 during the first to fourth periods t1, t2, t3, and t4.

Referring to FIG. 8 , in response to the on level of the second (N−1) scan signal SCAN2(N−1) supplied from the scan driver 220 during the first period t1, the first charging transistor (T1a) may charge the Q node to an on level, and the second and fourth discharge transistors T5a and T5q may discharge the QB node to the low potential power voltage VSS. The first and second output transistors T6 and T62 are turned on by the on level of the Q node, and the off level of the clock signal CLK(N) is transmitted through the output line 26 to the emission control signal EM( N)), and the off level of the clock signal CLK(N) can be output as the off level of the first scan signal SCAN1(N) through the scan output line 27. can

Referring to FIG. 9 , during the second period t2, the Q node is floated in an on-level state by the off-level of the second (N-1) scan signal SCAN1 (N-2), and the fourth discharge transistor (T5a, T5q) may discharge the QB node to a low potential power supply voltage (VSS). The first and second output transistors T6 and T62, which are turned on by the on level of the Q node, divide the on level of the clock signal CLK(N) from the light emission control signal EM(N). It can be output with the ON level of 1 scan signal (SCAN1[N]). At this time, the Q node on level is raised by the bootstrapping operation of the capacitor CE connected between the Q node and the output line 26, thereby improving the current capability of the first and second output transistors T6 and T62. there is. Accordingly, the rising time of the emission control signal EM(N) and the first scan signal SCAN1[N] may be improved.

Referring to FIG. 10 , in response to the on level of the second (N+2) scan signal SCAN2(N+2) supplied from the scan driver 220 during the third period t3, the first The second charging transistor T1b may charge the Q node to an on level, and the third discharging transistor T5b may discharge the QB node to the low potential power supply voltage VSS. The first and second output transistors T6 and T62 are maintained in a turned-on state by the on level of the Q node, and the off level of the clock signal CLK(N) is changed to the emission control signal EM(N) and It can be output at an off level of the first scan signal SCAN1[N].

Referring to FIG. 11 , in response to the off level of the second (N+2) scan signal SCAN2(N+2) during the fourth period t4, the second charging transistor T1b and the third discharging transistor ( T5b) is turned off, and the QB node can be charged to an on level by the high-potential power supply voltage VDD supplied through the third charging transistor T4. Due to the on level of the QB node, the third output transistor T7 can output the high-potential power voltage VDD to the on level of the emission control signal EM(N), and the fourth output transistor T72 can output the low potential power supply voltage VDD to the on level of the emission control signal EM(N). The potential power supply voltage VSS may be output at the off level of the first scan signal SCAN1[N]. The first discharge transistor T3 is turned on by the on level of the QB node, and the Q node has a low potential power. Discharged to the off level of the voltage VSS, and the first and second output transistors T6 and T62 may be turned off.

As such, in the light emission control driver according to an embodiment, each light emission control stage outputs a light emission control signal and a first scan signal using a second scan signal output from the scan driver, thereby reducing the circuit configuration and size of the gate driver. can

Accordingly, the light emission control driver, the display panel, and the display device according to an exemplary embodiment may reduce a bezel area.

In an emission control driver according to an exemplary embodiment, a third output transistor controlled by the QB node stably supplies a gate-on voltage of an emission control signal using a high-potential power supply voltage during an emission period that takes up most of the time in each frame. , the fourth output transistor can stably supply the gate-off voltage of the first scan signal using the low-potential power supply voltage.

In an emission control driver according to an exemplary embodiment, first and second output transistors controlled by a Q node use a scan signal and a clock signal from the scan driver to obtain a gate-off voltage and gate-on voltage of the emission control signal and the first scan signal. By supplying the voltage, the rising time of the emission control signal and the first scan signal may be improved.

Accordingly, the light emitting control driver, the display panel, and the display device according to an embodiment may improve reliability by improving the rising time of the light emitting control signal and the scan signal.

An emission control driver and a display device including the same according to an embodiment may be applied to various electronic devices. For example, a light emission control driver and a display device including the same according to an embodiment are mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices ( foldable device), rollable device, bendable device, flexible device, curved device, electronic notebook, e-book, PMP (portable multimedia player), PDA ( personal digital assistant), MP3 player, mobile medical device, desktop PC, laptop PC, netbook computer, workstation, navigation, vehicle navigation, vehicle display, television, It can be applied to wallpaper display devices, signage devices, game devices, laptop computers, monitors, cameras, camcorders, and home appliances.

Features, structures, effects, etc. described in various examples of the above-described specification are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, the features, structures, effects, etc. illustrated in at least one example in this specification can be combined or modified with respect to other examples by those skilled in the art to which the technical idea of this specification belongs. Therefore, contents related to these combinations and variations should be construed as being included in the technical scope or scope of rights of this specification.

The present specification described above is not limited to the foregoing embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes are possible within a range that does not deviate from the technical spirit of the present specification. It will be clear to those who have knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present specification.

100: display panel 200: gate driver
210, 220: scan driver 230: emission control driver
300: data driver 310: data driver IC
320: circuit film 232: charging and discharging unit
234: inverter 236: output buffer
21: first input line 22: second input line
23: clock line 24: first power line
25: second power line 26: output line
110: substrate 112: light blocking layer
114: buffer film 116: semiconductor layer
118: gate insulating film 122: interlayer insulating film
124: drain electrode 126: source electrode
130, 142, 146: inorganic insulating film 132, 138, 144: organic insulating film
140: encapsulation layer 120: gate electrode

Claims (14)

a plurality of light emission control stages respectively supplying a plurality of light emission control signals;
Each of the plurality of emission control stages,
Under the control of the first control node (hereinafter referred to as Q node), a light emission control signal is output to an output line using a clock signal and a first scan signal is output to a scan output line using a clock signal, and a second control node (hereinafter referred to as QB node) is controlled. an output buffer outputting a high-potential power supply voltage to the output line and a low-potential power supply voltage to the scan output line under control;
a charge/discharge unit that charges the Q node using a scan signal supplied from a scan driver and discharges the Q node under control of the QB node; and
A light emission control driver comprising an inverter for charging and discharging the QB node opposite to the Q node. The method of claim 1,
The output buffer is
a first output transistor controlled by the Q node and configured to output the clock signal supplied to a clock line to the output line;
a second output transistor controlled by the Q node and configured to output the clock signal supplied to a clock line to the scan output line;
a third output transistor controlled by the QB node and configured to output the high-potential power voltage supplied to the first power line to the output line; and
and a fourth output transistor controlled by the QB node and outputting the low potential power voltage supplied to a second power line to the scan output line. The method of claim 2,
The output buffer is
The emission control driver further comprising a capacitor connected between the Q node and the output line. The method of claim 2,
The charge/discharge unit
a first charging transistor charging the Q node with the second scan signal using the 2-1 scan signal supplied from the scan driver;
a second charging transistor for charging the Q node with the second scan signal using the 2-2 scan signal supplied from the scan driver; and
and a first discharge transistor controlled by the QB node to discharge the Q node to the low potential power supply voltage. The method of claim 4,
The inverter
a second charging transistor charging the QB node using the high-potential power supply voltage;
a second discharge transistor controlled by the 2-1st scan signal to discharge the QB node to the low potential power supply voltage;
a third discharge transistor controlled by the 2-1 scan signal to discharge the QB node to the low potential power supply voltage; and
and a fourth discharge transistor controlled by the Q node to discharge the QB node to the low potential power supply voltage. The method of claim 5,
The emission control stage is an N-th emission control stage outputting an N-th (N is an integer greater than 2) emission control signal and an N-th first scan signal;
The 2-1 scan signal is an N-1 second scan signal output from an N-1 scan stage of the scan driver,
Wherein the 2-2 scan signal is an N+2 second scan signal output from an N+2 scan stage of the scan driver. The method of claim 6,
The N-th light emission control signal has a gate-off level in the first to fourth periods included in each frame, a gate-off level in the first period and a third period, and a gate-on level in the second and fourth periods;
The N-th first scan signal has a gate-on level in the second period and a gate-off level in the first, third, and fourth periods. The method of claim 7,
In the first to fourth periods of the Nth light emission control signal and the Nth first scan signal,
The first period corresponds to an initialization period of a pixel circuit to which the Nth emission control signal and the Nth first scan signal are supplied;
the second period corresponds to a sampling period of the pixel circuit;
the third period corresponds to a programming period of the pixel circuit;
The fourth period corresponds to a light emission period of the pixel circuit. The method of claim 7,
During the first period,
The first charging transistor charges the Q node with the on level of the N−1 th second scan signal, and the first output transistor converts the off level of the clock signal to the gate off level of the N th light emission control signal. and the second output transistor outputs an off level of the clock signal as a gate off level of the Nth first scan signal. The method of claim 7,
During the second period,
The Q node is floated to an on level by the off level of the N−1 th second scan signal, and the first output transistor outputs the on level of the clock signal as the gate on level of the N th light emission control signal. , the second output transistor outputs the on level of the clock signal to the gate on level of the Nth first scan signal,
The Q node increases according to the on level of the clock signal. The method of claim 7,
During the third period,
The second charging transistor charges the Q node with the on level of the N+2 second scan signal, and the first output transistor converts the off level of the clock signal to the gate off level of the Nth light emission control signal. and the second output transistor outputs an off level of the clock signal as a gate off level of the Nth first scan signal. The method of claim 7,
During the fourth period,
The QB node charges the high-potential power supply voltage to an on level, the third output transistor outputs the high-potential power supply voltage to a gate-on level of the N-th light emission control signal, and the fourth output transistor charges the high-potential power supply voltage to a gate-on level of the N-th light emission control signal. An emission control driver that outputs a potential power supply voltage as a gate-off level of the N-th first scan signal. a display area displaying an image through subpixels;
a bezel area surrounding the display area;
a scan driver disposed in the bezel area and supplying a second scan signal to each of second gate lines connected to the subpixels; and
supplying the emission control signal to each of the third gate lines disposed in the bezel area and connected to the subpixels, and supplying a first scan signal to each of the first gate lines connected to the subpixels; A display panel comprising the emission control driver according to any one of claims 1 to 12. a display panel displaying an image through subpixels;
a scan driver built into the display panel and supplying a second scan signal to each of second gate lines connected to the subpixels; and
supplying the emission control signal to each of the third gate lines embedded in the display panel and connected to the subpixels, and supplying a first scan signal to each of the first gate lines connected to the subpixels; A display device comprising the emission control driver according to any one of claims 1 to 12.

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