KR20220096845A - Display Device having Gate Drivier - Google Patents

Abstract

The present specification relates to a display device having a gate driver capable of reducing leakage current of a TFT to reduce power consumption and secure output stability. In the gate driver according to one aspect, each stage may temporally separate a charging timing of a QB node through a QB node charging unit and a discharging timing of the QB node through a QB node discharging unit.

Description

Display Device having Gate Driver

The present specification relates to a display device having a gate driver capable of reducing power consumption by reducing leakage current of a TFT and securing output stability.

A display device includes a panel for displaying an image through a pixel matrix, and a driving circuit for driving the panel. Each of the pixels constituting the pixel matrix is independently driven by a thin film transistor (TFT). In the driving circuit, the gate driver drives the gate line connected to the TFT of each pixel, and the data driver drives the data line connected to the TFT.

The gate driver includes stages for respectively driving gate lines, and each stage is composed of a plurality of TFTs. As a gate driver, a gate-in-panel (GIP) method formed on a panel together with a TFT array of a pixel matrix is known.

When the N-type oxide TFT applied to the gate driver has a negative threshold voltage Vth, the low voltage applied to the gate for turn-off is not lower than the source voltage, so that the leakage current increases.

When the leakage current in the TFTs constituting the gate driver is large, the output waveform of the gate driver is distorted, so reliability is deteriorated and power consumption is increased. Therefore, a method for minimizing the leakage current is required.

The content of the background art described above is technical information that the inventor of the present specification possessed to derive an example of the present specification or acquired in the process of deriving an example of the present specification, and must be disclosed to the general public prior to the filing of the present specification It cannot be said to be a known technology.

The present specification provides a display device having a gate driver capable of reducing power consumption by reducing leakage current of a TFT and securing output stability.

The problems to be solved in the various embodiments of the present specification are not limited to the problems mentioned above, and other problems not mentioned are clear to those of ordinary skill in the art to which the technical idea of the present specification belongs from the description below. can be understood clearly.

In the gate driver according to one aspect, each stage is pulled up under the control of the Q node and includes a pull-up transistor for outputting a clock signal input through a clock terminal among a plurality of clocks to an output terminal; an output unit including a pull-down transistor for outputting a gate-off voltage to an output terminal; a Q node charging unit for charging the Q node; a Q node discharging unit discharging the Q node; a QB node charging unit for charging the QB node; A QB node discharging unit for discharging the QB node may be included, and a charging timing of the QB node through the QB node charging unit and a discharging timing of the QB node through the QB node discharging unit may be temporally separated.

The QB node charging unit includes: a first QB charging transistor configured to provide a high potential voltage to the QB node in response to a start signal; and a second QB charging transistor that provides a high potential voltage to the QB node in response to an output of the preceding stage.

The QB node charging unit may further include a capacitor providing a clock signal to the QB node, and the capacitor may provide a clock signal during a floating period of the QB node to periodically increase the high floating voltage of the QB node.

The QB node charging section further includes a capacitor that provides the voltage of the Q node of the preceding stage to the QB node, the capacitor raising the high floating voltage of the QB node when the Q node of the preceding stage rises to the precharging voltage, When the Q node of the stage drops from the bootstrapping voltage, the low floating voltage of the QB node can be decreased.

The QB node charging unit provides, during the active period of each frame, a first charging timing of the QB node by the first QB charging transistor and a second charging timing of the QB node through the first QB charging transistor, and a discharging timing of the QB node A first charging timing of the QB node may be provided before , and a second charging timing of the QB node may be provided immediately after the discharging timing of the QB node.

In the first period between the first charging timing of the QB node and the discharging timing of the QB node, and the second period between the second charging timing of the QB node and the end timing of the active period of each frame, the QB node maintains the high floating voltage It may be a floating period of

The first charging timing of the QB node may be provided at the same timing in a plurality of stages, and the second charging timing of the QB node may be provided in an OFF period of the Q node immediately following the ON period of the Q node in each stage.

The QB node discharge unit may include a QB discharge transistor that is controlled by the Q node to provide a second gate-off voltage to the QB node.

The QB node discharge unit includes first and second QB discharge transistors controlled by the Q node and connected in series between the QB node and the second gate-off voltage to provide a discharge path of the QB node; and an offset transistor controlled by the QB node to provide a high potential voltage as an offset voltage to an intermediate node of the first and second QB discharge transistors.

The QB node discharge unit may include a QB discharge transistor that provides a second gate-off voltage to the QB node by being controlled by a set terminal to which one of an output and a start signal of the preceding stage is applied.

The Q node charging unit includes a Q charging transistor that is controlled by a set terminal to which any one set signal of an output and a start signal of the preceding stage is applied to provide a set signal to the Q node, and the Q charging transistor is connected to the set terminal. first and second Q charging transistors sharing a gate electrode and connected in series between the set terminal and the Q node.

The Q node discharging unit includes a first Q discharging transistor controlled by the QB node and providing a second gate-off voltage to the Q node, the first Q discharging transistor sharing a gate electrode connected with the QB node and sharing a gate electrode connected to the Q node and the Q node It may include 1-1 and 1-2 Q discharge transistors connected in series between the two gate-off voltages.

The Q node discharge unit further includes a second Q discharge transistor that is controlled by a reset terminal to which either a reset signal or an output of a subsequent stage is applied and provides a second gate-off voltage to the Q node, the second Q discharge transistor may include 2-1 and 2-2 Q discharge transistors that share a gate electrode connected to the QB node and are connected in series between the Q node and the second gate-off voltage.

Each stage may further include an output discharge transistor that is controlled by a reset terminal to which either a reset signal or an output of a subsequent stage is applied to the Q node discharge unit and provides a second gate-off voltage to the output terminal.

When each stage is an Nth stage (N is an integer greater than 4), the output of the preceding stage uses the output of the N-4th preceding stage, and the bootstrapping period of the Q node of the preceding stage is the Nth stage may overlap with the precharging period of the Q node of , and the output of the subsequent stage may use the output of the N+4th preceding stage.

The display device according to an aspect may include the gate driver according to the above-described aspect.

Specific details according to various embodiments other than the means for solving the above-mentioned problems are included in the description and drawings below.

The gate driver and the display device according to an embodiment temporally separate the charging timing and the discharging timing of the QB node in each stage without overlap, thereby stably maintaining the low voltage of the QB node to prevent leakage current of the Q node, As a result, gate output failure can be prevented and power consumption can be reduced.

The gate driver and display device according to an embodiment may reduce the number of transistors in the QB node discharging unit by removing a short section between the charging path and the discharging path of the QB node in each stage, and as a result, the circuit configuration of the gate driver and By reducing the size, it can be advantageously applied to a narrow bezel.

The gate driver and the display device according to an embodiment block the leakage current of the QB node during the floating period of the QB node in each stage to stably maintain the discharge path of the Q discharge transistor, thereby preventing multi-output failure of the gate output, , power consumption can be reduced.

The gate driver and the display device according to one aspect use a coplanar-type oxide TFT and prevent leakage current even when the oxide TFT has a negative threshold voltage, thereby preventing distortion of an output waveform and reducing power consumption .

Since the contents of the problems to be solved, the problem solving means, and the effects mentioned above do not specify the essential characteristics of the claims, the scope of the claims is not limited by the matters described in the content of the invention.

The accompanying drawings are provided to help understanding of the embodiments of the present specification, and embodiments are provided together with detailed descriptions. However, the technical features of the present embodiment are not limited to specific drawings, and features disclosed in each drawing may be combined with each other to constitute a new embodiment.
1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment.
2 is a block diagram schematically illustrating some stages of a gate driver according to an exemplary embodiment.
3 is a cross-sectional view illustrating a structure of a coplanar oxide TFT of a gate driver according to an exemplary embodiment.
4 is an equivalent circuit diagram illustrating a configuration of each stage of a gate driver according to an exemplary embodiment.
FIG. 5 is a driving waveform diagram of the stage shown in FIG. 4 .
6 is an equivalent circuit diagram illustrating a configuration of each stage of a gate driver according to an exemplary embodiment.
FIG. 7 is a driving waveform diagram of the stage shown in FIG. 6 .
8 is an equivalent circuit diagram illustrating a configuration of each stage of a gate driver according to an exemplary embodiment.
9 is a diagram illustrating a leakage current blocking operation of a QB discharge transistor in each stage of a gate driver according to an exemplary embodiment.
10 is a waveform diagram illustrating voltages and gate outputs of a Q node and a QB node of each stage of a gate driver according to the related art and an embodiment.
11 is a graph illustrating power consumption of a gate driver according to a related art and an exemplary embodiment.

Advantages and features of the present specification, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments allow the disclosure of the present specification to be complete, and common knowledge in the technical field to which this specification belongs It is provided to fully inform those who have the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and thus the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in the description of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted. When "includes," "has," "consisting of," etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, cases including the plural are included unless otherwise explicitly stated.

In interpreting the components, even if there is no explicit description of the error range, it is interpreted as including the error range.

In the case of a description of the positional relationship, for example, when the positional relationship of the two parts is described as "on," "upper," "lower," "nextly", for example, "just" Alternatively, one or more other parts may be placed between two parts unless "directly" is used.

In the case of a description of a temporal relationship, when the temporal precedence is described as “after,” to “following,” “after,” “before”, etc., it is not continuous unless “immediately” or “directly” is used. cases may be included.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

In describing the components of the present specification, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected,” “coupled,” or “connected” to another component, the component may be directly connected or connected to the other component, but indirectly without specifically expressly stated. It should be understood that other components may be “interposed” between each component that is connected or can be connected.

“At least one” should be understood to include all combinations of one or more of the associated elements. For example, the meaning of “at least one of the first, second, and third components” means not only the first, second, or third components, but also two of the first, second, and third components. It can be said to include a combination of all or more components.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, referring to the embodiments of the present specification through the accompanying drawings and embodiments, as follows. The scales of the components shown in the drawings have different scales from the actual ones for convenience of description, and thus are not limited to the scales shown in the drawings.

1 is a block diagram schematically showing the configuration of a display device according to an embodiment of the present invention, and FIG. 2 is a block diagram schematically showing some stages of a gate driver according to an embodiment.

The display device according to an embodiment may be any one of various display devices including a liquid crystal display device, an electroluminescent display device, a micro LED (Light Emitting Diode) display device, and the like. The electroluminescent display device may be an organic light emitting diode (OLED) display device, a quantum dot light emitting diode (Quantum-dot Light Emitting Diode) display device, or an inorganic light emitting diode (Inorganic Light Emitting Diode) display device.

Referring to FIG. 1 , the display device includes a panel 100 , a GIP-type gate driver 200 , a data driver 300 , a timing controller 400 , a level shifter 600 , a gamma voltage generator 700 , and a power supply. management circuitry 500 and the like.

The power management circuit 500 uses an input voltage supplied from the outside to configure all the components of the display device, that is, the panel 100 , the gate driver 200 , the data driver 300 , the timing controller 400 , and the level shifter 600 . ) and the gamma voltage generator 700 may generate and output various driving voltages necessary for the operation.

The timing controller 400 may receive image data and synchronization signals from an external host system. The host system may be any one of a system of a portable terminal such as a computer, a TV system, a set-top box, a tablet, or a mobile phone. The synchronization signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 400 may perform various image processing such as luminance correction or image quality correction for reducing power consumption on the image data, and may supply the image-processed data to the data driver 300 .

The timing controller 400 generates and supplies a plurality of data control signals to the data driver 300 by using the synchronization signals and the internally stored timing setting information (start timing, pulse width, etc.), and provides the plurality of control signals. It can be generated and supplied to the level shifter 600 .

The gamma voltage generator 700 may generate a reference gamma voltage set including a plurality of reference gamma voltages having different voltage levels and supply it to the data driver 300 . The gamma voltage generator 700 may generate a plurality of reference gamma voltages corresponding to the gamma characteristics of the display device under the control of the timing controller 400 and supply the generated reference gamma voltages to the data driver 300 . The gamma voltage generator 700 may be configured as a programmable gamma IC, and receives gamma data from the timing controller 400 and generates or adjusts a reference gamma voltage level according to the gamma data to generate or adjust a reference gamma voltage level to the data driver 300 . can be output as

The data driver 300 is controlled according to a data control signal supplied from the timing controller 400 , converts digital data supplied from the timing controller 400 into an analog data signal, and corresponds to each data line of the panel 100 . Provides a data signal. The data driver 300 may convert digital data into an analog data signal using grayscale voltages in which a plurality of reference gamma voltages supplied from the gamma voltage generator 700 are subdivided.

The level shifter 600 may generate a plurality of gate control signals based on the plurality of control signals supplied from the timing controller 400 and supply them to the gate driver 200 . The level shifter 600 may level-shift the start signal and the reset signal supplied from the timing controller 400 , respectively, and supply it to the gate driver 200 . The level shifter 600 may generate a plurality of gate clocks having different phases by logic-processing the on and off clocks supplied from the timing controller 400 and supply them to the gate driver 200 . The on clock may determine a rising timing of each of the gate clocks, and the off clock may determine a falling timing of each of the gate clocks.

The panel 100 displays an image through the display area AA in which the sub-pixels SP are arranged in a matrix form. Each subpixel SP has a red (R) subpixel emitting red light, a green (G) subpixel emitting green light, a blue (B) subpixel emitting blue light, and a white (W) subpixel emitting white light. any one of them, and is independently driven by at least one TFT. The unit pixel may be composed of a combination of two, three, or four sub-pixels having different colors.

The panel 100 may further include a touch sensor screen for sensing a user's touch by overlapping the display area AA as a whole, and the touch sensor screen is embedded in the panel 100 or the display area AA of the panel 100 . ) can be placed on

The gate driver 200 is composed of TFTs formed in the same process as the TFT array disposed in the display area AA of the panel 100 , and is formed in a bezel area on either side or one side of the panel 100 , in a gate-in (GIP) area. Panel) type.

The gate driver 200 may receive a plurality of gate control signals from the level shifter 600 and perform a shift operation to individually drive the gate lines GL of the panel 100 . The gate driver 200 is configured as a shift register having a plurality of stages that are connected to each other to drive the plurality of gate lines GL, respectively, and generate individual gate outputs.

In FIG. 2 , for convenience, three gate outputs (GOUT(N-1), GOUT(N), GOUT(N+1)) (N is a positive integer) are generated among a plurality of stages constituting the gate driver 200, respectively. Only three stages ST(N-1), ST(N), and ST(N+1) are schematically shown.

Each stage ST(N) may receive at least one clock signal from among a plurality of clock signals CLKs having different phases. Each stage ST(N) may output an input clock pulse as a scan pulse of the gate output GOUT(N) in response to any one (set signal) of the start signal and the output of the preceding stage. Each stage ST(N) may output a gate-off voltage of the gate output GOUT(N) in response to any one (reset signal) of a reset signal and an output of a subsequent stage. The gate output GOUT(N) of each stage ST(N) may be used as a carry signal to be supplied to another stage as a set signal or a reset signal. The preceding stage refers to any one of stages that are located before (upper) the corresponding stage or output scan pulses before the corresponding stage, and the following stage is located after (lower) the corresponding stage or scan pulses after the corresponding stage It means any one of the stages that output .

TFTs disposed in the display area AA of the panel 100 and the bezel area including the gate driver 200 include an amorphous TFT using an amorphous silicon semiconductor layer, a poly TFT using a polysilicon semiconductor layer, and a metal oxide semiconductor layer. At least one of oxide TFTs may be applied.

For example, in the panel 100, an oxide TFT with higher mobility than an amorphous silicon TFT, a lower temperature process than a polysilicon TFT, and easy application to a large area can be applied, and Coplanar with good TFT characteristics. A type of oxide TFT can be applied.

3 is a cross-sectional view illustrating a structure of a coplanar-type oxide TFT of a gate driver according to an exemplary embodiment.

Referring to FIG. 3 , the coplanar-type oxide TFT includes a light blocking layer LS on a substrate SUB, a buffer film BF covering the light blocking layer LS, a semiconductor layer ACT on the buffer film BF, The gate insulating layer GI and the gate electrode GE stacked on the semiconductor layer ACT, the interlayer insulating layer ILD covering the semiconductor layer ACT, the gate insulating layer GI, and the gate electrode GE, and the interlayer insulating layer ( First and second source/drain electrodes SD1 and SD2 respectively connected to the first and second conductive regions CA1 and CA2 of the semiconductor layer ACT through the contact hole of the ILD are provided. One of the first and second source/drain electrodes SD1 and SD2 is a source electrode and the other is a drain electrode.

The semiconductor layer ACT is disposed on both sides of the channel region CH overlapping the gate electrode GE with the gate insulating layer GI interposed therebetween, and first and second source/drain electrodes ( First and second conductive regions CA1 and CA2 conductively formed to be in ohmic contact with SD1 and SD2, respectively. The semiconductor layer ACT includes an oxide semiconductor material. For example, the semiconductor layer ACT is IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), GZO (GaZnO). It may include at least one of a system and an ITZO (InSnZnO) system.

The light blocking layer LS is made of an opaque metal and absorbs external or internal light to prevent light from entering the oxide semiconductor layer ACT. The light blocking layer LS may be electrically floating or may be connected to any one of the first and second source/drain electrodes SD1 and SD2 .

Meanwhile, since the light blocking layer LS is used as a bottom gate electrode and the gate electrode GE is used as a top gate electrode, the coplanar oxide TFT shown in FIG. 3 may operate as a double gate TFT.

Compared to the back channel etched type oxide TFT, the coplanar oxide TFT has a thinner gate insulating film (GI), a larger on-current (Ion), and a steep gate voltage-to-current characteristic. Since the S-factor, which is the reciprocal of , is small and the parasitic capacitance is small, when applied to the gate driver 200 , high-speed driving is possible and the TFT size can be reduced. The S-factor is the current-voltage characteristic of the TFT, and it means the magnitude of the gate voltage required to increase the drain current by a factor of 10 when a gate voltage lower than the threshold voltage is applied.

The gate driver 200 according to an embodiment may use an N-type coplanar oxide TFT, and when each TFT is turned off, the off voltage applied to the gate electrode GE is applied to the source electrode SD1. In most cases, it is the same as the voltage. At this time, when the TFT has a negative threshold voltage (Vth<0), the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth) becomes greater than 0V (Vgs-Vth>0V), so that the leakage current increases and power consumption This increases and the gate output waveform may be distorted.

To prevent this, the gate driver 200 according to an embodiment includes a configuration for preventing leakage current of the QB node operating in a state opposite to that of the Q node controlling the pull-up TFT in each stage, thereby stabilizing the QB node. The off voltage also prevents leakage current of the Q node, thereby securing the stability of the gate output and reducing power consumption. A detailed description thereof will be provided later.

4 is an equivalent circuit diagram illustrating the configuration of each stage in the gate driver according to an embodiment, and FIG. 5 is a driving waveform diagram of the stage shown in FIG.

4 , each stage includes Q node charging units T1_a and T1_b, Q node discharging units T3_a, T3_b, T3n_a, and T3n_b, QB node charging units T4a and T4b, QB node discharging units T5q, and output It may include parts T6 and T7 and an output discharge part T3no. The Q node charging units T1_a, T1_b, Q node discharging units T3_a, T3_b, T3n_a, T3n_b, QB node charging units T4a, T4b, and QB node discharging unit T5q are all Q of the output units T6 and T7. It can be defined as a control unit that controls the node and the QB node. A Q node may be defined as a first control node, and a QB node may be defined as a second control node.

The TFTs constituting each stage may be a coplanar-type oxide TFT including a light blocking layer LS as shown in FIG. 3 .

Each stage STn includes a set terminal 2 to which any one of a start signal VST and an output CRY(N-4) of a preceding stage is applied as a set signal, and a first to which a high potential voltage VDD is applied. The power supply terminal 4 , the second power terminal 6 to which the first gate-off voltage VGL is applied, the third power terminal 8 to which the second gate-off voltage VSS is applied, and the clock signal GCLK(N) . It may include a reset terminal 16 to which is applied, and a control terminal 10 to which a start signal VST is applied. The first gate-off voltage VGL may be defined as a first gate low voltage, and the second gate-off voltage VSS may be defined as a second gate low voltage. The gate output GOUT(N) of each stage may be applied as a carry signal to the other stage.

The clock signal GCLK(N) applied to the clock terminal 12 of each stage is any one of a plurality of clock signals having different phases, for example, an 8-phase clock signal, and the clock signal GCLK(N) is It may be a pulse waveform in which a high voltage (gate-on voltage) of a period of 4H (or 3H) and a low voltage (gate-off voltage) of a period of 4H (or 5H) are alternately repeated.

As shown in FIG. 5 , the high potential voltage VDD applied to the first power terminal 4 of each stage is applied only during the active period Factive of each frame, and is applied as a low voltage during the blank period of each frame. can be

The output units T6 and T7 are pulled up under the control of the Q node and output the clock signal GCLK(N) applied to the clock terminal 12 through the output terminal 14 to the gate output GOUT( N)), the pull-up transistor T6 is pulled down by the control of the QB node opposite to the Q node, and the first gate-off voltage VGL from the first power supply terminal 6 is applied to the output terminal ( 14) and a pull-down transistor T7 that outputs to the gate output GOUT(N).

The pull-up transistor T6 may have a gate electrode connected to the Q node, a source electrode connected to the output terminal 14 , and a drain electrode connected to the clock terminal 12 . For example, the pull-up transistor T6 is turned on during the on period t3 of the Q node as shown in FIG. 5 to transmit the clock signal GCLK(N) from the clock terminal 12 to the output terminal 14 ) as a scan signal of the gate output GOUT(N). During the on period t3 of the Q node, the pull-up transistor T6 may output the gate output GOUT(N) having the gate-on voltage and the gate-off voltage of the clock signal GCLK(N).

The output units T6 and T7 further include a first capacitor CB connected between the gate electrode (Q node) and the source electrode (output terminal 14) of the pull-up transistor T6. The first capacitor CB bootstraps the high voltage of the Q node as shown in FIG. 5 when the pull-up TFT T6 is pulled up to output the gate-on voltage of the clock signal GCLK(N). to reduce the rising time of the gate output GOUT(N) by amplifying it.

The pull-down transistor T7 may have a gate electrode connected to the QB node, a source electrode connected to the second power supply terminal 6 , and a drain electrode connected to the output terminal 14 . For example, the pull-down transistor T7 is turned on during the on period of the QB node corresponding to the off periods t1, t2, t4, and t5 of the Q node as shown in FIG. 5, so that the second power terminal ( The first gate-off voltage VGL from 6 ) may be output as a gate-off voltage of the gate output GOUT(N) through the output terminal 14 .

The Q node charging units T1_a and T1_b receive the start signal VST or the output (CRY(N-4)) of the preceding stage as a set signal through the set terminal 2 to charge the Q node with the set signal. can The output CRY(N-4) of the preceding stage may be the gate output GOUT(N-4) output from the N-4th preceding stage.

The Q node charging units T1_a and T1_b may include diode-type Q charging transistors T1_a and T1_b having a gate electrode and a drain electrode connected to the set terminal 2 and a source electrode connected to the Q node. The pair of Q charging transistors T1_a and T1_b may share a gate electrode connected to the set terminal 2 and may be connected in series between the set terminal 2 and the Q node to provide a charging path of the Q node. The Q charging transistors T1_a and T1_b may be turned on when the output CRY(N-4) of the N-4 th preceding stage has a high voltage to precharge the Q node to a high voltage.

The Q node discharge units T3_a, T3_b, T3n_a, and T3n_b respond to the control of the QB node and control the Q node in response to the control of the reset terminal 16 to connect the Q node to the second gate-off voltage (VSS) of the third power terminal 8 . can be discharged with

The first Q node discharging units T3_a and T3_b include first Q discharging transistors T3_a and T3_b having a gate electrode connected to a QB node, a source electrode connected to the third power terminal 8 , and a drain electrode connected to the Q node. ) may be included. The pair of first Q discharge transistors T3_a and T3_b share a gate electrode connected to the QB node and are connected in series between the Q node and the third power supply terminal 8 to provide a first discharge path of the Q node. have.

As shown in FIG. 5 , the first Q discharge transistors T3_a and T3_b are turned on during the off period of the Q node, that is, the on period of the QB node (t1, t2, t4, t5) to connect the Q node to the second gate. It can be discharged to the off voltage (VSS). Accordingly, the first Q discharge transistors T3_a and T3_b prevent generation of ripple at the Q node due to the transition of the clock signal GCLK(N) during the Q node off periods t1, t2, t4, and t5 to prevent the gate It is possible to prevent the output (GOUT(N)) from being defective.

The second Q node discharge units T3n_a and T3n_b have a gate electrode connected to a reset terminal 16 to which an output signal CRY(N+4) or a reset signal of a subsequent stage is supplied, and a third power supply terminal 8 source It may include second Q discharge transistors T3n_a and T3n_b to which an electrode is connected and a drain electrode is connected to the Q node. The pair of second Q discharge transistors T3n_a and T3n_b share a gate electrode connected to the reset terminal 16 and are connected in series between the Q node and the third power supply terminal 8 to provide a second discharge path of the Q node. can provide The output (CRY(N+4)) of the subsequent stage may be the gate output (GOUT(N)+4) output from the N+4th post stage. The second Q discharge transistors T3n_a and T3n_b may be turned on when the output CRY(N+4) of the subsequent stage is a high voltage to discharge the Q node to the second gate-off voltage VSS.

The output discharge unit T3no includes an output discharge transistor T3no having a gate electrode connected to a reset terminal 16 , a drain electrode connected to an output terminal 14 , and a source electrode connected to a second power supply terminal 6 . can do. The output discharge transistor T3no is turned on when the carry signal CRY(N+4) or the reset signal of the subsequent stage is a high voltage (t4) to set the output terminal 14 to the first gate-off voltage VGL. can be discharged.

The QB node charging units T4a and T4b may charge the QB node to the high potential voltage VDD of the first power terminal 4 in response to the control of the control terminal 10 and the reset terminal 16 .

The QB node charging unit has a first QB charging transistor ( T4a). As shown in FIG. 5 , the first QB charging transistor T4a may be turned on during a period t1 in which the start signal VST is a high voltage to charge the QB node to the high potential voltage VDD.

The QB node charging unit may include a second QB charging transistor T4b having a gate electrode connected to the reset terminal 16 , a drain electrode connected to the first power supply terminal 4 , and a source electrode connected to the QB node. The second QB charging transistor T4b is turned on during the period t4 when the carry signal CRY(N+4) of the subsequent stage or the reset signal is high voltage as shown in FIG. 5 to power the QB node It can be charged with the above voltage (VDD).

The QB node charging units T4a and T4b may further include a second capacitor C connected between the clock terminal 12 and the QB node. As shown in FIG. 5 , the second capacitor C is formed when the clock signal GCLK(N) is at a high voltage during the floating period t2 and t5 after the QB node is charged to a high voltage (t1, t4). Each time, the high voltage of the QB node can be increased. Accordingly, the QB node maintains a stable high voltage during the floating period t2 and t5 to stably maintain the discharge path of the Q discharge transistors T3_a and T3_b, thereby preventing the multi-output failure of the gate output GOUT(N). can do.

The first charging timing t1 of the QB node charging units T4a and T4b is provided to the plurality of stages at the same timing, and the second charging timing t4 is the Q node following the on period t3 of the Q node in each stage. can be provided during the off period of

The QB node discharging unit T5q may discharge the QB node to the second gate-off voltage VSS of the third power terminal 8 in response to the control of the Q node.

The QB node discharging unit T5q may include a QB discharging transistor T5q having a gate electrode connected to the Q node, a source electrode connected to the third power terminal 8 , and a drain electrode connected to the QB node. As shown in FIG. 5 , the QB discharge transistor T5q is turned on during the on period t3 of the Q node to discharge the QB node to the second gate-off voltage VSS.

Referring to FIG. 5 , in the QB node, during the active period Factive of each frame, a period t1 in which the start signal VST is a high voltage, and a carry signal CRY(N+4) in a subsequent stage is a high voltage. The high potential voltage VDD may be charged through the QB node charging units T4a and T4b during the phosphor period t4. The QB node maintains the charged high voltage during the floating periods t2 and t5 and increases to a higher high voltage whenever the high voltage of the clock signal GCLK(N) is applied to the second capacitor C. can be kept stable. The QB node may be discharged to the second gate-off voltage VSS through the QB node discharge unit T5q during a period t3 when the Q node is a high voltage.

As described above, the gate driver according to an embodiment performs the charging timings t1 and t4 of the QB node by the QB node charging units T4a and T4b in each stay and the discharging timing t3 by the QB node discharging unit T5q. By temporally separating without overlap, it is possible to remove a section in which the charging path and the discharging path of the QB node are shorted. Accordingly, during the on period t3 of the Q node, the QB node stably maintains a low voltage to prevent leakage current of the Q node, thereby preventing a defect in the gate output GOUT(N) and reducing power consumption. have. In addition, the number of transistors in the QB node discharging unit T5q is lower than that of the related art gate driver in which the VDD voltage is continuously applied to the QB node during the active period of each frame by removing the short section between the charging path and the discharging path of the QB node. Since it can be reduced from two to one, the circuit configuration and size of the gate driver can be reduced, so that it can be advantageously applied to a narrow bezel.

Furthermore, in the gate driver according to an embodiment, whenever the high voltage of the clock signal GCLK(N) is applied to the second capacitor C during the floating period of the QB node (t2, t5), the high voltage of the QB node is It is possible to prevent multi-output failure of the gate output GOUT(N) by stably maintaining the discharge paths of the Q discharge transistors T3_a and T3_b by maintaining the high voltage at the QB node.

6 is an equivalent circuit diagram illustrating the configuration of each stage in the gate driver according to an embodiment, and FIG. 7 is a driving waveform diagram of the stage shown in FIG. 6 .

The stage of the gate driver shown in FIG. 6 includes a QB node discharge transistor T5c in which the QB node discharge part T5c is controlled by the set terminal 2, in contrast to the stage of the gate driver shown in FIG. and, except for the configuration in which the second capacitor C is connected to the Q(N-4) node 18 of the preceding stage, the remaining circuit configurations are the same, so the description of the same configurations as in FIG. 4 and the same configurations A description of the effect will be omitted.

The QB node discharge unit T5c has a gate electrode connected to the set terminal 2 to which the output CRY(N-4) or the start signal VST of the preceding stage is applied, and a source electrode to the third power supply terminal 8 . It may include a QB discharge transistor T5c connected to the QB node and a drain electrode connected to the QB node. The QB discharge transistor T5c is turned on during the precharging period during the on period t3 of the Q node to which the output CRY(N-4) of the preceding stage or the start signal VST is applied as a high voltage to the QB node may be discharged to the second gate-off voltage VSS.

The second capacitor C has one electrode connected to the QB node and the other electrode connected to the Q(N-4) node 18 of the N-4th preceding stage. As shown in FIG. 7 , the Q(N-4) node 18 has a precharging period during the on period t3 of the Q node of the current stage and a high voltage floating period t2 of the QB node before the precharging period. ), during the on-period t3(N-4)) of the Q(N-4) node 18 overlapping a portion of the Q(N-4) node 18, the precharging voltage and the booststrapping voltage of the Q(N-4) node 18 are It can be applied to the capacitor (C).

Accordingly, when the voltage of the Q(N-4) node of the preceding stage rises to the pre-charging voltage during a part of the high voltage floating period t2 of the QB node as shown in FIG. 7 , the second capacitor C is It can raise the high voltage of the QB node. In addition, as shown in FIG. 7 , in the second capacitor C, the voltage of the Q(N-4) node of the preceding stage is booted during the bootstrapping period of the Q node, which is the low voltage floating period (part of t3) of the QB node. When dropping from the strapping voltage to the low voltage, the low voltage of the QB node can be decreased. Accordingly, by preventing the leakage current of the Q discharge transistors T3_a and T3_b by the falling voltage of the low voltage of the QB node during the bootstrapping period of the Q node, it is possible to prevent a defect in the gate output GOUT(N) and reduce power consumption. can be reduced

8 is an equivalent circuit diagram illustrating a configuration of each stage in the gate driver according to an embodiment, and FIG. 9 is a diagram illustrating a leakage current blocking operation of a QB discharge transistor in each stage of the gate driver according to an embodiment.

In the stage of the gate driver shown in FIG. 8, in contrast to the stage of the gate driver shown in FIG. 4, the QB node discharge part includes a pair of QB discharge transistors T5q_a and T5q_b, and a pair of QB discharge transistors ( Except for the configuration that further includes an offset transistor T3qb for applying the high potential voltage VDD as an offset voltage QBh to the intermediate nodes of T5q_a and T5q_b, the rest of the circuit configuration is the same. A description of and a description of the effects of the same components will be omitted.

A pair of QB discharge transistors T5q_a and T5q_b share a gate electrode connected to the Q node, and are connected in series between the QB node and the third power supply terminal 8, thereby discharging the QB node during the on period t3 of the Q node. It may be discharged to the second gate low voltage VSS.

The offset transistor T3qb is turned on during the periods t1 , t2 , t4 , and t5 when the QB node is a high voltage to apply the high potential voltage VDD from the first power supply terminal 4 to the QB discharge transistors T5q_a and T5q_b ) by supplying the high-state offset voltage to the intermediate node of the QB discharge transistors T5q_a and T5q_b may prevent leakage current.

Referring to FIG. 9 , during the off periods t1, t2, t4, and t5 of the Q node, a second gate-off voltage VSS is applied to the gate electrodes of the pair of QB discharge transistors T5q_a and T5q_b, and one A second gate-off voltage VSS is applied to the source electrode of the second QB discharge transistor T5q_b among the pair of QB discharge transistors T5q_a and T5q_b. At this time, a high potential voltage (VDD) is applied to an intermediate node between the source electrode of the first QB discharge transistor T5q_a and the drain electrode of the second QB discharge transistor T5q_b among the pair of QB discharge transistors T5q_a and T5q_b. is applied, so that the gate-source voltage (Vgs<<0) of the first QB discharge transistor T5q_a becomes a negative voltage smaller than 0V, so that the QB discharge transistors T5q_a and T5q_b increase the negative threshold voltage. Even when it has, it is possible to block the leakage current of the QB discharge transistors T5q_a and T5q_b.

Accordingly, during the high voltage charging period (t1, t4) and the high voltage floating period (t2, t5) of the QB node, the offset transistor T3qb blocks the leakage current of the QB discharge transistors T5q_a and T5q_b, thereby blocking the QB node By stably maintaining the high voltage of the Q discharge transistors T3_a and T3_b and stably maintaining the discharge path of the Q discharge transistors T3_a and T3_b, multi-output failure of the gate output GOUT(N) can be prevented and power consumption can be reduced.

10 is a waveform diagram illustrating voltages and gate outputs of a Q node and a QB node of each stage of a gate driver according to the related art and an embodiment.

Referring to FIG. 10 , when the threshold voltage (Vth) of the TFT is a negative voltage in the stage of the gate driver according to the related art, the low voltage of the QB node is unstable and the leakage current of the Q node is increased during the bootstrapping period of the Q node. Accordingly, it can be seen that the bootstrapping voltage waveform of the Q node may be distorted, and a ripple occurs at the Q node during the off period of the Q node, thereby generating a multi-output at the gate output GOUT.

On the other hand, in the stage of the gate driver according to an exemplary embodiment, even when the threshold voltage (Vth) of the TFT is a negative voltage, the QB node stably maintains the low voltage during the bootstrapping period of the Q node, thereby reducing the leakage current of the Q node. In the off period of the Q node, the voltage of the QB node rises periodically to prevent the ripple of the Q node and to prevent the multi-output of the gate output (GOUT) to ensure the stability of the gate output (GOUT) can be known

11 is a graph illustrating power consumption of a gate driver according to a related art and an exemplary embodiment.

Referring to FIG. 11 , when the threshold voltage (Vth) of the TFT is a negative voltage, the power consumption by the related art gate driver having the DC structure of the QB node is higher than the power consumption of the gate driver having the QB floating structure according to an embodiment. It can be seen that the power consumption is further reduced.

As such, the gate driver and the display device according to an embodiment temporally separate the charging timing and the discharging timing of the QB node in each stage without overlap, thereby stably maintaining the low voltage of the QB node to prevent leakage current of the Q node. As a result, a defect in the gate output GOUT(N) can be prevented and power consumption can be reduced.

The gate driver and display device according to an embodiment may reduce the number of transistors in the QB node discharging unit by removing a short section between the charging path and the discharging path of the QB node in each stage, and as a result, the circuit configuration of the gate driver and By reducing the size, it can be advantageously applied to a narrow bezel.

The gate driver and the display device according to an embodiment increase the high voltage of the QB node or decrease the low voltage of the QB node by the second capacitor during the floating period of the QB node in each stage, thereby forming the Q discharge transistors T3_a and T3_b. It is possible to stably maintain the discharge path and prevent leakage current, and as a result, it is possible to prevent multi-output failure of the gate output GOUT(N).

The gate driver and the display device according to an embodiment block the leakage current of the QB node by an offset transistor during the high voltage charging period and the floating period of the QB node in each stage to stably maintain the discharge path of the Q discharging transistor to output the gate Multi-output failure of (GOUT(N)) can be prevented, and power consumption can be reduced.

The gate driver and the display device according to one aspect use a coplanar-type oxide TFT and prevent leakage current even when the oxide TFT has a negative threshold voltage, thereby preventing distortion of an output waveform and reducing power consumption .

A gate driver and a display device including the same according to an embodiment may be applied to various electronic devices. For example, a gate driver and a display device including the same according to an embodiment may include a mobile device, a video phone, a smart watch, a watch phone, a wearable device, and a foldable device. device), rollable device, bendable device, flexible device, curved device, electronic notebook, e-book, PMP (portable multimedia player), PDA (personal) digital assistant, MP3 player, mobile medical device, desktop PC, laptop PC, netbook computer, workstation, navigation, vehicle navigation, vehicle display, television, wallpaper (wall paper) It can be applied to a display device, a shiny (signage) device, a game device, a notebook computer, a monitor, a camera, a camcorder, and a home appliance.

Features, structures, effects, etc. described in various examples of the present specification are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. illustrated in at least one example of the present specification may be combined or modified with respect to other examples by those of ordinary skill in the art to which the technical spirit of the present specification pertains. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the technical scope or scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications and changes are possible within the scope without departing from the technical spirit of the present specification. It will be clear to those who have the knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present specification.

2: set terminal 4: first power terminal
6: second power terminal 10: control terminal
8: third power terminal 12: clock terminal
14: output terminal 16: reset terminal
18: Q (N-4) terminal

Claims (17)

In a gate driver including a plurality of stages each driving a plurality of gate lines,
each stage
A pull-up transistor that is pulled up under the control of the first node (hereinafter referred to as the Q node) and outputs a clock signal input through a clock terminal among the plurality of clocks to an output terminal, and a second node (hereinafter referred to as the QB node) an output unit including a pull-down transistor for outputting a first gate-off voltage to the output terminal;
a Q node charging unit charging the Q node;
a Q node discharging unit discharging the Q node;
a QB node charging unit charging the QB node; and
and a QB node discharging unit discharging the QB node,
A gate driver in which a charging timing of the QB node through the QB node charging unit and a discharging timing of the QB node through the QB node discharging unit are separated. The method according to claim 1,
The QB node charging unit
a first QB charging transistor for providing a high potential voltage to the QB node in response to a start signal; and
and a second QB charging transistor for providing the high potential voltage to the QB node in response to an output of a preceding stage. 3. The method according to claim 2,
The QB node charging unit
Further comprising a capacitor for providing the clock signal to the QB node,
The capacitor provides the clock signal during the floating period of the QB node to periodically increase the high floating voltage of the QB node. 3. The method according to claim 2,
The QB node charging unit
Further comprising a capacitor providing the voltage of the Q node of the preceding stage to the QB node,
The capacitor increases the high floating voltage of the QB node when the Q node of the preceding stage rises to the pre-charging voltage, and increases the low floating voltage of the QB node when the Q node of the preceding stage falls from the bootstrapping voltage. Descending gate driver. 3. The method according to claim 2,
The QB node charging unit
During the active period of each frame,
providing a first charging timing of the QB node by the first QB charging transistor and a second charging timing of the QB node via the first QB charging transistor;
A gate driver providing a first charging timing of the QB node before a discharging timing of the QB node, and providing a second charging timing of the QB node immediately after a discharging timing of the QB node. 6. The method of claim 5,
A first period between the first charging timing of the QB node and the discharging timing of the QB node, and a second period between the second charging timing of the QB node and the end timing of the active period of each frame, include: A gate driver that is a floating period that maintains a high floating voltage. 6. The method of claim 5,
The first charging timing of the QB node is provided at the same timing in the plurality of stages,
The second charging timing of the QB node is provided in an off period of the Q node immediately following an on period of the Q node in each stage. The method according to claim 1,
The QB node discharge unit
and a QB discharge transistor controlled by the Q node to provide a second gate-off voltage to the QB node. The method according to claim 1,
The QB node discharge unit
first and second QB discharge transistors controlled by the Q node and connected in series between the QB node and a second gate-off voltage to provide a discharge path of the QB node; and
and an offset transistor controlled by the QB node to provide a high potential voltage as an offset voltage to an intermediate node of the first and second QB discharge transistors. The method according to claim 1,
The QB node discharge unit
A gate driver comprising: a QB discharge transistor controlled by a set terminal to which one of an output of a preceding stage and a start signal is applied to provide a second gate-off voltage to the QB node. The method according to claim 1,
The Q node charging unit
a Q charging transistor controlled by a set terminal to which any one set signal of an output of a preceding stage and a start signal is applied to provide the set signal to the Q node;
wherein the Q charging transistor shares a gate electrode connected to the set terminal and includes first and second Q charging transistors connected in series between the set terminal and the Q node. The method according to claim 1,
The Q node discharge unit
a first Q discharge transistor controlled by the QB node and providing a second gate-off voltage to the Q node;
wherein the first Q discharge transistor shares a gate electrode connected to the QB node, and a gate driver including 1-1 and 1-2 Q discharge transistors connected in series between the Q node and the second gate-off voltage. . 13. The method of claim 12,
The Q node discharge unit
a second Q discharge transistor controlled by a reset terminal to which either a reset signal or an output of a subsequent stage is applied, the second Q discharge transistor providing a second gate-off voltage to the Q node;
wherein the second Q discharge transistor shares a gate electrode connected to the QB node and includes 2-1 and 2-2 Q discharge transistors connected in series between the Q node and the second gate-off voltage. . The method according to claim 1,
Each stage is
The Q node discharge unit further includes an output discharge transistor that is controlled by a reset terminal to which either a reset signal or an output of a subsequent stage is applied and provides a second gate-off voltage to the output terminal. 5. The method according to claim 4,
When each stage is the Nth stage (N is an integer greater than 4),
The output of the preceding stage uses the output of the N-4th preceding stage,
A gate driver in which a bootstrapping period of the Q node of the preceding stage overlaps a precharging period of the Q node of the Nth stage. 14. The method of claim 13,
When each stage is the Nth stage (N is an integer greater than 4),
The output of the following stage is a gate driver using the output of the N+4th preceding stage. panel to display the video,
A display device in which the gate driver according to any one of claims 1 to 16 is built in the panel.

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