KR20220087742A - Gate driver and display device having the same - Google Patents

Abstract

The present specification provides a gate driver capable of reducing leakage current and power consumption of a TFT, and a display device having the same. In the gate driver according to one aspect, each stage is pulled up under the control of the Q node and outputs a first clock signal input through the first clock terminal among the plurality of clocks to the output terminal; and the control of the QB node an output unit including a pull-down transistor for pulling down the output terminal by a control unit for charging and discharging the Q node and charging and discharging the QB node opposite to the Q node; and a QB stabilizing circuit for controlling the QB node using a second clock signal of the plurality of clocks and an output of a first preceding stage of the plurality of stages, wherein the QB stabilizing circuit is configured to: The QB node discharge transistor may include a QB node discharge transistor for maintaining the QB node as a gate-off voltage using the on voltage of the second clock signal and the on voltage of the output of the first preceding stage.

Description

GATE DRIVER AND DISPLAY DEVICE HAVING THE SAME

The present specification relates to a gate driver capable of reducing leakage current and power consumption of a TFT, and a display device having the same.

A display device includes a panel for displaying an image through a pixel matrix, and a driving circuit for driving the panel. Each of the pixels constituting the pixel matrix is independently driven by a thin film transistor (TFT). In the driving circuit, the gate driver drives the gate line connected to the TFT of each pixel, and the data driver drives the data line connected to the TFT.

The gate driver includes stages for respectively driving gate lines, and each stage is composed of a plurality of TFTs. As a gate driver, a gate-in-panel (GIP) method formed on a panel together with a TFT array of a pixel matrix is known.

When the N-type oxide TFT applied to the gate driver has a negative threshold voltage Vth, the low voltage applied to the gate for turn-off is not lower than the source voltage, so that the leakage current increases.

When the leakage current in the TFTs constituting the gate driver is large, the output waveform of the gate driver is distorted, so reliability is deteriorated and power consumption is increased. Therefore, a method for minimizing the leakage current is required.

The content of the background art described above is technical information that the inventor of the present specification possessed to derive an example of the present specification or acquired in the process of deriving an example of the present specification, and must be disclosed to the general public prior to the filing of the present specification It cannot be said to be a known technology.

The present specification provides a gate driver capable of reducing leakage current and power consumption of a TFT, and a display device having the same.

The problems to be solved in the various embodiments of the present specification are not limited to the problems mentioned above, and other problems not mentioned are clear to those of ordinary skill in the art to which the technical idea of the present specification belongs from the description below. can be understood clearly.

In the gate driver according to one aspect, each stage is pulled up under the control of the Q node and outputs a first clock signal input through the first clock terminal among the plurality of clocks to the output terminal; and the control of the QB node an output unit including a pull-down transistor for pulling down the output terminal by a control unit for charging and discharging the Q node and charging and discharging the QB node opposite to the Q node; and a QB stabilizing circuit for controlling the QB node using a second clock signal of the plurality of clocks and an output of a first preceding stage of the plurality of stages, wherein the QB stabilizing circuit is configured to: The QB node discharge transistor may include a QB node discharge transistor for maintaining the QB node as a gate-off voltage using the on voltage of the second clock signal and the on voltage of the output of the first preceding stage.

The QB stabilization circuit includes: a first capacitor connected between a second clock terminal to which a second clock signal is applied and a connection node; a second capacitor connected between a control terminal to which an output of the first preceding stage is applied and the connection node; and a QB discharge transistor controlled by the connection node and connected between the QB node and a power supply terminal to which the gate-off voltage is supplied. The QB stabilization circuit may further include an initialization transistor configured to initialize the connection node to the gate-off voltage in response to a stabilization signal during a vertical blank period of each frame.

During the precharging period of the Q node during the on period of the Q node, the QB discharge transistor is turned on by the connection node to which the on voltage of the second clock signal is transmitted through the first capacitor to discharge the QB node to the gate-off voltage. can

During the bootstrapping period of the Q node during the on period of the Q node, the QB discharge transistor is turned on by the connection node to which the on voltage of the output of the first preceding stage is transmitted through the second capacitor, thereby causing the QB node to the gate-off voltage. After discharging, the second clock signal, the turn-on voltage, and the turn-on voltage of the output of the first preceding stage may be summed and applied to the connection node during a portion of the precharging period.

The control unit may include: a first charging unit including a Q charging transistor for precharging a Q node to the set signal in response to a set signal that is one of a start signal and an output of a second preceding stage; a second charging unit including a QB charging transistor that charges the QB node to a high potential voltage; A first Q discharge transistor for discharging the Q node to the gate-off voltage under the control of the QB node, and a second Q discharge for discharging the Q node to the gate-off voltage in response to any one of a reset signal and an output of a subsequent stage a first discharge unit including a transistor; and a first QB discharge transistor for discharging the QB node to a gate-off voltage under the control of the Q node, and a second QB discharging transistor for discharging the QB node to the second gate-off voltage in response to a set signal. It may include a discharge unit.

The output unit further includes a second pull-up transistor for outputting a first clock signal to the carry terminal in response to the control of the Q node, and a second pull-down transistor for outputting a gate-off voltage to the carry terminal in response to the control of the QB node, , the pull-down transistor of the output unit may output a second gate-off voltage higher than the gate-off voltage to the output terminal in response to the control of the QB node.

The first discharge unit may further include an output discharge transistor for discharging the output terminal to the second gate-off voltage in response to the reset signal and the output of the subsequent stage.

The first discharge unit further includes an offset transistor for generating an offset voltage of the high potential voltage during an ON period of the Q node in response to the control of the Q node and outputting it to the offset node, Q charging transistor, QB charging transistor, first Q each of the discharging transistor, the second Q discharging transistor includes a pair of series transistors, and an offset node to be connected with an intermediate node between the pair of Q charging transistors and the intermediate node between the pair of first Q discharging transistors. can

Each stage includes: a first stabilization transistor configured to reset the Q node to a gate-off voltage in response to a stabilization signal during a vertical blank period of each frame; a second stabilization transistor for resetting the QB node to a gate-off voltage in response to the stabilization signal; a third stabilization transistor configured to reset the carry terminal to a gate-off voltage in response to the stabilization signal; and a fourth stabilization transistor configured to reset the output terminal to a second gate-off voltage in response to the stabilization signal, wherein the first stabilization transistor includes a pair of first stabilization transistors connected in series, the offset The node may be connected with an intermediate node between the pair of first stabilization transistors.

The first clock signal is a clock signal inverted in phase from the second clock signal, the output of the first preceding stage is the output of the n-2 th (n is an integer greater than 4) preceding stage, and the output of the second preceding stage is This is the output of the n-4 th preceding stage, and the output of the n-2 th preceding stage and the on voltage section of the second clock signal may overlap during the on period of the Q node.

In the off period of the Q node, the QB node may maintain the on voltage when the first clock signal is the on voltage, and the QB node may maintain the off voltage when the second clock signal is the on voltage.

A display device according to an aspect may include the above-described gate driver.

Specific details according to various embodiments other than the means for solving the above-mentioned problems are included in the description and drawings below.

A gate driver and a display device according to one aspect use a QB stabilization circuit to stably maintain a sufficiently low gate-off voltage during the on period of the Q node by using a QB stabilization circuit even when the threshold voltage of the TFT shifts negatively. By minimizing the leakage current, output failure can be prevented and power consumption can be reduced.

A gate driver and a display device according to one aspect use a coplanar-type oxide TFT and use a QB stabilization circuit to stably pull down a QB node even when a negative threshold voltage is used to minimize leakage current to minimize an output waveform distortion can be prevented and power consumption can be reduced.

A gate driver and a display device according to an aspect may prevent multi-output failure and reduce power consumption by preventing a ripple of a Q node by a high voltage of the QB node using a QB stabilization circuit.

Since the contents of the problems to be solved, the problem solving means, and the effects mentioned above do not specify the essential characteristics of the claims, the scope of the claims is not limited by the matters described in the content of the invention.

The accompanying drawings are provided to help understanding of the embodiments of the present specification, and embodiments are provided together with detailed descriptions. However, the technical features of the present embodiment are not limited to specific drawings, and features disclosed in each drawing may be combined with each other to constitute a new embodiment.
1 is a block diagram illustrating a configuration of a display apparatus according to an exemplary embodiment.
2 is a block diagram schematically illustrating some stages of a gate driver according to an exemplary embodiment.
3 is a cross-sectional view illustrating a structure of a coplanar oxide TFT according to an embodiment.
4 is an equivalent circuit diagram illustrating a configuration of each stage according to an embodiment.
FIG. 5 is a driving waveform diagram of the stage shown in FIG. 4 .
6 is an equivalent circuit diagram illustrating a configuration of each stage according to an exemplary embodiment.
FIG. 7 is a driving waveform diagram of the stage shown in FIG. 6 .
8 is a waveform diagram illustrating a comparison between an output voltage according to a threshold voltage of a TFT in a stage of a gate driver according to a related art and an exemplary embodiment.
9 is a waveform diagram illustrating a comparison of the maximum voltage of a Q node according to a threshold voltage of a TFT in a stage of a gate driver according to a related art and an embodiment.
10 is a waveform diagram illustrating a comparison between voltages of a Q node and a QB node in a stage of a gate driver according to a related art and an exemplary embodiment.
11 is a diagram illustrating a QB node voltage at a bootstrapping time according to a threshold voltage of a TFT in a stage of a gate driver according to a related art and an embodiment.

Advantages and features of the present specification, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments allow the disclosure of the present specification to be complete, and common knowledge in the technical field to which this specification belongs It is provided to fully inform those who have the scope of the invention, and the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and thus the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in the description of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted. When "includes," "has," "consisting of," etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, even if there is no explicit description of the error range, it is interpreted as including the error range.

In the case of a description of the positional relationship, for example, when the positional relationship of the two parts is described as "on," "upper," "lower," "nextly", for example, "just" Alternatively, one or more other parts may be placed between two parts unless "directly" is used.

In the case of a description of a temporal relationship, when the temporal precedence is described as “after,” to “following,” “after,” “before”, etc., it is not continuous unless “immediately” or “directly” is used. cases may be included.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

In describing the components of the present specification, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected,” “coupled,” or “connected” to another component, the component may be directly connected or connected to the other component, but indirectly without specifically expressly stated. It should be understood that other components may be “interposed” between each component that is connected or can be connected.

“At least one” should be understood to include all combinations of one or more of the associated elements. For example, the meaning of “at least one of the first, second, and third components” means not only the first, second, or third components, but also two of the first, second, and third components. It can be said to include a combination of all or more components.

Each feature of the various embodiments of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship. may be

Hereinafter, referring to the embodiments of the present specification through the accompanying drawings and embodiments, as follows. The scales of the components shown in the drawings have different scales from the actual ones for convenience of description, and thus are not limited to the scales shown in the drawings.

1 is a block diagram schematically showing the configuration of a display device according to an embodiment of the present invention, and FIG. 2 is a block diagram schematically showing some stages of a gate driver according to an embodiment.

The display device according to an embodiment may be any one of various display devices including a liquid crystal display device, an electroluminescent display device, a micro LED (Light Emitting Diode) display device, and the like. The electroluminescent display device may be an organic light emitting diode (OLED) display device, a quantum dot light emitting diode (Quantum-dot Light Emitting Diode) display device, or an inorganic light emitting diode (Inorganic Light Emitting Diode) display device.

Referring to FIG. 1 , the display device includes a panel 100 , a GIP-type gate driver 200 , a data driver 300 , a timing controller 400 , a level shifter 600 , a gamma voltage generator 700 , and a power supply. management circuitry 500 and the like.

The power management circuit 500 uses an input voltage supplied from the outside to configure all the components of the display device, that is, the panel 100 , the gate driver 200 , the data driver 300 , the timing controller 400 , and the level shifter 600 . ) and the gamma voltage generator 700 may generate and output various driving voltages necessary for the operation.

The timing controller 400 may receive image data and synchronization signals from an external host system. The host system may be any one of a system of a portable terminal such as a computer, a TV system, a set-top box, a tablet, or a mobile phone. The synchronization signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 400 may perform various image processing such as luminance correction or image quality correction for reducing power consumption on the image data, and may supply the image-processed data to the data driver 300 .

The timing controller 400 generates and supplies a plurality of data control signals to the data driver 300 by using the synchronization signals and the internally stored timing setting information (start timing, pulse width, etc.), and provides the plurality of control signals. It can be generated and supplied to the level shifter 600 .

The gamma voltage generator 700 may generate a reference gamma voltage set including a plurality of reference gamma voltages having different voltage levels and supply it to the data driver 300 . The gamma voltage generator 700 may generate a plurality of reference gamma voltages corresponding to the gamma characteristics of the display device under the control of the timing controller 400 and supply the generated reference gamma voltages to the data driver 300 . The gamma voltage generator 700 may be configured as a programmable gamma IC, and receives gamma data from the timing controller 400 and generates or adjusts a reference gamma voltage level according to the gamma data to generate or adjust a reference gamma voltage level to the data driver 300 . can be output as

The data driver 300 is controlled according to a data control signal supplied from the timing controller 400 , converts digital data supplied from the timing controller 400 into an analog data signal, and corresponds to each data line of the panel 100 . Provides a data signal. The data driver 300 may convert digital data into an analog data signal using grayscale voltages in which a plurality of reference gamma voltages supplied from the gamma voltage generator 700 are subdivided.

The level shifter 600 may generate a plurality of gate control signals based on the plurality of control signals supplied from the timing controller 400 and supply them to the gate driver 200 . The level shifter 600 may level-shift the start signal and the reset signal supplied from the timing controller 400 , respectively, and supply it to the gate driver 200 . The level shifter 600 may generate a plurality of clocks for GIPs having different phases by logic-processing the on and off clocks supplied from the timing controller 400 and supply them to the gate driver 200 . The on clock may determine the rising timing of each of the clocks for GIP, and the off clock may determine the timing of each of the clocks for the GIP.

The panel 100 displays an image through the display area AA in which the sub-pixels SP are arranged in a matrix form. Each subpixel SP has a red (R) subpixel emitting red light, a green (G) subpixel emitting green light, a blue (B) subpixel emitting blue light, and a white (W) subpixel emitting white light. any one of them, and is independently driven by at least one TFT. The unit pixel may be composed of a combination of two, three, or four sub-pixels having different colors.

The panel 100 may further include a touch sensor screen for sensing a user's touch by overlapping the display area AA as a whole, and the touch sensor screen is embedded in the panel 100 or the display area AA of the panel 100 . ) can be placed on

The gate driver 200 is composed of TFTs formed in the same process as the TFT array disposed in the display area AA of the panel 100 , and is formed in a bezel area on either side or one side of the panel 100 , in a gate-in (GIP) area. Panel) type.

The gate driver 200 may receive a plurality of gate control signals from the level shifter 600 and perform a shift operation to individually drive the gate lines GL of the panel 100 . The gate driver 200 is configured as a shift register having a plurality of stages that are connected to each other to drive the plurality of gate lines GL, respectively, and generate individual gate outputs.

In FIG. 2 , for convenience, three stages STn-1, STn, STn+1, n each generating three gate outputs OUTn-1, OUTn, and OUTn+1 among a plurality of stages constituting the gate driver 200 . is a natural number) only.

Each stage STn may receive at least one clock signal from among a plurality of clock signals CLKs having different phases. Each stage STn may output an input clock pulse as a scan pulse of the gate output OUTn in response to any one (set signal) of the start signal and the output of the preceding stage. Each stage STn may output a gate-off voltage of the gate output OUTn in response to any one (reset signal) of a reset signal and an output of a subsequent stage. The gate output OUTn or the carry output of each stage STn may be used as a carry signal to be supplied to another stage as a set signal or a reset signal. The preceding stage refers to any one of stages that are located before (upper) the corresponding stage or output scan pulses before the corresponding stage, and the following stage is located after (lower) the corresponding stage or scan pulses after the corresponding stage It means any one of the stages that output .

TFTs disposed in the display area AA of the panel 100 and the bezel area including the gate driver 200 include an amorphous TFT using an amorphous silicon semiconductor layer, a poly TFT using a polysilicon semiconductor layer, and a metal oxide semiconductor layer. At least one of oxide TFTs may be applied.

For example, in the panel 100, an oxide TFT with higher mobility than an amorphous silicon TFT, a lower temperature process than a polysilicon TFT, and easy application to a large area can be applied, and Coplanar with good TFT characteristics. type of oxide TFT can be applied.

3 is a cross-sectional view illustrating a structure of a coplanar-type oxide TFT according to an exemplary embodiment.

Referring to FIG. 3 , the coplanar-type oxide TFT includes a light blocking layer LS on a substrate SUB, a buffer film BF covering the light blocking layer LS, a semiconductor layer ACT on the buffer film BF, The gate insulating layer GI and the gate electrode GE stacked on the semiconductor layer ACT, the interlayer insulating layer ILD covering the semiconductor layer ACT, the gate insulating layer GI, and the gate electrode GE, and the interlayer insulating layer ( First and second source/drain electrodes SD1 and SD2 respectively connected to the first and second conductive regions CA1 and CA2 of the semiconductor layer ACT through the contact hole of the ILD are provided. One of the first and second source/drain electrodes SD1 and SD2 is a source electrode and the other is a drain electrode.

The semiconductor layer ACT is disposed on both sides of the channel region CH overlapping the gate electrode GE with the gate insulating layer GI interposed therebetween, and first and second source/drain electrodes ( First and second conductive regions CA1 and CA2 conductively formed to be in ohmic contact with SD1 and SD2, respectively. The semiconductor layer ACT includes an oxide semiconductor material. For example, the semiconductor layer ACT is IZO (InZnO), IGO (InGaO), ITO (InSnO), IGZO (InGaZnO), IGZTO (InGaZnSnO), GZTO (GaZnSnO), GZO (GaZnO). It may include at least one of a system and an ITZO (InSnZnO) system.

The light blocking layer LS is made of an opaque metal and absorbs external or internal light to prevent light from entering the oxide semiconductor layer ACT. The light blocking layer LS may be electrically floating or may be connected to any one of the first and second source/drain electrodes SD1 and SD2 .

Meanwhile, since the light blocking layer LS is used as a bottom gate electrode and the gate electrode GE is used as a top gate electrode, the coplanar oxide TFT shown in FIG. 3 may operate as a double gate TFT.

Compared to the back channel etched type oxide TFT, the coplanar oxide TFT has a thinner gate insulating film (GI), a larger on-current (Ion), and a steep gate voltage-to-current characteristic. Since the S-factor, which is the reciprocal of , is small and the parasitic capacitance is small, when applied to the gate driver 200 , high-speed driving is possible and the TFT size can be reduced. The S-factor is the current-voltage characteristic of the TFT, and it means the magnitude of the gate voltage required to increase the drain current by a factor of 10 when a gate voltage lower than the threshold voltage is applied.

The gate driver 200 according to an embodiment may use an N-type coplanar oxide TFT, and when each TFT is turned off, the off voltage applied to the gate electrode GE is applied to the source electrode SD1. In most cases, it is the same as the voltage. At this time, when the TFT has a negative threshold voltage (Vth<0), the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth) becomes greater than 0V (Vgs-Vth>0V), so that the leakage current increases and the gate output The waveform may be distorted.

To prevent this, in the gate driver 200 according to an embodiment, a period in which the Q node controlling the pull-up TFT is turned on (pre-charging period and bootstrapping period) in order to supply an input clock to the gate output in each stage while pulling-down the QB node to the gate-off voltage (VSS) through the QB discharge transistor (T5q, FIG. 4) controlled by the Q node, and additionally using the QB stabilization circuit (60, FIG. 4) The voltage of the QB node may be stably maintained as the gate-off voltage (VSS). Accordingly, by stably turning off the Q discharge transistor T3 ( FIG. 4 ) controlled by the QB node during the on period of the Q node, the leakage current of the Q node through the transistor T3 can be minimized. A detailed description thereof will be provided later.

4 is an equivalent circuit diagram illustrating the configuration of each stage STn in the gate driver according to an exemplary embodiment, and FIG. 5 is a driving waveform diagram of the stage STn shown in FIG. 4 .

Referring to FIG. 4 , each stage STn includes a first charging unit 10 , a first discharging unit 20 , a second charging unit 30 , a second discharging unit 40 , an output unit 50 , and QB stabilization. A circuit 60 may be provided. The first charging unit 10 , the first discharging unit 20 , the second charging unit 30 , the second discharging unit 40 , and the QB stabilizing circuit 60 all connect the Q node and the QB node of the output unit 50 . It can be defined as a control unit that controls. A Q node may be defined as a first control node, and a QB node may be defined as a second control node.

The TFTs T1, T3, T3n, T4, T5c, T5q, T6, T7, T8, and T9 constituting each stage STn are of the coplanar type including the light blocking layer LS as shown in FIG. 3 . It may be an oxide TFT of

Each stage STn includes a set terminal 2 to which any one of a start signal VST and an output CRn-4 of a preceding stage is applied as a set signal, and a first power terminal to which a high potential voltage VDD is applied. 4), the second power terminal 8 to which the gate-off voltage VSS is applied, the first clock terminal 12 to which the clock signal CLKn is applied, the output terminal 14 to which the gate output OUTn is applied, The reset terminal 16 to which any one of the reset signal and the output (CRn+4) of the succeeding stage is applied as a reset signal, the second clock terminal 5 to which the inverted clock signal CLK_B is applied, the output of the other preceding stage ( It may include a control terminal 7 to which CRn-2 is applied, and a stabilization terminal 18 to which a stabilization signal STB is applied. The gate-off voltage VSS may be defined as a gate low voltage. The gate output OUTn of each stage STn may be output as a carry signal CRn to another stage.

The clock signal CLKn applied to the first clock terminal 12 of each stage STn is any one of the eight-phase clock signals CLK1 to CLK8, and the inverted clock signal applied to the second clock terminal 5 is CLK_B may be another one of the eight-phase clock signals CLK1 to CLK8 whose phase is inverted from the clock signal CLKn. Each of the clock signal CLKn and the inverted clock signal CLK_B may be a pulse waveform in which a high voltage (gate-on voltage) period of a 3H period and a low logic (gate-off voltage) period of a 4H period are alternately repeated. In contrast, each of the clock signal CLKn and the inverted clock signal CLK_B may be a pulse waveform in which a high voltage (gate-on voltage) section of a 4H period and a low logic (gate-off voltage) section of a 4H period are alternately repeated. have.

The first charging unit 10 may receive the start signal VST or the output CRn-4 of the preceding stage as a set signal through the set terminal 2 to charge the Q node with the set signal. The output CRn-4 of the preceding stage may be the gate output OUTn-4 output from the n-4th preceding stage.

The first charging unit 10 may include a diode-type Q charging transistor T1 having a gate electrode and a drain electrode connected to the set terminal 2 and a source electrode connected to a Q node. For example, as shown in FIG. 5 , the Q charging transistor T1 is turned on when the output CRn-4 of the n-4th preceding stage is at a high voltage to precharge the Q node to a high voltage. have.

The first discharge unit 20 may discharge the Q node to the gate-off voltage VSS of the second power terminal 8 in response to the control of the QB node. The first discharge unit 20 receives the reset signal or the output (CRn+4) of the subsequent stage as a reset signal through the reset terminal 16 to convert the Q node to the gate-off voltage (VSS) of the second power terminal 8 . can be discharged with The output CRn+4 of the subsequent stage may be the gate output OUTn+4 output from the n+4th post stage.

The first discharge unit 20 may include a first Q discharge transistor T3 having a gate electrode connected to the QB node, a source electrode connected to the second power terminal 8 , and a drain electrode connected to the Q node. . The first discharge unit 20 has a gate electrode connected to a reset terminal 16 to which an output signal (CRn+4) or a reset signal of a subsequent stage is supplied, a second power supply terminal 8 is a source electrode, and a drain electrode is a Q node. The connected second Q discharge transistor T3n may be further included.

For example, as shown in FIG. 5 , the first Q discharge transistor T3 discharges the Q node to the gate-off voltage VSS when the QB node is at a high voltage during the Q-node off period Qoff to generate a clock signal. It is possible to prevent the ripple of the Q node due to the transition of (CLKn) and to prevent output failure due to the ripple. As shown in FIG. 5 , the second Q discharge transistor T3n is turned on when the output (CRn+4) of the subsequent stage is a high voltage to connect the Q node to the gate-off voltage (VSS) of the second power supply terminal 8 . ) can be discharged.

The second charging unit 30 may charge the QB node to the high potential voltage VDD in response to the high potential voltage VDD applied to the first power terminal 4 . The second charging unit 30 may include a diode-type QB charging transistor T4 having a gate electrode and a drain electrode connected to the first power terminal 4 and a source electrode connected to the QB node. The QB charging transistor T4 is turned on by the high potential voltage VDD applied during the active period of each frame to charge the QB node to the high potential voltage VDD.

The second discharge unit 40 may discharge the QB node to the gate-off voltage VSS of the second power terminal 8 in response to the control of the Q node. The second discharge unit 40 connects the QB node to the gate-off voltage of the second power supply terminal 8 in response to the control of the set terminal 2 to which the start signal VST or the output CRn-4 of the preceding stage is supplied. (VSS) can be discharged. The output CRn-4 of the preceding stage may be the gate output OUTn-4 output from the n-4th preceding stage.

The second discharge unit 40 may include a first QB discharge transistor T5q having a gate electrode connected to the Q node, a source electrode connected to the second power terminal 8 , and a drain electrode connected to the QB node. . The second discharge unit 40 further includes a second QB discharge transistor T5c having a gate electrode connected to the set terminal 2 , a source electrode connected to the second power supply terminal 8 , and a drain electrode connected to the QB node. may include

For example, as shown in FIG. 5 , the first QB discharge transistor T5q is turned on during the on period Qon of the Q node in which the Q node is a high voltage to discharge the QB node to the gate-off voltage VSS. can do it The second QB discharge transistor T5c is turned on when the set terminal 2 has a high voltage to discharge the QB node to the gate-off voltage VSS. Accordingly, even if the QB charging transistor T4 maintains a turn-on state by the high potential voltage VDD during the active period of each frame, as shown in FIG. 5 , during the on period Qon of the Q node, the QB node is discharged through the first and second QB discharge transistors T5q and T5c, so that the QB node may operate in a voltage state opposite to that of the Q node.

The output unit 50 is pulled up under the control of the Q node and outputs the clock signal CLKn applied to the first clock terminal 12 to the gate output OUTn through the output terminal 14 . The pull-up transistor T6 is pulled down by the control of the QB node opposite to the Q node, and the gate-off voltage VSS from the second power supply terminal 8 is output to the gate through the output terminal 14 ( OUTn) and a pull-down transistor T7.

The pull-up transistor T6 may have a gate electrode connected to the Q node, a source electrode connected to the output terminal 14 , and a drain electrode connected to the clock terminal 12 . For example, as shown in FIG. 5 , the pull-up transistor T6 is turned on during the on period Qon of the Q node to transmit the clock signal CLKn from the clock terminal 12 through the output terminal 14 . It can be output as a scan signal of the gate output OUTn. During the on period Qon of the Q node, the pull-up transistor T6 may output the gate output OUTn having the gate-on voltage VGH and the gate-off voltage VSS of the clock signal CLKn.

The output unit 50 further includes a first capacitor CB connected between the gate electrode (Q node) and the source electrode (output terminal 14) of the pull-up TFT T6. The first capacitor CB bootstraps the high voltage of the Q node as shown in FIG. 5 when the pull-up TFT T6 is pulled up to output the gate-on voltage VGH of the clock signal CLKn. to reduce the rising time of the gate output OUTn by amplifying it.

The pull-down transistor T7 may have a gate electrode connected to the QB node, a source electrode connected to the second power supply terminal 8 , and a drain electrode connected to the output terminal 14 . For example, the pull-down transistor T7 is turned on during the on period and off period of the QB node corresponding to the off period Qoff of the Q node as shown in FIG. The gate-off voltage VSS may be output as the off voltage of the gate output OUTn through the output terminal 14 .

The QB stabilization circuit 60 responds to the inverted clock signal CLK_B applied through the second clock terminal 5 and the output CRn-2 of the preceding stage applied through the control terminal 7 to a Q node During the on period Qon of , the QB node may be stably discharged to the gate-off voltage VSS. At this time, the first QB discharge transistor T5q is also turned on by the on voltage of the Q node to discharge the QB node to the gate-off voltage VSS. Accordingly, during the on period Qon of the Q node, the QB stabilization circuit 60 may pull down the QB node together with the first QB discharge transistor T5q to the gate-off voltage VSS to stably maintain it.

In addition, the QB stabilization circuit 60 maintains the QB node in a high state when the inverted clock signal CLK_B has a low voltage, that is, when the clock signal CLK is a high voltage during the off period Qoff of the Q node. It is possible to prevent the ripple of the Q node. The output CRn-2 of the preceding stage may be the gate output OUTn-2 output from the n-2 th preceding stage.

The QB stabilization circuit 60 may include two transistors T8 and T9 and two capacitors C1 and C2.

The QB stabilization circuit 60 is connected between the first clock terminal 5 and the connection node A to transfer the inverted clock signal CLK_B to the connection node A, a first capacitor C1, and a control terminal 7 ) and a second capacitor C2 connected between the connection node A and transferring the output CRn-2 of the n-2 th preceding stage to the connection node A.

QB stabilization circuit 60 is applied to stabilization terminal 18, QB discharge transistor T9 which is controlled by connection node A to discharge the QB node to the gate-off voltage VSS of second power supply terminal 8 An initialization transistor T8 controlled by the stabilization signal STB to initialize the connection node A to the gate-off voltage VSS of the second power terminal 8 may be included. The QB discharge transistor T9 may have a gate electrode connected to the connection node A, a source electrode connected to the second power terminal 8 , and a drain electrode connected to the QB node. In the initialization transistor T8 , a gate electrode may be connected to the stabilization terminal 18 , a source electrode may be connected to the second power terminal 8 , and a drain electrode may be connected to the connection node A .

Referring to FIG. 5 , the initialization transistor T8 is turned on by the high voltage of the stabilization signal STB supplied to the stabilization terminal 18 during the vertical blank period of each frame according to the vertical synchronization signal, and the connection node A ) may be initialized to the gate-off voltage VSS. During the active period of each frame, the initialization transistor T8 is turned off by the low voltage of the stabilization signal STB.

During the on period Qon of the Q node, the first QB discharge transistor T5q of the second discharge unit 40 is turned on by the on voltage of the Q node so that the QB node is discharged to the gate-off voltage VSS, and have.

During the on period Qon of the Q node, during the period in which the Q node is precharged to a high voltage by the output CRn-4 of the n-4 th preceding stage, the first capacitor C1 receives the inverted clock signal CLK_B ) by transferring the high voltage to the connection node A, the QB discharge transistor T9 is turned on and the QB node is further pulled down to the gate-off voltage VSS to be discharged.

Subsequently, during the on period Qon of the Q node, during a partial precharging period and during the initial stage in which the Q node is bootstrapped according to the clock signal CLKn, the second capacitor C2 is the output of the n-2 th preceding stage. By transferring the high voltage of (CRn-2) to the connection node A, the QB discharge transistor T9 maintains a turned-on state so that the QB node can stably maintain the gate-off voltage VSS, which is a pull-down state. .

Before bootstrapping during the on period Qon of the Q node, the connection node A is obtained by adding the high voltage of the output CRn-2 of the n-2 th preceding stage to the high voltage of the inverted clock signal CLK_B. It may rise higher, and as a result, the QB discharge transistor T9 is strongly turned on to stably maintain the gate-off voltage VSS of the QB node. Accordingly, at the bootstrapping time during the on period Qon of the Q node, the QB node may stably maintain the gate-off voltage VSS, and the first Q discharge transistor T3 may turn- By stably maintaining the off state, leakage current can be minimized, and distortion of the Q node and the gate output OUTn due to the leakage current can be prevented.

In addition, the QB stabilization circuit 60 turns on the QB discharge transistor T9 whenever the inverted clock signal CLK_B is at a high voltage during the off period Qoff of the Q node so that the QB node receives the gate-off voltage VSS. ), while the QB discharge transistor T9 is turned off whenever the inverted clock signal CLK_B is a low logic voltage, that is, whenever the clock signal CLK is a high voltage voltage, the QB node is connected to the QB charging transistor. It can be charged to a high state through (T4). Accordingly, the first Q discharge transistor T3 discharges the Q node to the gate-off voltage VSS by the high state of the QB node whenever the clock signal CLKn transitions from the low state to the high state. It is possible to prevent the ripple of the Q node according to (CLKn) and to prevent output failure due to the ripple.

6 is an equivalent circuit diagram illustrating a configuration of each stage STn in a gate driver according to an exemplary embodiment.

6 , each stage STn includes a first charging unit 10A, a first discharging unit 20A, a second charging unit 30A, a second discharging unit 40, an output unit 50A, and QB stabilization. A circuit 60 and a stabilizing unit 70 may be provided. The first charging unit 10A, the first discharging unit 20A, the second charging unit 30A, the second discharging unit 40 , the QB stabilizing circuit 60 , and the stabilizing unit 70 may be defined as a control unit. Transistors T1, T3, T3n, T3q, T3no, T4, T5q, T5c, T6, T6c, T7, T7c, T8, and T9 constituting each stage STn have a light blocking layer ( LS) may be a coplanar type oxide TFT.

Hereinafter, FIG. 6 will only describe the changed configurations compared to FIG. 4 , and the description of the remaining redundant configurations will be omitted or simply referred to.

The output unit 50A includes, in addition to the first pull-up transistor T6 and the first pull-down transistor T7 connected to the output terminal 14 , the second pull-up transistor T6c and the second pull-up transistor T6c connected to the carry terminal 15 . 2 may further include a pull-down transistor T7c. A first gate-off voltage VSS is applied through the second power terminal 8 , and a second gate-off voltage VGL higher than the first gate-off voltage VSS is applied through the third power terminal 9 . can be

The second pull-up transistor T6c is pulled-up during the on-period Qon of the Q node under the control of the Q node to transmit the clock signal CLKn applied to the clock terminal 12 to the carry terminal 15 . through the carry signal CRn. The second pull-down transistor T7c is pulled-down during the off period Qoff of the Q node under the control of the QB node to transfer the first gate-off voltage VSS from the second power supply terminal 8 to the carry terminal. It can be output as the carry signal CRn through (15).

The first charging unit 10A may include a pair of Q charging transistors T1 having a gate electrode commonly connected to the set terminal 2 and serially connected between the set terminal 2 and the Q node. The pair of Q charging transistors T1 are turned on when the start signal VST or the carry signal CRn-4 of the preceding stage is at a high voltage to precharge the Q node. The carry signal CRn-4 of the preceding stage refers to a carry signal output through the carry terminal of the n-4th preceding stage.

The first discharge unit 20A may include a pair of first Q discharge transistors T3 having a gate electrode commonly connected to the QB node and serially connected between the Q node and the third power terminal 8 . The pair of first Q discharge transistors T3 may be turned on when the QB node has a high voltage to discharge the Q node to the first gate-off voltage VSS of the second power terminal 8 .

The first discharge unit 20A has a gate electrode commonly connected to a reset terminal 16 to which a carry signal CRn+4 or a reset signal of a subsequent stage is supplied, and is serially connected between the Q node and the third power supply terminal 8 . A pair of second Q discharge transistors T3n may be further included. The carry signal CRn+4 of the subsequent stage refers to a carry signal output through the carry terminal of the n+4th subsequent stage. The pair of second Q discharge transistors T3n are turned on when the carry signal CRn+4 or the reset signal of the subsequent stage is at a high voltage to connect the Q node to the first gate-off voltage of the second power supply terminal 8 . (VSS) can be discharged.

The first discharge unit 20A has an output discharge transistor T3no having a gate electrode connected to a reset terminal 16 , a drain electrode connected to an output terminal 14 , and a source electrode connected to a third power supply terminal 9 . may further include. The output discharge transistor T3no is turned on when the carry signal CRn+4 or the reset signal of the subsequent stage is at a high voltage to connect the output terminal 14 to the second gate-off voltage VGL of the third power supply terminal 9 . ) can be rapidly discharged.

The first discharge unit 20A generates an offset transistor T3q for generating an offset voltage at a transistor-transistor offset (TTO) node during the on period Qon of the Q node in response to the control of the Q node. may include more. The offset transistor T3q has a gate electrode connected to the Q node, a drain electrode connected to the first power supply terminal 4 , and a source electrode connected to the TTO node. The offset transistor T3q is turned on during the on period Qon in which the Q node is a high voltage and supplies the high potential voltage VDD from the first power supply terminal 4 as an offset voltage to the TTO node and A leakage current of the connected transistors T1 , T3 , and T3n may be minimized.

The TTO node is an intermediate node between a pair of Q charging transistors T1 , an intermediate node between a pair of first Q discharge transistors T3 , and an intermediate node between a pair of second Q discharge transistors T3n. It can be commonly connected to a node.

The offset voltage of the high potential voltage VDD to the source electrode through the TTO node among the pair of first Q discharge transistors T3 that are turned off by the low logic of the QB node during the on period Qon of the Q node The gate-source voltage Vgs of any one of the applied transistors becomes a negative value lower than the threshold voltage, thereby minimizing leakage current.

The offset voltage of the high potential voltage VDD to the source electrode through the TTO node among the pair of second Q discharge transistors T3n that are turned off by the low logic of the QB node during the on period Qon of the Q node The gate-source voltage Vgs of any one of the applied transistors becomes a negative value lower than the threshold voltage, thereby minimizing leakage current.

Offset of the high potential voltage VDD to the source electrode through the TTO node among the pair of Q charging transistors T1 that are turned off by the low logic of the set terminal 2 during the on period Qon of the Q node In any one of the transistors to which the voltage is applied, the gate-source voltage Vgs becomes a negative value lower than the threshold voltage to minimize leakage current.

The second charging unit 30A has a gate electrode commonly connected to the first power supply terminal 4 to which the high potential voltage VDD is applied and is connected in series between the first power supply terminal 4 and the QB node to power the QB node. A pair of QB charging transistors T4 charged with the above voltage VDD may be included.

The second discharge unit 40 discharges the QB node to the first gate-off voltage VSS of the second power terminal 8 during the on-period Qon of the Q node in response to the control of the Q node. a transistor T5q and a second QB discharge transistor T5c for discharging the QB node to the second gate-off voltage VSS of the third power supply terminal 8 in response to the control of the set terminal 2 . have.

The stabilization unit 70 connects the Q node, the QB node, and the carry terminal 15 to the first gate-off voltage VSS of the second power supply terminal 8, respectively, in response to the stabilization signal STB applied to the stabilization terminal 18 . ) to discharge the first to third stabilization transistors (Tst_q, Tst_qb, Tst_cr), and a fourth stabilization transistor ( Tst_out) may be included.

The first to fourth stabilization transistors Tst_q, Tst_qb, Tst_r, and Tst_out are simultaneously turned by the high voltage of the stabilization signal STB supplied to the stabilization terminal 18 during the vertical blank period of each frame according to the vertical synchronization signal- It is turned on and turned off by the low logic of the stabilization signal STB during the active period of each frame. The first stabilization transistor Tst_q discharges the Q node, the second stabilization transistor Tst_qb discharges the QB node, and the third stabilization transistor Tst_cr discharges the carry terminal 15 to the first gate-off voltage VSS, The fourth stabilization transistor Tst_out initializes all main nodes of each stage STn by discharging the output terminal 14 to the second gate-off voltage VGL.

The first stabilization transistor Tst_q may include a pair of stabilization transistors Tst_q connected in series, and an intermediate node between the pair of first stabilization transistors Tst_q is connected to a TTO node to which an offset voltage is applied. can be Among the pair of first stabilization transistors Tst_q that are turned off by the low logic of the stabilization signal STB during the on period Qon of the Q node, the high potential voltage VDD is applied to the source electrode through the TTO node. In any one of the transistors to which the offset voltage of is applied, the gate-source voltage Vgs becomes a negative value lower than the threshold voltage, thereby minimizing leakage current.

The QB stabilization circuit 60 includes a first capacitor C1 connected between the first clock terminal 5 and the connection node A, and a second capacitor C1 connected between the control terminal 7 and the connection node A ( C2), a QB discharge transistor T9 controlled by the connection node A and connected between the QB node second power supply terminal 8, the stabilization terminal 18 and controlled by the connection node A and the second It may include an initialization transistor T8 connected between the power supply terminal 8 .

The QB stabilization circuit 60 is configured at the beginning of the precharging period and bootstrapping period in which the inverted clock signal CLK_B and the output CRn-2 of the n-2 th preceding stage are high voltage during the on period Qon of the Q node. , the QB node may be pulled down to the gate-off voltage VSS through the QB discharge transistor T9 to stably maintain it. During the on period Qon of the Q node, the QB node is discharged to the gate-off voltage VSS through the first QB discharge transistor T5q of the second discharge unit 40 . Accordingly, even when the threshold voltage Vth of the TFT is negative during the on period Qon of the Q node, the QB node may stably maintain the gate-off voltage VSS. As a result, the first Q discharge transistor T3 is stably turned off by the sufficiently low and stable gate-off voltage VSS of the QB node to minimize the leakage current of the Q node through the first Q discharge transistor T3. and distortion of the Q node and the gate output OUTn due to the leakage current can be prevented.

Since the QB stabilization circuit 60 turns off the QB discharge transistor T9 whenever the inverted clock signal CLK_B is at a low voltage during the off period Qoff of the Q node, the QB node is charged and maintained in a high state, When the clock signal CLK transitions from a low voltage to a high voltage, the ripple of the Q node may be prevented.

FIG. 7 is a driving waveform diagram of each stage shown in FIG. 6 .

Referring to FIG. 7 , the high potential voltage VDD supplies the gate-on voltage VGH during the active period of each frame and supplies the gate-off voltage VSS during the vertical blank period. The stabilization signal STB supplies the high voltage stabilization voltage STB during the vertical blank period of each frame and supplies the gate-off voltage VSS during the active period.

As shown in FIG. 7 , each stage of the gate driver according to an embodiment has two phases inverted from among the eight-phase clock signals CLK1 to CLK8 in which a high voltage section partially overlaps each other while the phases are sequentially delayed as shown in FIG. 7 . A clock signal may be supplied.

In each of the eight-phase clock signals CLK1 to CLK8, a high voltage (gate-on voltage) section of a 4H period and a low logic (gate-off voltage) section of a 4H period are alternately repeated. The eight-phase clock signals CLK1 to CLK8 have a high voltage section sequentially phase-delayed by 1H period, and each clock signal is a high voltage section of each of the adjacent clocks having a 3H period, a 2H period, and a 1H period of the high voltage period. can overlap. These eight-phase clock signals CLK1 to CLK8 are sequentially output to the corresponding gate output OUT, so that each gate output OUT may have a high period of 4H period, thereby providing sufficient charging time during high-speed driving. .

In the eight-phase clock signals CLK1 to CLK8, a clock signal having an nth phase is applied to the output unit 50A through the first clock terminal 12 of each stage STn, and has an n+4th phase A clock signal may be applied to the QB stabilization circuit 60 through the second clock terminal 5 of each stage STn.

For example, the fifth clock signal CLK5 is applied to the first clock terminal 12 of the nth stage STn, and the first clock signal CLK1 inverted in phase from the fifth clock signal CLK5 is n It may be applied to the second clock terminal 5 of the th stage STn.

6 and 7 , the Qn node of the nth stage STn is precharged when the carry output CRn-4 of the n−4th preceding stage is a high voltage, and the fifth clock signal CLK5 is It is bootstrapped when the voltage is high and outputs the fifth clock signal CLK5 to the gate output OUTn through the output terminal 14 of the nth stage STn, and then the carry output CRn of the n+4th subsequent stage. When +4) is a high voltage, the second gate-off voltage VGL may be output through the output terminal 14 of the n-th stage STn.

The gate output OUTn of the n-th stage STn has a first gate-off voltage VSS that is a low voltage of the fifth clock signal CLK5 and a gate-on voltage VGH that is a high voltage during the on period Qon of the Qn node. ), and a second gate-off voltage VGL higher than the first gate-off voltage VSS may be output during the remaining period. The carry output outputs CRn-4, CRn-2, and CRn+4 of each stage may output the first gate-off voltage VSS as a low voltage and output the gate-on voltage VGH as a high voltage.

During the on period Qon of the Qn node, the QB node may be discharged to the gate-off voltage VSS through the first QB discharge transistor T5q of the second discharge unit 40 . During the on period Qon of the Qn node, the QB stabilization circuit 60 provides a pre-load in which the first clock signal CLK1 that is the inverted clock signal CLK_B and the carry output CRn-2 of the n-2 th preceding stage have a high voltage. At the beginning of the charging period and the bootstrapping period, the QB node is pulled down to the gate-off voltage (VSS) through the QB discharge transistor T9 turned on by the high voltage of the connection node A (see FIG. 5 ) to stably may be maintained, and the first Q discharge transistor T3 may be stably turned off by the QB node. Meanwhile, the leakage current of the Q node may be minimized through the first Q discharge transistor T3 , and distortion of the Q node and the gate output OUTn due to the leakage current may be prevented.

The carry output CRn-2 of the n-2th preceding stage overlaps the carry output CRn-4 of the n-4th preceding stage and the high voltage of the 2H period, and the gate output OUTn of the nth stage and 2H The high voltages of the periods may overlap.

In the QB stabilization circuit 60, whenever the first clock signal CLK1, which is the inverted clock signal CLK_B, has a low voltage during the off period Qoff of the Q node, the QB discharge transistor T9 is turned off so that the QB node is Since it is charged and maintained in a high state, it is possible to prevent ripple of the Q node when the second clock signal CLK5, which is the clock signal CLKn, transitions from a low voltage to a high voltage.

8 is a waveform diagram showing a comparison of an output voltage according to a threshold voltage of a TFT in a stage of a gate driver according to a related art and an embodiment, and FIG. It is a waveform diagram showing the comparison of the maximum voltage of the Q node according to the threshold voltage.

8 and 9, the stage of the gate driver according to the related art operates normally when the threshold voltage (Vth) of the TFT is 0V, so that the output voltage and the maximum voltage (Qmax) of the Q node reach the target voltage. Able to know. On the other hand, in the stage of the gate driver according to an exemplary embodiment, even when the threshold voltage (Vth) of the TFT is a negative voltage such as -1.5V, -1V, etc., it operates normally so that the output voltage and the maximum voltage (Qmax) of the Q node are the target. It can be seen that the voltage is reached. In addition, it can be seen that in the stage of the gate driver according to an exemplary embodiment, when the channel width of the QB discharge transistor T9 is large (W2>W1), the normal operation is performed even at a lower threshold voltage Vth.

10 is a waveform diagram illustrating a comparison between voltages of a Q node and a QB node in a stage of a gate driver according to a related art and an exemplary embodiment.

Referring to FIG. 10 , in the stage of the gate driver according to the related art, when the threshold voltage (Vth) of the TFT is a negative voltage, the QB node does not stably maintain the low voltage at the bootstrapping time of the Q node and partially rises. It can be seen that the voltage waveform of the Q node is distorted as the leakage current of the Q node increases as it occurs at the point. On the other hand, in the stage of the gate driver according to an embodiment, even if the threshold voltage (Vth) of the TFT shifts to a negative voltage, the QB node stably maintains the low voltage at the bootstrapping time of the Q node, so that the leakage current of the Q node is reduced. It can be seen that the voltage of the Q node operates normally by being minimized.

11 is a diagram illustrating a QB node voltage at a bootstrapping time according to a threshold voltage of a TFT in a stage of a gate driver according to a related art and an embodiment.

Referring to FIG. 11 , when the threshold voltage (Vth) of the TFT shifts to a negative voltage in the stage of the gate driver according to the related art, the voltage of the QB node does not stably maintain the low voltage at the bootstrapping time of the Q node. It can be seen that the increase On the other hand, in the stage of the gate driver according to an embodiment, it can be seen that the voltage of the QB node stably maintains the low voltage at the bootstrapping time of the Q node even when the threshold voltage Vth of the TFT shifts to a negative voltage. .

As described above, in the gate driver and display device according to an embodiment, the QB node stably maintains the gate-off voltage during the on-period of the Q node using the QB stabilization circuit even when the threshold voltage of the TFT shifts negatively to the Q node. By minimizing the leakage current, output failure can be prevented and power consumption due to the leakage current can be reduced.

The gate driver and the display device according to one aspect use a coplanar type oxide TFT and use the QB stabilization circuit to stably maintain the QB node even when the oxide TFT has a negative threshold voltage, so the leakage current is minimized. It is possible to prevent distortion of the output waveform and reduce power consumption due to leakage current.

A gate driver and a display device according to an aspect may prevent multi-output failure and reduce power consumption by preventing a leaf of a Q node by a high voltage of the QB node using a QB stabilization circuit.

A gate driver and a display device including the same according to an embodiment may be applied to various electronic devices. For example, a gate driver and a display device including the same according to an embodiment may include a mobile device, a video phone, a smart watch, a watch phone, a wearable device, and a foldable device. device), rollable device, bendable device, flexible device, curved device, electronic notebook, e-book, PMP (portable multimedia player), PDA (personal) digital assistant, MP3 player, mobile medical device, desktop PC, laptop PC, netbook computer, workstation, navigation, vehicle navigation, vehicle display, television, wallpaper (wall paper) It can be applied to a display device, a shiny (signage) device, a game device, a notebook computer, a monitor, a camera, a camcorder, and a home appliance.

Features, structures, effects, etc. described in various examples of the present specification are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. illustrated in at least one example of the present specification may be combined or modified with respect to other examples by those of ordinary skill in the art to which the technical spirit of the present specification pertains. Accordingly, the contents related to such combinations and modifications should be interpreted as being included in the technical scope or scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present specification. It will be clear to those who have the knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present specification.

2: set terminal 4: first power terminal
5: second clock terminal 7: control terminal
8: second power terminal 9: third power terminal
12: first clock terminal 14: output terminal
16: reset terminal 18: stabilization terminal
10, 10A: first charging unit 20, 20A: first discharging unit
30, 30A: second charging unit 40: second discharging unit
50, 50A: output 60: QB stabilization circuit
70: stabilization part STn: stage
15: carry terminal

Claims (18)

In a gate driver including a plurality of stages each driving a plurality of gate lines,
each stage
a pull-up transistor that is pulled up under the control of a first node (hereinafter referred to as a Q node) and outputs a first clock signal input through a first clock terminal among a plurality of clocks to an output terminal; and a second node (hereinafter, a QB node) an output unit including a pull-down transistor for pulling-down the output terminal under the control of a;
a controller for charging and discharging the Q node and charging and discharging the QB node opposite to the Q node; and
a QB stabilization circuit for controlling the QB node using a second clock signal of the plurality of clocks and an output of a first preceding stage of any one of the plurality of stages;
The QB stabilization circuit is
and a QB node discharge transistor configured to maintain the QB node at a gate-off voltage using an on voltage of the second clock signal and an on voltage of an output of the first preceding stage during an on period of the Q node. The method according to claim 1,
The QB stabilization circuit is
a first capacitor connected between a second clock terminal to which the second clock signal is applied and a connection node;
a second capacitor connected between a control terminal to which an output of the first preceding stage is applied and the connection node;
and the QB discharge transistor controlled by the connection node and connected between the QB node and a power supply terminal to which the gate-off voltage is supplied. 3. The method according to claim 2,
The QB stabilization circuit is
and an initialization transistor configured to initialize the connection node to the gate-off voltage in response to a stabilization signal during a vertical blank period of each frame. 3. The method according to claim 2,
During the precharging period of the Q node during the on period of the Q node,
The QB discharge transistor is turned on by the connection node to which the turn-on voltage of the second clock signal is transmitted through the first capacitor to discharge the QB node to the gate-off voltage. 5. The method according to claim 4,
In the bootstrapping period of the Q node during the on period of the Q node,
The QB discharge transistor is turned on by the connection node to which the on voltage of the output of the preceding stage is transmitted through the second capacitor to discharge the QB node to the gate-off voltage;
A gate driver in which the second clock signal, the on voltage, and the on voltage of the output of the first preceding stage are summed and applied to the connection node during a part of the precharging period The method according to claim 1,
the control unit
a first charging unit including a Q charging transistor for precharging the Q node to the set signal in response to a set signal that is one of a start signal and an output of a second preceding stage;
a second charging unit including a QB charging transistor for charging the QB node to a high potential voltage;
a first Q discharge transistor for discharging the Q node to the gate-off voltage under the control of the QB node, and a first Q discharge transistor for discharging the Q node to the gate-off voltage in response to any one of a reset signal and an output of a subsequent stage a first discharging unit including 2 Q discharging transistors; and
a first QB discharge transistor for discharging the QB node to the gate-off voltage under the control of the Q node, and a second QB discharge transistor for discharging the QB node to the second gate-off voltage in response to the set signal; A driver including a second discharge unit including a driver. 7. The method of claim 6,
the output unit
a second pull-up transistor for outputting the first clock signal to a carry terminal in response to the control of the Q node; and a second pull-down transistor for outputting the gate-off voltage to the carry terminal in response to the control of the QB node. including,
The pull-down transistor of the output unit outputs a second gate-off voltage higher than the gate-off voltage to the output terminal in response to the control of the QB node. 8. The method of claim 7,
The first discharge unit
and an output discharge transistor configured to discharge the output terminal to the second gate-off voltage in response to the reset signal and an output of a subsequent stage. 9. The method of claim 8,
The first discharge unit further includes an offset transistor for generating an offset voltage of the high potential voltage during an ON period of the Q node in response to the control of the Q node and outputting it to the offset node,
each of the Q charging transistor, the QB charging transistor, the first Q discharging transistor, and the second Q discharging transistor comprises a pair of series transistors;
The offset node is connected to an intermediate node between the pair of Q charging transistors and an intermediate node between the pair of first Q discharging transistors. 10. The method of claim 9,
Each stage is
During the vertical blank period of each frame,
a first stabilization transistor configured to reset the Q node to the gate-off voltage in response to the stabilization signal;
a second stabilization transistor configured to reset the QB node to the gate-off voltage in response to the stabilization signal;
a third stabilization transistor configured to reset the carry terminal to the gate-off voltage in response to the stabilization signal; and
Further comprising a stabilization unit comprising a fourth stabilization transistor for resetting the output terminal to the second gate-off voltage in response to the stabilization signal,
The first stabilization transistor includes a pair of first stabilization transistors connected in series, and the offset node is connected to an intermediate node between the pair of first stabilization transistors. 7. The method of claim 6,
the first clock signal is a clock signal inverted in phase from the second clock signal;
the output of the first preceding stage is the output of the n-2 th (n is an integer greater than 4) preceding stage,
The output of the second preceding stage is the output of the n-4th preceding stage,
A gate driver in which an output of the n-2 th preceding stage and an on voltage section of the second clock signal overlap during an on period of the Q node. 3. The method according to claim 2,
In an off period of the Q node, the QB node maintains an on voltage when the first clock signal is an on voltage, and the QB node maintains an off voltage when the second clock signal is an on voltage. In a gate driver including a plurality of stages each driving a plurality of gate lines,
each stage
a pull-up transistor that is pulled up under the control of a first node (hereinafter referred to as a Q node) and outputs a first clock signal input through a first clock terminal among a plurality of clocks to an output terminal; and a second node (hereinafter, a QB node) an output unit including a pull-down transistor for pulling-down the output terminal under the control of a;
a controller for charging and discharging the Q node and charging and discharging the QB node opposite to the Q node; and
a QB stabilization circuit for controlling the QB node using a second clock signal of the plurality of clocks and an output of a first preceding stage of any one of the plurality of stages;
The QB stabilization circuit is
a first capacitor connected between a second clock terminal to which the second clock signal is applied and a connection node;
a second capacitor connected between a control terminal to which an output of the first preceding stage is applied and the connection node;
the QB discharge transistor controlled by the connection node and connected between the QB node and a power supply terminal to which the gate-off voltage is supplied; and
and an initialization transistor configured to initialize the connection node to the gate-off voltage in response to a stabilization signal during a vertical blank period of each frame. 14. The method of claim 13,
the control unit
a first charging unit including a Q charging transistor for precharging the Q node to the set signal in response to a set signal that is one of a start signal and an output of a second preceding stage;
a second charging unit including a QB charging transistor for charging the QB node to a high potential voltage;
a first Q discharge transistor for discharging the Q node to the gate-off voltage under the control of the QB node, and a first Q discharge transistor for discharging the Q node to the gate-off voltage in response to any one of a reset signal and an output of a subsequent stage a first discharging unit including 2 Q discharging transistors; and
a first QB discharge transistor for discharging the QB node to the gate-off voltage under the control of the Q node, and a second QB discharge transistor for discharging the QB node to the second gate-off voltage in response to the set signal; A driver including a second discharge unit including a driver. 15. The method of claim 14,
the output unit
a second pull-up transistor for outputting the first clock signal to a carry terminal in response to the control of the Q node; and a second pull-down transistor for outputting the gate-off voltage to the carry terminal in response to the control of the QB node. including,
The pull-down transistor of the output unit outputs a second gate-off voltage higher than the gate-off voltage to the output terminal in response to the control of the QB node. 15. The method of claim 14,
the first clock signal is a clock signal inverted in phase from the second clock signal;
the output of the first preceding stage is the output of the n-2 th (n is an integer greater than 4) preceding stage,
The output of the second preceding stage is the output of the n-4th preceding stage,
A gate driver in which an output of the n-2 th preceding stage and an on voltage section of the second clock signal overlap during an on period of the Q node. 14. The method of claim 13,
In an off period of the Q node, the QB node maintains an on voltage when the first clock signal is an on voltage, and the QB node maintains an off voltage when the second clock signal is an on voltage. panel to display the video,
A display device in which the gate driver according to any one of claims 1 to 17 is built in the panel.

Images