KR20170079376A - Thin film transistor, display device having built-in gate driver using the same - Google Patents

Abstract

The present invention relates to a display device including a thin film transistor capable of reducing unnecessary parasitic capacitors and a built-in gate driver capable of reducing a load of a clock line using the same, wherein the thin film transistor according to an embodiment includes an active layer, A gate electrode overlapping the active layer with a gate insulating layer therebetween, and a first electrode and a second electrode connected to the active layer. The active layer includes first and second conductively connected regions individually connected to the first and second electrodes, and a channel region between the first and second conductivated regions. The thin film transistor includes an active layer removing portion in which a corresponding conductive region adjacent to at least one of the first electrode and the second electrode is partially removed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor (TFT) and a display device having a built-

The present invention relates to a display device including a thin film transistor capable of reducing an unnecessary parasitic capacitor and an embedded gate driver capable of reducing a load of a clock line using the thin film transistor.

The display device includes a liquid crystal display (LCD), an organic light emitting diode (OLED), an electrophoretic display (EPD), and an electro wetting display.

The display device includes a display panel in which each pixel displays an image through a pixel array independently driven by a thin film transistor (TFT), a gate driver for driving the display panel, and a data driver. Recently, the gate driver is formed with a TFT array of a pixel array and mainly uses a gate-in-panel (GIP) method embedded in a non-display region of a display panel.

The gate driver includes shift registers, and the shift registers are connected to each other to drive gate lines of the display panel, and each stage is composed of a plurality of TFTs. The shift register has clock lines for supplying clocks and power supply lines for supplying power supply voltages. The clock lines and the power supply lines are arranged side by side outside the stages.

The stages of the shift register have a problem that the output delay increases from the upper end portion to the lower end portion. The output delay of each stage is affected by the delay of the clock signal output as a scan pulse through the output TFT of each stage, and the clock delay is increased by the resistor and the parasitic capacitor acting as the load of the clock line. The load of the clock line is relatively influenced by the parasitic capacitor between the clock line and the output TFT having a relatively large area.

The built-in gate driver uses parasitic capacitors rather than TFTs having a bottom gate structure in which the source and drain electrodes overlap with the gate electrodes by using a poly TFT or an oxide TFT having a coplanar structure in which the source and drain electrodes do not overlap with the gate electrode The parasitic capacitors of the output TFT still have a great influence on the load of the clock line as the area of the output TFT is relatively large.

Accordingly, there is a need to reduce the capacitance (parasitic capacitance) of the parasitic capacitor which increases the load of the clock line in the output TFT in order to solve the output delay problem of the gate driver due to the conventional clock delay.

The present invention provides a display device including a thin film transistor capable of reducing an unnecessary parasitic capacitor and an embedded gate driver capable of reducing a load of a clock line using the same.

A thin film transistor according to an embodiment of the present invention includes an active layer, a gate electrode overlapping the active layer with a gate insulating layer therebetween, and a first electrode and a second electrode connected to the active layer. The active layer has first and second conductively connected regions that are individually connected to the first and second electrodes. The thin film transistor includes an active layer removing portion in which a corresponding conductive region adjacent to at least one of the first electrode and the second electrode is partially removed.

The first electrode includes a first main line and a plurality of first finger portions branched from the first main line. The second electrode includes a second main line spaced apart from the first main line and a plurality of second finger portions branched from the second main line and alternately arranged with the plurality of first finger fingers. The gate electrode includes a plurality of first gate electrode portions positioned in respective regions between the first and second fingers, and a plurality of second gate electrode portions connecting the plurality of first gate electrode portions to each other. The active layer has a channel region overlapping each of the first gate electrode portions in each region between the first and second fingers, and a first conductorized region sandwiched between the channel regions and the second conductorized region And has an alternately arranged structure. The active layer removing portion is located on both sides of at least one of the first and second finger portions.

A display device according to an embodiment of the present invention includes a gate driver that is embedded in a non-display area of a display panel and includes a plurality of stages that supply scan outputs to a plurality of gate lines of the display panel. Each of the plurality of stages uses the thin film transistor described above to supply the clock signal supplied from the clock line to the scan output in response to the control of the control node.

The active layer removal portion may be located only in the conductorized region connected to the clock line of the first and second conductorized regions.

A thin film transistor of a coplanar structure according to an embodiment of the present invention includes an active layer removing portion formed in an active layer conducting region around at least one electrode connected to a signal line of a source electrode and a drain electrode, It is possible to reduce the load of the signal line connected to the thin film transistor by reducing the capacitance of the unnecessary parasitic capacitors acting thereon.

The built-in gate driver of the display device according to the embodiment of the present invention can reduce the delay of the clock signal used for the scan output by reducing the load of the clock line by using the thin film transistor described above, Can be improved.

1 is a plan view of a thin film transistor according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the thin film transistor shown in FIG. 1 taken along line A-A 'and line B-B'.
3 is a plan view of a thin film transistor according to another embodiment of the present invention.
4 is a diagram schematically illustrating a display device including a built-in gate driver according to an embodiment of the present invention.
5 is an equivalent circuit diagram illustrating an LCD pixel structure applied to the pixel shown in FIG.
6 is an equivalent circuit diagram illustrating an OLED pixel structure applied to the pixel shown in FIG.
7 is a circuit diagram showing an embedded gate driver according to an embodiment of the present invention as an output switching device.
8 is a plan view showing an output switching device as an embedded gate driver according to an embodiment of the present invention.
9 is a plan view showing an output switching device as an embedded gate driver according to an embodiment of the present invention.
10 is a cross-sectional view illustrating a cross-sectional structure taken along the line C-C 'of the output switching device shown in FIG.

2 is a cross-sectional view taken along line A-A 'and line B-B' of FIG. 2; FIG. 3 is a cross- Fig.

1 to 3, a thin film transistor according to an embodiment has a coplanar structure. The thin film transistor includes a light shielding layer LS on a substrate SUB under the buffer layer BUF, an active layer ACT stacked on the buffer layer BUF, a gate insulating layer GI, a gate electrode GE, An interlayer insulating layer ILD covering the laminated structure of the active layer ACT, the gate insulating layer GI and the gate electrode GE and the contact holes H1 and H2 penetrating the interlayer insulating layer ILD A source electrode SE and a drain electrode DE respectively connected to the source region SA and the drain region DA of the active layer ACT via the source electrode SE and the drain electrode DE on the interlayer insulating layer ILD, And a passivation layer (PAS) covering the electrode DE.

The light-shielding layer LS on the substrate SUB is formed of a metal material having a light-shielding function so as to block external light that changes the characteristics of the active layer ACT from entering the active layer ACT. The light-shielding layer LS is made of any one of metals such as molybdenum (Mo), aluminum (Al), chromium (Cr), tungsten (W), titanium (Ti), nickel (Ni), neodymium (Nd) and copper Or a single layer or a multi-layer structure composed of an alloy thereof.

The buffer layer BUF covering the light-shielding layer LS on the substrate SUB prevents contaminants such as moisture and gas from flowing from the outside into the active layer ACT. The buffer layer BUF is formed as a structure in which a single insulating layer or a plurality of insulating layers are stacked. The buffer layer BUF is formed of an oxide insulating material such as silicon oxide (SiOx), aluminum oxide (AlOx), or the like in order to prevent the characteristic change due to the hydrogen inflow from the nitride based insulating material when the active layer ACT is the oxide active layer .

The active layer ACT stacked on the buffer layer BUF has a channel region CH and a low resistance source region SA and a drain region DA which are conductively processed to reduce the offset resistance. The active layer ACT may be formed of a polysilicon. The active layer ACT may be formed of an oxide semiconductor containing at least one of In, Ga, Zn, Al, Sn, Zr, Hf, Cd, Ni and Cu. When the active layer ACT is a poly layer, the source region SA and the drain region DA are made conductive by dopant ion doping. When the active layer ACT is an oxide active layer, the source region SA and the drain region DA are made conductive as the active layer ACT is exposed by plasma, ultraviolet (UV), or etchant, .

A gate insulating layer GI and a gate electrode GE overlapping the channel region CH are formed in a laminated structure on the active layer ACT. The gate insulating layer GI may be formed of a single layer or a multilayer structure of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx) and the like. The gate insulating layer GI may be formed of an oxide-based insulating material to prevent a change in characteristics of the active layer ACT using an oxide semiconductor. The gate electrode GE may be formed of any one of metals such as molybdenum (Mo), aluminum (Al), chrome (Cr), tungsten (W), titanium (Ti), nickel (Ni), neodymium (Nd), and copper Or a single layer or a multi-layer structure composed of an alloy thereof.

The interlayer insulating layer ILD covering the active layer ACT, the gate insulating layer GI and the gate electrode GE is formed on the buffer layer BUF and the contact holes H1, H2 are formed. The ILD may be formed of a single layer or a multilayer structure or an organic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or the like.

A source electrode SE and a drain electrode DE are formed on the interlayer insulating layer ILD. The source electrode SE is connected to the source region SA of the active layer ACT via the contact hole H1 and the drain electrode DE is connected to the drain region of the active layer ACT through the contact hole H2 DA. The source electrode SE and the drain electrode DE may be formed of at least one selected from the group consisting of Mo, Al, Cr, W, Ti, Ni, ), And the like, or an alloy thereof.

A passivation layer PAS is formed on the interlayer insulating layer ILD to cover the source electrode SE and the drain electrode DE. The ILD may be formed of a single layer or a multilayer structure of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), aluminum oxide (AlOx), or the like.

Particularly, the thin film transistor of the present invention includes an active layer removing portion (hereinafter referred to as " active layer removing portion ") partially removing the conducting regions SA and DA of the active layer ACT at the periphery of at least one of the source electrode SE and the drain electrode DE RH) to reduce the capacitance of the parasitic capacitors.

The thin film transistor of the coplanar structure has a structure in which the source electrode SE and the drain electrode DE and the gate electrode GE do not overlap each other even if the source electrode SE and the drain electrode DE do not overlap with the gate electrode GE, A fringe electric field between the fringing electric field and the side electric field between the gate electrode and the conductive area SA of the active layer ACT and the gate electrode GE is formed to form a gate-source parasitic capacitor Cgs, Human parasitic capacitor (Cgd). At least one of these parasitic capacitors Cgs and Cgd increases the load on the signal line connected to the thin film transistor and causes signal delay. Therefore, the thin film transistor of the present invention has the conductive regions SA, DA (Cgs, Cgd) by reducing the capacity of the parasitic capacitors (Cgs, Cgd).

When both the gate-source parasitic capacitor Cgs and the gate-drain parasitic capacitor Cgd are unnecessary, the active layer removing RH is located at both sides of the source electrode SE as shown in FIG. In the source region SA of the active layer ACT and the drain region DA of the active layer ACT located on both sides of the drain electrode DE.

Alternatively, when the gate-drain parasitic capacitor Cgd is unnecessary, the active layer removing region RH may be formed in the drain region DE of the active layer ACT located on both sides of the drain electrode DE, (DA).

Of course, when the gate-source parasitic capacitor Cgs is unnecessary, the active layer removing RH is formed only in the source region SA of the active layer ACT located on both sides of the source electrode SE in Fig. .

Referring to FIGS. 1 and 2, since the active layer removing region RH is located as close as possible to both sides of the source electrode SE or the drain electrode DE at the maximum distance from the channel region CH, And does not affect the width W and the length L of the channel region CH for determining the characteristics. The active layer removing portion RH is formed from the first and second edge portions E1 and E2 of the active layer ACT parallel to the length L of the channel region CH to the source electrode SE or the drain electrode DE As shown in FIG. The active layer removing RH is located apart from the contact holes H1 and H2 to prevent the contact resistance between the source electrode SE and the drain electrode DE and the active layer ACT from increasing.

As described above, the thin film transistor of the coplanar structure according to the embodiment of the present invention has the conductorized regions SA, DA (DA) of the active layer ACT at the periphery of at least one of the source electrode SE and the drain electrode DE ) Is partially removed, the capacitance of the unnecessary parasitic capacitor can be reduced.

The thin film transistor according to the present invention can be applied to a built-in gate driver of a display device in which a capacitance of a parasitic capacitor is required to reduce a clock load.

4 is an equivalent circuit diagram illustrating an LCD pixel structure applied to each pixel of FIG. 4, and FIG. 6 is a cross-sectional view of a display device having an embedded gate driver according to an embodiment of the present invention. Is an equivalent circuit diagram illustrating an OLED pixel structure applied to each pixel.

4, the display apparatus includes a display panel 400, a gate driver 300, a data driver 200, and a timing controller 100, which are panel driving units.

The display panel 400 displays an image through a matrix-shaped pixel array. Each pixel P of the pixel array is independently driven by the TFT. As the TFT, an amorphous silicon (a-Si) TFT, a poly-Si TFT, an oxide TFT, an organic TFT or the like can be used. As the display panel 400, a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an electrophoretic display (EPD), or the like can be used.

For example, when the display panel 400 is an LCD panel, as shown in FIG. 5, each pixel P includes a TFT connected to the gate line GL and the data line DL, And a liquid crystal capacitor Clc and a storage capacitor Cst connected in parallel. The liquid crystal capacitor Clc charges the difference voltage between the data signal supplied to the pixel electrode through the TFT and the common voltage Vcom supplied to the common electrode, and drives the liquid crystal according to the charged voltage to control the light transmission amount. The storage capacitor Cst stably maintains the voltage charged in the liquid crystal capacitor Clc.

6, each pixel P includes an OLED element connected between a high potential power supply (EVDD) line and a low potential power supply (EVSS) line, And a pixel circuit including the first and second switching TFTs ST1 and ST2 and the driving TFT DT and the storage capacitor Cst in order to independently drive the OLED elements. Structure.

The OLED element includes an anode connected to the driving TFT DT, a cathode connected to the low potential voltage EVSS, and a light emitting layer between the anode and the cathode to emit light proportional to the amount of current supplied from the driving TFT DT Occurs.

The first switching TFT ST1 is driven by the gate signal of one gate line GLa to supply the data voltage from the corresponding data line DL to the gate node of the driving TFT DT and the second switching TFT ST2 Is driven by the gate signal of the other gate line GLb to supply a reference voltage from the reference line RL to the source node of the driver TFT DT. The second switching TFT ST2 is further used as a path for outputting the current from the driving TFT DT to the reference line R in the sensing mode.

The storage capacitor Cst connected between the gate electrode and the source electrode of the driving TFT DT receives the data voltage supplied to the gate electrode of the driving TFT DT through the first switching TFT ST1 and the data voltage supplied to the second switching TFT ST2 to the source electrode of the driving TFT DT and supplies the charged voltage to the driving TFTs (ST1, ST2) during the period in which the first and second switching TFTs ST1, ST2 are turned off DT).

The driving TFT DT controls the current supplied from the high potential power supply EVDD according to the driving voltage supplied from the storage capacitor Cst to supply a current proportional to the driving voltage to the OLED element to emit the OLED element.

The timing controller 100 performs various image processes on the image data supplied from the outside, and supplies the image data to the data driver 200. The timing controller 100 generates data control signals for controlling the operation timing of the data driver 200 using a plurality of timing control signals supplied from the outside and supplies the data control signals to the data driver 200, Generates gate control signals for controlling the operation timing, and supplies the gate control signals to the gate driver 300.

The data driver 200 converts image data from the timing controller 100 into analog data signals using gamma voltages and supplies the analog data signals to the data lines of the display panel 400, respectively.

The gate driver 300 is controlled according to gate control signals from the timing controller 100 to drive a plurality of gate lines of the display panel 400, respectively. The gate driver 300 supplies a gate-on voltage to the respective gate lines in a corresponding scan period and a gate-off voltage in the remaining periods. The gate driver 300 is formed on the thin film transistor array substrate together with the thin film transistors constituting each pixel P of the pixel array in the non-display region of the display panel 400, and is embedded in the display panel 400. The switching elements constituting the gate driver 300 incorporated in the display panel 400 may use a poly-TFT or an oxide TFT having a coplanar structure in which source and drain electrodes do not overlap with gate electrodes in order to reduce parasitic capacitors.

Particularly, the output switching element for outputting a clock as a scan output in the gate driver 300 includes an active layer eliminating part that partially removes the conducting region of the active layer around the drain electrode connected to the clock line, The capacitance of the gate-drain parasitic capacitor can be reduced. Accordingly, by reducing the load of the clock line, it is possible to reduce the delay of the clock signal used for the scan output, thereby improving the output characteristic of the gate drive circuit.

Referring to FIG. 7, the gate driver 300 includes a plurality of stages ST for individually driving the gate lines GL. In each stage ST, a plurality of clocks At least one of the clock signals CLKs is supplied.

Each stage ST includes an output switching element Tpu for supplying one of the clocks supplied to its output section to the corresponding gate line in response to the high logic of the Q node controlled by the node control section CON, Respectively. Each of the clock lines is connected to a plurality of stages using the corresponding clock.

The output switching element Tpu has a relatively large channel width for stably supplying the scan output. Even though the output switching element Tpu has a coplanar structure, the gate-drain parasitic capacitor Cgd between the drain electrode connected to the clock line and the gate electrode connected to the Q node, the source electrode connected to the output node, And a gate-source parasitic capacitor (Cgs) between the gate electrodes.

The gate-source parasitic capacitor (Cgs) increases the voltage of the Q node according to the clock supplied to the output node when the Q node is in the floating state, thereby stabilizing the turn-on of the output switching element (Tpu) However, the gate-drain parasitic capacitor Cgd is unnecessary to delay the clock by increasing the load of the clock line, and thus a reduction is necessary.

Therefore, the output switching element Tpu can reduce the gate-drain parasitic capacitor Cgd by providing the active layer removing RH at the periphery of the drain electrode DE as described above in Fig. On the other hand, in order to balance the characteristics of the source electrode SE and the drain electrode DE, the output switching element Tpu is formed on the periphery of the source electrode SE and the drain electrode DE, And a removing unit RH.

FIGS. 8 and 9 are plan views illustrating an output switching device of a gate driver according to an embodiment of the present invention, and FIG. 10 is a cross-sectional view taken along a line C-C ' Sectional view.

8 to 10, the source electrode SE includes a source main line SEm and a plurality of source fingers SEf branched in parallel from the source main line SEm.

The drain electrode DE includes a drain main line DEm spaced apart from and facing the source main line SEm and a plurality of source main lines DEm branched from the drain main line DEm and alternately arranged with the plurality of source fingers SEf (Def).

The gate electrode GE includes a plurality of first gate electrode portions GE1 positioned between each of the plurality of source finger portions SEf and a plurality of drain finger portions Def, And a plurality of second gate electrode units GE2 connecting the gate electrodes GE1 to each other. The plurality of second gate electrode units GE2 are formed between the region between the end of the drain fringe DEf and the source main line SEm and the region between the end of the source fence SEf and the drain main line DEm Are alternately arranged.

The active layer ACT is disposed in parallel with the main lines SEm and DEm between the source main line SEm and the drain main line DEm and has source fingers SEf and drain fingers DEf, And the first gate electrode portions GE1 are overlapped with each other. The active layer ACT includes a plurality of channel regions CH overlapping with the first gate electrode portions GE1 in regions between each of the plurality of source finger portions SEf and the plurality of drain finger portions Def. 10) and a source region SA (FIG. 10) and a drain region DA (FIG. 10) that are made conductive with the channel region CH (FIG. 10) sandwiched therebetween. The plurality of channel regions CH are separated from each other.

The active layer ACT has a region between the end portion of the drain fingering DEf and the source main line SEm where a plurality of second gate electrode portions GE2 are located for reducing the off current, SEf and the drain main line DEm. The first edge portion E1 which is parallel to the length L of the channel region in the active layer ACT is located inside the end portion of the source finger reflex SEf and is parallel to the length L direction of the channel region, The second edge portion E2 side by side with the first edge portion E2 is located inside the end portion of the drain fingering DEf. The distance between the first and second edge portions E1 and E2 of the active layer ACT determines the width W of the channel region.

Since the drain main line DEm is connected to the clock line, in order to reduce the gate-drain parasitic capacitor Cgd acting as the load of the clock line, the active layer removing RH May be formed only in the drain region DA of the active layer ACT located on both sides of the drain fingering DEf.

On the other hand, in order to symmetrically maintain the electric characteristics of the source electrode SE and the drain electrode DE, the active layer removing RH is formed on both sides of the drain fingering DEf and the source Can be formed on both sides of the finger refusal SEf.

Since the active layer removing RH is located as close as possible to the both side portions of the drain fingering DEf and / or both side portions of the source fingering SEf so as to be as far as possible from the channel region CH, And does not affect the width W and the length L of the channel region CH to be determined. The active layer removing portion RH is provided between the first and second edge portions E1 and E2 of the active layer ACT parallel to the length L direction of the channel region CH, / RTI > may be formed in the shape of a recess concave along both sides of the source finger (SEf). The active layer removing RH is located apart from the contact holes H1 and H2 to prevent the contact resistance between the source electrode SE and the drain electrode DE and the active layer ACT from increasing.

A thin film transistor of a coplanar structure according to an embodiment of the present invention includes an active layer removing portion formed in an active layer conducting region around at least one electrode connected to a signal line of a source electrode and a drain electrode, It is possible to reduce the load of the signal line connected to the thin film transistor by reducing the capacitance of the unnecessary parasitic capacitors acting thereon.

The built-in gate driver of the display device according to the embodiment of the present invention can reduce the delay of the clock signal used for the scan output by reducing the load of the clock line by using the thin film transistor described above, Can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUB: Substrate LS: Shading layer
BUF: buffer layer ACT: active layer
CH: channel region SA: source region
DA: drain region GI: gate insulating layer
GE: gate electrode SE: source electrode
DE: drain electrode PAS: passivation layer
ILD: Interlayer insulating layer H1, H2: Contact hole
E1, E2: active layer edge portion RH: active layer removal
DEm: drain main line DEf: drain drain
SEm: Source Mainline SEf: Source Finger
GE1: first gate electrode portion GE2: second gate electrode portion

Claims (7)

An active layer,
A gate electrode overlapping the active layer with a gate insulating layer therebetween,
A first electrode and a second electrode connected to the active layer,
Wherein the active layer comprises first and second conductively connected regions independently of the first and second electrodes and a channel region between the first and second conductivated regions,
And an active layer removing portion in which a corresponding conductive region adjacent to at least one of the first electrode and the second electrode is partially removed. The method according to claim 1,
The first and second electrodes are located on the interlayer insulating layer covering the gate electrode and connected to the first and second conductive regions through respective contact holes passing through the interlayer insulating layer,
The first and second electrodes overlapping the gate electrode,
Wherein the active layer removing portion overlaps the gate electrode and the contact hole. The method of claim 2,
Wherein the active layer removing portion is located on both sides of the corresponding electrode of the first and second electrodes and has a groove shape recessed from the edge portion of the active layer in parallel with the longitudinal direction of the channel region. The method of claim 3,
Wherein the first electrode includes a first main line and a plurality of first finger portions branched from the first main line,
The second electrode includes a second main line spaced apart from and facing the first main line and a plurality of second finger portions branched from the second main line and alternately arranged with the plurality of first finger fingers ,
The gate electrode includes a plurality of first gate electrode portions positioned in respective regions between the first and second fingers and a plurality of second gate electrode portions connecting the plurality of first gate electrode portions to each other and,
Wherein the active layer has a channel region overlapping each of the first gate electrode portions in each region between the first fingers and the second fingers, the first conducting region having the channel region therebetween, The second conductive regions are alternately arranged,
Wherein the active layer removing portion is located on both sides of at least one of the first and second fingers. The method of claim 4,
Wherein the active layer has a first edge portion that is parallel to a front end portion of the plurality of second finger portions facing the first main line and a second edge portion that is parallel to the front end portion of the plurality of first finger portions facing the second main line And a second edge portion,
Wherein the active layer removing portion has a groove shape recessed along both side portions of the finger portion from at least one edge portion of the first and second edge portions. A display panel,
And a plurality of stages which are embedded in a non-display area of the display panel and supply scan outputs to a plurality of gate lines of the display panel,
Each of the plurality of stages
A display device comprising an output switching element for supplying a clock signal supplied from a clock line to the scan output in response to a control of a control node, using the thin film transistor according to any one of claims 1 to 5. The method of claim 6,
Wherein the active layer removing portion is located only in a conductorized region connected to the clock line among the first and second conductorized regions.

Images