WO2018190396A1 - Active matrix substrate - Google Patents

Abstract

This active matrix substrate is provided with at least one TFT 10A, and a peripheral circuit containing the TFT 10A. The TFT 10A comprises a gate electrode 3, a gate insulating layer 5, an oxide semiconductor layer 7 arranged on the gate insulating layer, and a source electrode 8 and a drain electrode 9 arranged on the oxide semiconductor layer. Seen from the substrate normal direction, the gate electrode 3 has a first edge 3e1 and a second edge 3e2 opposite each other, and the first edge and the second edge extend across the oxide semiconductor layer 7 in the channel width direction DW of the TFT 10A. Seen from the substrate normal direction, the source electrode 8 extends across the oxide semiconductor layer 7 in the channel width direction DW so as to overlap the first edge 3e1, and the drain electrode extends across the oxide semiconductor layer 7 in the channel width direction DW so as to overlap the second edge 3e2.

Description

Active matrix substrate

The present invention relates to an active matrix substrate.

An active matrix substrate used for a liquid crystal display device or the like has a display area having a plurality of pixels and an area other than the display area (non-display area or frame area). The display region includes a switching element such as a thin film transistor (hereinafter, “TFT”) for each pixel. Conventionally, as such a switching element, a TFT having an amorphous silicon film as an active layer (hereinafter referred to as “amorphous silicon TFT”) or a TFT having a polycrystalline silicon film as an active layer (hereinafter referred to as “polycrystalline silicon TFT”). Is widely used.

It has been proposed to use an oxide semiconductor instead of amorphous silicon or polycrystalline silicon as a material for the active layer of TFT. Such a TFT is referred to as an “oxide semiconductor TFT”. An oxide semiconductor has higher mobility than amorphous silicon. For this reason, the oxide semiconductor TFT can operate at a higher speed than the amorphous silicon TFT.

∙ Peripheral circuits such as drive circuits may be formed monolithically (integrated) in the non-display area of the active matrix substrate. By forming the drive circuit monolithically, the non-display area can be narrowed and the cost can be reduced by simplifying the mounting process. For example, in the non-display area, the gate driver circuit may be formed monolithically and the source driver circuit may be mounted by a COG (Chip on Glass) method.

In devices with a high demand for narrow frames such as smartphones, it has been proposed to form a demultiplexer circuit such as a source switching (SSD) circuit monolithically in addition to a gate driver (for example, Patent Document 1). And 2). The SSD circuit is a circuit that distributes video data from one video signal line from each terminal of the source driver to a plurality of source lines. By mounting the SSD circuit, the region (terminal portion / wiring forming region) in which the terminal portion and the wiring are arranged in the non-display region can be further narrowed. In addition, since the number of outputs from the source driver is reduced and the circuit scale can be reduced, the cost of the driver IC can be reduced.

Peripheral circuits such as drive circuits and SSD circuits include TFTs. In this specification, a TFT disposed as a switching element in each pixel in the display region is referred to as a “pixel TFT”, and a TFT constituting a peripheral circuit is referred to as a “circuit TFT”. Further, among the circuit TFTs, TFTs used as switching elements in the demultiplexer circuit (SSD circuit) are referred to as “DMX circuit TFTs”.

International Publication No. 2011/118079 JP 2010-102266 A

In an active matrix substrate using an oxide semiconductor TFT as a pixel TFT, the DMX circuit TFT is preferably an oxide semiconductor TFT using the same oxide semiconductor film as the pixel TFT from the viewpoint of the manufacturing process.

However, it is difficult to form a demultiplexer circuit using an oxide semiconductor TFT, and conventionally, a polycrystalline silicon TFT has been used as a TFT for a DMX circuit. The reason for this is as follows.

Since the oxide semiconductor has a mobility that is about an order of magnitude smaller than that of polycrystalline silicon, the oxide semiconductor TFT has a smaller current driving force than the polycrystalline silicon TFT. For this reason, when forming a TFT for a DMX circuit using an oxide semiconductor, it is necessary to increase the size of the TFT (increase the channel width) or increase the driving voltage as compared with the case of using polycrystalline silicon. There is. When the size of the TFT is increased, the gate capacitance load increases and the driving power of the demultiplexer circuit increases. On the other hand, even if the driving voltage of the TFT is increased, the driving power of the demultiplexer circuit increases.

In addition to the DMX circuit TFT, when a peripheral circuit including a TFT through which a large current flows is formed monolithically, there is the same problem as described above.

Embodiments of the present invention have been made in view of the above circumstances, and an object of the present invention is to provide an active matrix substrate capable of reducing driving power of peripheral circuits including oxide semiconductor TFTs.

An active matrix substrate according to an embodiment of the present invention includes a display region including a plurality of pixels, a non-display region provided around the display region, a substrate, supported by the substrate, and An active matrix substrate comprising at least one TFT disposed in a non-display area and a peripheral circuit including the at least one TFT, wherein the at least one TFT includes a gate electrode and a gate covering the gate electrode An insulating layer; an oxide semiconductor layer disposed on the gate insulating layer so as to at least partially overlap the gate electrode with the gate insulating layer interposed therebetween; and the oxide semiconductor on the oxide semiconductor layer A source electrode disposed in contact with a part of the layer; and a drain disposed on the oxide semiconductor layer so as to be in contact with another part of the oxide semiconductor layer. The gate electrode has a first edge and a second edge facing each other when viewed from the normal direction of the substrate, and the first edge and the second edge Extends across the oxide semiconductor layer in the channel width direction of the at least one TFT, and when viewed from the normal direction of the substrate, the source electrode is connected to the first edge of the gate electrode. The oxide semiconductor layer extends across the oxide semiconductor layer in the channel width direction so as to overlap, and the drain electrode overlaps the second edge portion of the gate electrode in the channel width direction. Extending across.

In one embodiment, the source edge facing the drain electrode in the source electrode and / or the drain edge facing the source electrode in the drain electrode when viewed from the normal direction of the substrate, The region overlapping with the oxide semiconductor layer has at least one projection protruding in the channel length direction of the at least one TFT, and a recess or notch adjacent to the at least one projection in the channel width direction. The length of the at least one convex portion in the channel length direction is less than 1/3 of the width of the gate electrode in the channel length direction.

In one embodiment, the total width in the channel width direction of the at least one protrusion disposed at the source edge or the drain edge is 70% or more and 90% of the channel width W of the at least one TFT. It is as follows.

In one embodiment, each of the source edge and the drain edge includes the at least one protrusion and the recess or the notch, and the at least one protrusion of the source edge includes: The at least one convex portion of the drain edge is opposed to the channel length direction, and the concave portion or the notch portion of the source edge portion corresponds to the concave portion or the notch portion of the drain edge portion and the channel length direction. Opposite to.

In one embodiment, each of the source edge and the drain edge includes the at least one protrusion and the recess or the notch, and the at least one protrusion of the source edge includes: The recess or the notch of the drain edge is opposed to the channel length direction, and the recess or the notch of the source edge has at least one protrusion of the drain edge and the channel length direction. Opposite to.

In one embodiment, the display region further includes a plurality of source bus lines extending in the channel width direction and a plurality of gate bus lines extending in the channel length direction of the at least one TFT, and the peripheral circuit includes a plurality of peripheral buses. Each of the plurality of unit circuits from one video signal line out of the plurality of video signal lines to n lines out of the plurality of source bus lines (n is 2). The video signal is distributed to the source bus lines of the above integer), each of the plurality of unit circuits includes at least n DMX circuit TFTs, and the at least one TFT includes the at least n DMX circuits. TFT for use.

In one embodiment, the demultiplexer circuit further includes a plurality of control signal trunk lines, and each of the plurality of unit circuits includes n branch wirings connected to the one video signal line, and the n number of branch lines. A source bus line; and n control signal branch lines, each of the plurality of control signal branch lines being electrically connected to one of the plurality of control signal trunk lines, In each of the circuits, the drain electrode of each DMX circuit TFT is a part of one of the n source bus lines, the source electrode is a part of one of the n branch wirings, and the gate electrode is each of the plurality of unit circuits, each of the n branch wirings, the n control signal branch lines, and the n source bus lines is a part of the n control signal branch lines, And it extends to the serial channel width direction.

In one embodiment, the demultiplexer circuit includes a plurality of sub-circuits, and each of the sub-circuits includes at least a first unit circuit and a second unit circuit of the plurality of unit circuits, and each of the sub-circuits , The n control signal branch lines in the first unit circuit and the second unit circuit are common.

In one embodiment, in each of the sub-circuits, the first unit circuit formation region in which the at least n DMX circuit TFTs of the first unit circuit are formed is the at least n DMX of the second unit circuit. It is located between the second unit circuit formation region where the circuit TFT is formed and the display region.

In one embodiment, in each of the sub-circuits, one of the at least n DMX circuit TFTs in the first unit circuit and one of the at least n DMX circuit TFTs in the second unit circuit are: It is connected to the same control signal branch line, and is arranged on the same control signal branch line with an interval.

In one embodiment, the plurality of source bus lines are arranged in the channel length direction from one end, and each of the sub-circuits is Nth (N is a natural number), (N + 1) th from the one end. , (N + 2) th and (N + 3) th arrayed first source bus line, second source bus line, third source bus line and fourth source bus line, respectively. 3 source bus lines are electrically connected to one of the plurality of video signal lines through the first unit circuit, and the second source bus line and the fourth source bus line are connected to the second unit circuit. It is electrically connected to another one of the video signal lines through a circuit.

In one embodiment, in each of the sub-circuits, when viewed from the normal direction of the substrate, one of the at least n DMX circuit TFTs of the first unit circuit includes the second source bus line and the Arranged between the fourth source bus lines.

In one embodiment, the at least n DMX circuit TFTs include a plurality of TFTs arranged in the channel width direction and connected in parallel to each other.

In one embodiment, the plurality of control signal trunks include n first control signal trunks and n second control signal trunks, and each of the n first control signal trunks includes the The same control signal as one of the n second control signal trunk lines is supplied, and the n control signal branch lines in some unit circuits of the plurality of unit circuits are the n first control signal trunk lines. The n control signal branch lines in other part of the unit circuits are electrically connected to the n second control signal trunk lines.

In one embodiment, the peripheral circuit includes a gate driver, the gate driver includes a plurality of shift registers, and the at least one TFT includes an output transistor in each of the plurality of shift registers.

An active matrix substrate according to another embodiment of the present invention includes a display area including a plurality of pixels and a non-display area provided around the display area, and is disposed in the non-display area. And a demultiplexer circuit supported by the substrate, a plurality of source bus lines extending in a first direction in the display region, and a plurality of gate bus lines extending in a second direction intersecting the first direction. The demultiplexer circuit includes a plurality of unit circuits and a plurality of control signal trunk lines, and each of the plurality of unit circuits is connected to the plurality of sources from one video signal line among the plurality of video signal lines. A video signal is distributed to n source bus lines (n is an integer of 2 or more) of bus lines, and each of the plurality of unit circuits is for at least n DMX circuits. FT, n branch wirings connected to the one video signal line, the n source bus lines, and n control signal branch lines, and the n control signal branch lines Each is electrically connected to one of the plurality of control signal trunk lines, and in each of the plurality of unit circuits, the n branch wirings, the n control signal branch lines, and the n control signal main lines are connected. Each source bus line extends in the first direction, and each DMX circuit TFT includes a gate electrode, an oxide semiconductor layer disposed on the gate electrode via a gate insulating layer, A source electrode is disposed on the oxide semiconductor layer so as to be in contact with a part of the oxide semiconductor layer, and is disposed on the oxide semiconductor layer so as to be in contact with another part of the oxide semiconductor layer. Drain electrode, and the drain electrode Is a part of one of the n source bus lines, the source electrode is a part of one of the n branch lines, and the gate electrode is one of the n control signal branch lines. The gate electrode has a first edge and a second edge facing each other when viewed from the normal direction of the substrate, and the first edge and the second edge are The physical semiconductor layer extends across the first direction, and when viewed from the normal direction of the substrate, the source electrode extends in the first direction so as to overlap the first edge, The drain electrode extends in the first direction so as to overlap the second edge.

In one embodiment, the plurality of unit circuits include a first unit circuit and a second unit circuit, and in the display area, the plurality of source bus lines are arranged in the second direction from one end. The first source bus line, the second source bus line, and the third source bus line arranged in the Nth (N is a natural number), (N + 1) th, (N + 2) th and (N + 3) th from the one end, respectively. And the fourth source bus line, wherein the first source bus line and the third source bus line are electrically connected to one of the plurality of video signal lines through the first unit circuit, The second source bus line and the fourth source bus line are electrically connected to the other one of the plurality of video signal lines via the second unit circuit, and are normal to the substrate. When viewed from the direction, one of said at least n DMX circuit TFT of the first unit circuit is disposed between the second source bus line and the fourth source bus lines.

In one embodiment, the n control signal branch lines in the first unit circuit and the second unit circuit are common, and one of the at least n DMX circuit TFTs in the first unit circuit; One of the at least n DMX circuit TFTs in the second unit circuit is connected to the same control signal line, and is arranged on the same control signal line with a gap.

In one embodiment, in each of the DMX circuit TFTs, when viewed from the normal direction of the substrate, the source edge of the source electrode facing the drain electrode and / or the source electrode of the drain electrode The opposing drain edge includes a region overlapping with the oxide semiconductor layer, at least one protrusion protruding in the second direction, and a recess or notch adjacent to the at least one protrusion in the first direction. The length of the at least one convex portion in the second direction is less than 1/3 of the width of the gate electrode in the second direction.

In one embodiment, the oxide semiconductor layer includes an In—Ga—Zn—O-based semiconductor.

In one embodiment, the In—Ga—Zn—O-based semiconductor includes a crystalline portion.

According to one embodiment of the present invention, it is possible to provide an active matrix substrate capable of reducing driving power of a peripheral circuit including an oxide semiconductor TFT.

It is the schematic which shows an example of the planar structure of the active matrix substrate 1000 of 1st Embodiment. FIGS. 7A and 7B are a plan view and a cross-sectional view illustrating a circuit TFT (thin film transistor 10 </ b> A) included in a peripheral circuit monolithically formed on the active matrix substrate 1000 of the first embodiment, respectively. (A) And (b) is the top view and sectional drawing which illustrate other circuit TFT (thin film transistor 10B) in 1st Embodiment, respectively. (A) And (b) is the top view and sectional drawing which illustrate further other circuit TFT (thin film transistor 10C) in 1st Embodiment, respectively. It is a top view which illustrates thin-film transistor 10B when alignment arises. FIG. 10 is a plan view illustrating still another circuit TFT in the first embodiment. (A)-(d) is a top view which shows TFT of the reference example 1 and Examples 1-3. (A)-(c) is a top view which shows the structure of the sample TFT of the reference example used for the measurement, the sample TFT which has a symmetrical structure, and the sample TFT which has an asymmetrical structure, respectively. It is a figure which shows the measured value of the on-current per unit W / L of TFT which has a symmetrical structure and an asymmetrical structure. It is a figure for demonstrating the structure and operation | movement of the demultiplexer circuit DMX in 1st Embodiment. 2 is a plan view illustrating an SSD unit circuit 100. FIG. (A) and (b) are a plan view and a cross-sectional view taken along line IV-IV ′ of one pixel region PIX in the active matrix substrate 1000, respectively. (A) And (b) is the top view and sectional drawing which show the other circuit TFT (thin film transistor 10D) in 1st Embodiment, respectively. (A) is a figure for demonstrating the structure of the demultiplexer circuit DMX in 2nd Embodiment, and shows one subcircuit 200 in the demultiplexer circuit DMX, (b) is the signal waveform of the subcircuit 200 It is a figure (timing chart) which shows an example. It is a top view which shows an example of the layout of the demultiplexer circuit DMX in 2nd Embodiment. FIG. 10 is an enlarged plan view illustrating a sub circuit 200A of a demultiplexer circuit DMX according to a second embodiment. It is a top view which shows a part of other subcircuit 200B of the demultiplexer circuit DMX in 2nd Embodiment. It is a top view which shows a part of other subcircuit 200C of the demultiplexer circuit DMX in 2nd Embodiment. It is a top view which shows a part of other subcircuit 200D of the demultiplexer circuit DMX in 2nd Embodiment. It is an enlarged plan view showing a part of another sub-circuit 200E of the demultiplexer circuit DMX in the second embodiment. It is an enlarged plan view showing a part of another sub-circuit 200F of the demultiplexer circuit DMX in the second embodiment. It is an enlarged plan view showing a part of another sub-circuit 200G of the demultiplexer circuit DMX in the second embodiment. It is a figure which shows the structure of the other subcircuit 300 of the demultiplexer circuit DMX in 2nd Embodiment. 3 is an enlarged plan view showing an example of a sub circuit 300. FIG. It is a figure which illustrates the structure of the other subcircuits 400 (1) and 400 (2) of the demultiplexer circuit DMX in 2nd Embodiment. (A) And (b) is the top view and sectional drawing which illustrate TFT (thin film transistor 90) of the reference example 2 used for the demultiplexer circuit DMX, respectively. It is a figure which illustrates the shift register circuit in 3rd Embodiment. It is a figure which shows an example of the unit shift register circuit SR.

(First embodiment)
Hereinafter, the active matrix substrate of the first embodiment will be described with reference to the drawings. Hereinafter, an active matrix substrate in which an SSD circuit and a gate driver are monolithically formed and a source driver is mounted will be described as an example. Note that the active matrix substrate of the present embodiment only needs to have a monolithic peripheral circuit including at least one TFT.

<Structure of active matrix substrate>
FIG. 1 is a schematic diagram illustrating an example of a planar structure of an active matrix substrate 1000 according to the present embodiment.

The active matrix substrate 1000 has a display area DR and an area (non-display area or frame area) FR other than the display area DR. The display area DR is composed of pixel areas PIX arranged in a matrix. The pixel region PIX (sometimes simply referred to as “pixel”) is a region corresponding to a pixel of the display device. The non-display area FR is an area that is located around the display area DR and does not contribute to display.

In the display region DR, a plurality of gate bus lines GL (1) to GL (j) (j is an integer of 2 or more, hereinafter referred to as “gate bus line GL”) extending in the x direction (also referred to as row direction or second direction). And a plurality of source bus lines SL (1) to SL (k) (k is an integer of 2 or more, hereinafter referred to as “source bus line SL”) extending in the y direction (also referred to as column direction or first direction). Are collectively called). Each pixel region PIX is defined by a gate bus line GL and a source bus line SL, for example. Each gate bus line GL is connected to each terminal of the gate driver GD. The source bus line SL is connected to each terminal of the source driver SD.

Each pixel region PIX includes a thin film transistor Pt and a pixel electrode PE. The thin film transistor Pt is also referred to as a “pixel TFT”. The gate electrode of the thin film transistor Pt is electrically connected to the corresponding gate bus line GL, and the source electrode is electrically connected to the corresponding source bus line SL. The drain electrode is electrically connected to the pixel electrode PE. When the active matrix substrate 1000 is applied to a display device in a horizontal electric field mode such as an FFS (Fringe Field Switching) mode, the active matrix substrate 1000 is provided with a common electrode (common electrode) CE for a plurality of pixels. It is done. In a case where the active matrix substrate 1000 is applied to a vertical electric field mode display device, the common electrode CE is provided on a counter substrate that is disposed to face the active matrix substrate 1000 with a liquid crystal layer interposed therebetween.

In the non-display area FR, for example, a gate driver GD that drives the gate bus line GL, a demultiplexer circuit DMX, and the like are provided integrally (monolithically). The demultiplexer circuit DMX functions as an SSD circuit that drives the source bus line SL in a time division manner. The source driver SD that drives the source bus line SL is mounted on the active matrix substrate 1000, for example.

In the illustrated example, the gate driver GD is disposed in the region FRa located on both sides of the display region DR, and the source driver SD is mounted in the region FRb located below the display region DR. The demultiplexer circuit DMX is arranged between the display region DR and the source driver SD in the region FRb. Between the demultiplexer circuit DMX and the source driver SD is a terminal portion / wiring forming region LR in which a plurality of terminal portions and wirings are formed.

<Structure of circuit TFT>
2A and 2B are a plan view and a cross-sectional view illustrating a circuit TFT (thin film transistor 10A) included in a peripheral circuit monolithically formed on the active matrix substrate 1000 of this embodiment, respectively. The thin film transistor 10A can be used, for example, as a switching element (DMX circuit TFT) of an SSD circuit or as an output transistor of a gate driver circuit. Note that the active matrix substrate 1000 of the present embodiment only needs to include at least one thin film transistor 10A as a circuit TFT, and may further include a circuit TFT having another structure.

The thin film transistor 10A is supported on the substrate 1 and formed in a non-display area. The thin film transistor 10A includes a gate electrode (also referred to as “lower gate electrode”) 3 disposed on the substrate 1, a gate insulating layer 5 covering the gate electrode 3, an oxide semiconductor layer 7, a source electrode 8, and a drain electrode. 9. The oxide semiconductor layer 7 is disposed on the gate insulating layer 5 so as to at least partially overlap the gate electrode 3 with the gate insulating layer 5 interposed therebetween.

The source electrode 8 is provided on the oxide semiconductor layer 7 and is in contact with a part of the oxide semiconductor layer 7. The drain electrode 9 is provided on the oxide semiconductor layer 7 and is in contact with another part of the oxide semiconductor layer 7. In this specification, a portion of the oxide semiconductor layer 7 in contact with the source electrode 8 is referred to as a source contact region 7s, and a portion in contact with the drain electrode 9 is referred to as a drain contact region 7d. When viewed from the normal direction of the substrate 1, a region located between the source contact region 7 s and the drain contact region 7 d and overlapping the gate electrode 3 is a “channel region 7 c”. In this embodiment, when the end portions facing each other in the channel length direction of the oxide semiconductor layer 7 are p1 and p2, the source contact region 7s is disposed on the end portion p1 side of the channel region 7c, and the end of the channel region 7c A drain contact region 7d is disposed on the portion p2 side.

In this specification, in a plane parallel to the substrate 1, the direction DL parallel to the direction of current flow in the channel region 7c is referred to as “channel length direction”, and the direction DW perpendicular to the channel length direction DL is referred to as “channel width direction”. Call. In the channel region 7c, the length along the channel length direction DL is the channel length L, and the length along the channel width direction DW is the channel width W. In the present embodiment, the channel length direction DL is a direction connecting the end portions p1 and p2. A source contact region 7s, a channel region 7c, and a drain contact region 7d are arranged in this order along the channel length direction DL from the end p1 to the end p2. Note that depending on the shape and arrangement of the gate electrode 3, the oxide semiconductor layer 7, and the drain contact region 7 d, the direction of current flow through the channel region 7 c may not be one direction. In that case, a channel length direction DL is a direction connecting the end portions p1 and p2 of the oxide semiconductor layer 7 or a direction connecting the shortest distance between the source contact region 7s and the drain contact region 7d.

The source electrode 8 and the drain electrode 9 are preferably designed to overlap the gate electrode 3 when viewed from the normal direction of the substrate 1. The lengths xs and xd where the source electrode 8 and the drain electrode 9 overlap the gate electrode 3 can be set in consideration of alignment accuracy.

The gate electrode 3 has a first edge 3e1 and a second edge 3e2 that face each other when viewed from the normal direction of the substrate 1. The first edge 3e1 and the second edge 3e2 extend across the oxide semiconductor layer 7 generally in the channel width direction DW. In this example, the first edge 3 e 1 crosses one end p 1 of the oxide semiconductor layer 7, and the second edge 3 e 2 crosses the other end p 2 of the oxide semiconductor layer 7. The width wg of the gate electrode 3 in the channel length direction DL is smaller than the width ws of the oxide semiconductor layer 7 in the channel length direction DL.

The source electrode 8 extends across the oxide semiconductor layer 7 in the channel width direction DW so as to overlap the first edge 3e1 of the gate electrode 3 when viewed from the normal direction of the substrate 1. Similarly, the drain electrode 9 extends across the oxide semiconductor layer 7 in the channel width direction DW so as to overlap the second edge 3e2 of the gate electrode 3. As described above, in the thin film transistor 10A, when viewed from the normal direction of the substrate 1, only a part of the width of the source electrode 8 and the drain electrode 9 (width in the channel length direction DL direction) overlaps with the gate electrode 3. Is done. Therefore, the gate-source / drain parasitic capacitance can be reduced as compared with the case where the entire width of the source electrode 8 and the drain electrode 9 overlaps with the gate electrode 3 (see FIG. 7A).

When viewed from the normal direction of the substrate 1, only one of the source electrode 8 and the drain electrode 9 is disposed so as to overlap the edge of the gate electrode 3, and the entire width of the other electrode is the same as that of the gate electrode 3. It may overlap. For example, when the widths of the source electrode 8 and the drain electrode 9 are substantially equal, the source electrode 8 extends so that the entire width thereof overlaps with the gate electrode 3, and the drain electrode 9 overlaps with the second edge 3 e 2 of the gate electrode 3. The overlapping area of the drain electrode 9 and the gate electrode 3 may be smaller than the overlapping area of the source electrode 8 and the gate electrode 3.

The source electrode 8 has a first source edge 8e1 and a second source edge 8e2 extending in the channel width direction DW. In any cross section of the oxide semiconductor layer 7 in the channel length direction DL, the first source edge 8e1 and the second source edge 8e2 of the source electrode 8 may both be located on the oxide semiconductor layer 7. Good. The drain electrode 9 has a first drain edge 9e1 and a second drain edge 9e2 extending in the channel width direction DW. In any cross section in the channel length direction DL of the oxide semiconductor layer 7, the first drain edge portion 9 e 1 and the second drain edge portion 9 e 2 of the drain electrode 9 may both be located on the oxide semiconductor layer 7. Good. In such a configuration, the width wT of the thin film transistor 10 </ b> A in the channel length direction DL is determined by the width ws of the oxide semiconductor layer 7.

In the present embodiment, the source electrode 8 and the drain electrode 9 are formed using the same conductive film as the source bus line SL (FIG. 1). A layer formed using the same conductive film as the source bus line SL is referred to as a “source metal layer”. The gate electrode 3 is formed using the same conductive film as the gate bus line GL (FIG. 1). A layer formed using the same conductive film as the gate bus line GL is referred to as a “gate metal layer”.

The thin film transistor 10A is covered with a protective layer (here, an inorganic insulating layer) 11. The inorganic insulating layer 11 is disposed so as to be in contact with the upper surfaces of the source electrode 8 and the drain electrode 9 and the channel region 7 c of the oxide semiconductor layer 7.

The lengths (overlapping lengths) xs and xd where the source electrode 8, the drain electrode 9 and the gate electrode 3 overlap can be set in consideration of alignment accuracy. For example, even when alignment occurs in the channel length direction DL, the oxide semiconductor layer 7 is set so that a region (offset region) that does not overlap any of the gate electrode 3, the source electrode 8, and the drain electrode 9 does not occur. Can be done. The overlapping lengths xs and xd vary depending on the manufacturing apparatus, but are, for example, 1.5 μm or more and 3.0 μm or less.

FIGS. 3A and 3B are a plan view and a cross-sectional view illustrating another circuit TFT (thin film transistor 10B) in this embodiment, respectively. 4A and 4B are a plan view and a cross-sectional view illustrating still another circuit TFT (thin film transistor 10C) in this embodiment, respectively. In these drawings, the same components as those in FIG. 2 are denoted by the same reference numerals. In the following description, differences from the thin film transistor 10A shown in FIG. 2 will be mainly described, and description of the same configuration as the thin film transistor 10A will be omitted.

The thin film transistors 10B and 10C differ from the thin film transistor 10A in that the source electrode 8 and / or the drain electrode 9 have protrusions protruding in the channel length direction when viewed from the normal direction of the substrate 1.

The source electrode 8 in the thin film transistors 10B and 10C has a first source edge 8e1 facing the drain electrode 9. Similarly, the drain electrode 9 has a first drain edge 9 e 1 facing the source electrode 8. The first source edge 8e1 includes one or a plurality of protrusions 82 protruding in the channel length direction DL, a recess 84 adjacent to the protrusion 82 in the channel width direction DW, and / or a region overlapping the oxide semiconductor layer 7. Or it has the notch part 86. FIG. Similarly, the first drain edge 9e1 includes one or a plurality of protrusions 92 protruding in the channel length direction DL and a recess adjacent to the protrusion 92 in the channel width direction DW in a region overlapping with the oxide semiconductor layer 7. 94 and / or a notch 96. In the present embodiment, the channel length L is the distance between the portion of the convex portion 82 closest to the drain electrode 9 and the portion of the convex portion 92 closest to the source electrode 8.

In the illustrated example, the protrusions 82 and 92 are rectangular when viewed from the normal direction of the substrate 1, but may not be rectangular. For example, the convex portions 82 and 92 may be rounded.

In this example, the second source edge 8e2 of the source electrode 8 and the second drain edge 9e2 of the drain electrode 9 are located not on the oxide semiconductor layer 7 but on the gate insulating layer 5. In this case, the width wT of the thin film transistors 10B and 10C in the channel length direction DL is determined by the distance wSD between the second source edge 8e2 and the second drain edge 9e2.

In the thin film transistor 10B, the protrusion 82 of the first source edge 8e1 and the protrusion 92 of the first drain edge 9e1 face each other in the channel length direction DL. Further, the recess 84 or notch 86 of the first source edge 8e1 and the recess 94 or notch 96 of the first drain edge 9e1 face each other in the channel length direction DL. In this specification, as illustrated in the thin film transistor 10B, when a line extending in the channel length direction DL from the center of each convex portion 82 of the first source edge 8e1 toward the drain side is drawn, An electrode structure in which the convex portion 92 of the drain edge portion 9e1 is located is referred to as a “symmetric structure”. In addition, the planar shape such as the length in the channel length direction may be different between the convex portion 82 and the convex portion 92.

In the thin film transistor 10C, the protrusion 82 of the first source edge 8e1 and the recess 94 or the notch 96 of the first drain edge 9e1 face each other in the channel length direction DL, and the recess of the first source edge 8e1. 84 or the notch 86 and the protrusion 92 of the first drain edge 9e1 face each other in the channel length direction DL. In this specification, as illustrated in the thin film transistor 10C, when a line extending in the channel length direction DL from the center of the convex portion 82 of the first source edge 8e1 toward the drain side is drawn, the first drain is formed on the line. The electrode structure when the convex portion 92 of the edge portion 9e1 is not located is referred to as “asymmetric structure”.

In the thin film transistors 10B and 10C, the distance between the first edge 3e1 and the portion of the convex portion 82 of the source electrode 8 that is closest to the drain electrode 9 is the overlap length xs of the source electrode 8 and the gate electrode 3. . Similarly, the distance between the second edge 3e2 and the portion of the projection 92 of the drain electrode 9 that is closest to the source electrode 8 is the overlap length xd of the drain electrode 9 and the gate electrode 3. Therefore, it is possible to reduce the overlapping area between the source electrode 8 or the drain electrode 9 and the gate electrode 3 as compared with the thin film transistor 10A while ensuring predetermined overlapping lengths xd and xs (for example, 1.5 μm or more and 3.0 μm or less). For example, in the case where the overlap lengths xd and xs are the same, by providing the convex portions 82 and 92, the source electrode is provided by the area of the concave portions 84 and 94 and the notches 86 and 96 while ensuring the on-current. 8 or the overlapping area of the drain electrode 9 and the gate electrode 3 can be reduced.

In addition, it is preferable that the source electrode 8 and the drain electrode 9 do not have a comb structure (see Patent Document 1) arranged so that the convex portion of the other electrode is positioned in the concave portion of one electrode. If it has a comb structure, the size and parasitic capacitance of the TFT may increase.

The length h of the protrusions 82 and 92 in the channel length direction DL is, for example, 1 / w of the width of the gate electrode 3 in the channel length direction DL (that is, the distance between the first edge 3e1 and the second edge 3e2). Less than 3. Thereby, the overlapping area of the source electrode 8 and the drain electrode 9 and the gate electrode 3 can be reduced while suppressing an increase in the TFT width wT. On the other hand, if the length h in the channel length direction DL of the protrusions 82 and 92 is, for example, 1/10 or more of the width wg of the gate electrode 3, the overlapping area of the source electrode 8 and the drain electrode 9 with the gate electrode 3 is further increased. It can be effectively reduced.

When the width (length in the channel width direction DW) fs and fd of the plurality of protrusions 82 and 92 disposed on the oxide semiconductor layer 7 or only one protrusion 82 and 92 is disposed. The widths fs and fd of the protrusions 82 and 92 may be 70% or more of the channel width W (here, the width of the oxide semiconductor layer 7 in the channel width direction DW). As a result, it is possible to reduce the gate-drain capacitance Cdg or the source-drain capacitance Csg (hereinafter abbreviated as “parasitic capacitance Cdg, Csg”) while more reliably suppressing the decrease in the on-current. . On the other hand, if the widths fs and fd of the protrusions 82 and 92 or the sum thereof is 90% or less of the channel width W, the overlapping area between the source electrode 8 or the drain electrode 9 and the gate electrode 3 can be more effectively reduced. The parasitic capacitance Cdg or Csg can be reduced more effectively. The above effect can be obtained if at least one of the widths fs and fd satisfies the above range.

When the plurality of convex portions 82 and 92 are periodically arranged on the first source edge portion 8 e 1 or the first drain edge portion 9 e 1, the widths fs and fd of the respective convex portions 82 and 92 are the same as those of the convex portions 82 and 92. It may be 70% or more and 90% or less of the arrangement pitch.

The arrangement pitch, width, and length in the channel length direction of the projections 82 of the source electrode 8 may be the same as the arrangement pitch, width, and length in the channel length direction of the projections 92 of the drain electrode 9, respectively. May be different.

In the thin film transistors 10B and 10C, when a misalignment between the gate metal layer and the source metal layer occurs in the channel length direction DL, the source electrode 8 when viewed from the normal direction of the substrate 1, for example, as illustrated in FIG. And a part of one of the recesses or notches of the drain electrode 9 (here, the recess 94 and the notch 96 of the drain electrode 9) do not overlap with the gate electrode 3, and as a result, the oxide semiconductor layer 7 There is a possibility that an offset region 7off occurs. The offset region 7off is located between the channel region 7c and the source electrode 8 and the drain electrode 9 in the oxide semiconductor layer 7 when viewed from the normal direction of the substrate 1, and the source electrode 8 and the drain electrode 9 And a region that does not overlap any of the gate electrode 3. The width Loff of the offset region 7off in the channel length direction DL is defined as an “offset width”. The offset width Loff is equal to or less than the overlap lengths xd and xs (design values). In general, when an offset region is generated, the offset region has a higher resistance than the channel region in the on-state of the TFT, and there is a problem that the on-current of the TFT becomes small. On the other hand, in the present embodiment, a predetermined on-current can be ensured even when the offset region 7off occurs. In the present embodiment, the region 7n adjacent to the offset region 7off in the channel width direction DW in the oxide semiconductor layer 7 overlaps the convex portion 92 of the drain electrode 9, and functions as the channel region 7c. That is, the plurality of offset regions 7off are arranged apart from each other in the channel width direction WD. Therefore, a decrease in on-current due to the offset region 7off is suppressed as compared with a case where an offset region is formed between the channel region 7c and the source contact region 7s or the drain contact region 7d in the oxide semiconductor layer 7. It is possible.

The structure of the thin film transistor in this embodiment is not limited to the structure described with reference to FIGS. For example, as illustrated in FIG. 6, a convex portion may be formed on only one of the source electrode 8 and the drain electrode 9. Such an electrode structure is also included in the “asymmetric structure”. In addition, as will be described later with reference to FIG. 13, the thin film transistor of this embodiment may have a double gate structure in which another gate electrode is further provided above the oxide semiconductor layer 7). As a result, the on-current can be further increased.

<Estimation of parasitic capacitance of TFT>
The present inventor has calculated the parasitic capacitance and TFT characteristics of the TFTs of Reference Example 1 and Example, and the results will be described.

FIGS. 7A to 7D are plan views showing TFTs of Reference Example 1 and Examples 1 to 3. FIG. In the TFT of Reference Example 1, the source electrode 8 and the drain electrode 9 are arranged so as to overlap the gate electrode 3 over the entire width when viewed from the normal direction of the substrate 1. The TFTs of Examples 1 to 3 have the same structure as the thin film transistors 10A to 10C, respectively.

As shown in the figure, in any TFT, the channel length L is 2.5 μm, the channel width W is 20 μm, the width of the source electrode 8 and the drain electrode 9 is 2.5 μm, the first source edge 8e1 and the first drain edge. The distance x1 between 9e1 and the edge of the oxide semiconductor layer 7 extending in the channel width direction DW was 3 μm. The overlapping lengths xd and xs of the TFTs of Examples 1 to 3 were 1.5 μm. Further, the width wg in the channel length direction DL of the gate electrode 3 of the TFT of Reference Example 1 was set to 12 μm, and the width wg of the gate electrode 3 of the TFT of Examples 1 to 3 in the channel length direction DL was set to 5.5 μm. Further, in the TFTs of Examples 2 and 3, the projections 82 and 92 having widths fs and fd of 3.5 μm and a length h in the channel length direction of 0.9 μm are respectively formed on the source electrode 8 and the drain electrode 9 by 7 μm. Arrangement pitches p (fs) and p (fd).

When the parasitic capacitance (total of gate-drain capacitance Cdg and source-drain capacitance Csg) in the TFTs of Reference Example 1 and Examples 1 to 3 was calculated, it was assumed that the parasitic capacitance in the TFT of Reference Example 1 was 1. The parasitic capacitance of the TFT of Example 1 was 0.71, the parasitic capacitance of the TFT of Example 2 was 0.63, and the parasitic capacitance of the TFT of Example 3 was 0.57.

From this result, it was confirmed that the parasitic capacitance of the TFTs of Examples 1 to 3 can be reduced as compared with the TFT of Reference Example 1. It was also confirmed that the parasitic capacitance can be further reduced as compared with the TFT of Example 1 by providing the projections 82 and 92 on the source electrode 8 and the drain electrode 9 (Examples 2 and 3). Furthermore, in the TFT of Example 3 having an asymmetric structure, the ratio of the width (total) of the protrusions 92 to the channel width W of one electrode (here, the drain electrode 9) can be reduced. It was found that the parasitic capacitance can be made smaller than that of the TFT 2.

Therefore, when a peripheral circuit (for example, a demultiplexer circuit) is formed using the TFTs of Examples 1 to 3, the driving power of the peripheral circuit is 71% and 63%, respectively, as compared with the case of using the TFT of Reference Example 1. , It can be reduced to 57%.

<Relationship between width of source / drain electrode in channel width direction and on characteristics of TFT>
Subsequently, the relationship between the width of the source electrode 8 and the drain electrode 9 in the channel width direction (hereinafter referred to as “electrode width”) f and the on-current of the TFT was examined. The electrode width f corresponds to the width (or the total) of the convex portions of the source electrode 8 or the drain electrode 9 in the channel width direction DW in the thin film transistor of this embodiment. Here, a plurality of sample TFTs having different electrode structures were produced, and their on-currents were measured.

FIGS. 8A to 8C are plan views showing the structures of the reference sample TFT used in the measurement, the sample TFT having a symmetric structure, and the sample TFT having an asymmetric structure, respectively. In any sample TFT, the channel width W (here, the width in the channel width direction DW of the oxide semiconductor layer 7 is defined as the channel width) is 10 μm, and the channel length L is 3 μm.

In the sample TFT of the reference example, the source electrode 8 and the drain electrode 9 are arranged over the channel width W as shown in FIG.

In the sample TFT having a symmetric structure, as shown in FIG. 8B, the width f of the source electrode 8 and the drain electrode 9 in the channel width direction DW is smaller than the channel width W (f <W). The width f of the source electrode 8 and the drain electrode 9 is the same. Further, the source electrode 8 and the drain electrode 9 are arranged so as to be symmetrical with respect to the center line extending in the channel width direction DW of the oxide semiconductor layer 7. Here, as sample TFTs having a symmetric structure, a plurality of sample TFTs were produced with different electrode widths f.

In the sample TFT having an asymmetric structure, the source electrode 8 is disposed over the channel width W as shown in FIG. 8C, but the width f of the drain electrode 9 in the channel width direction DW is greater than the channel width W. Is also small. Here, as the sample TFT having an asymmetric structure, a plurality of sample TFTs were manufactured by changing the electrode width f of the drain electrode 9.

Next, the on-current per unit W / L of the plurality of sample TFTs described above was measured.

FIG. 9 is a diagram showing measured values of on-current per unit W / L of a sample TFT having a symmetric structure and an asymmetric structure. The vertical axis represents the relative value of the on-current of each sample TFT when the on-current of the sample TFT of the reference example is 1. The horizontal axis represents the ratio of the electrode width f to the channel width W (the width of the oxide semiconductor layer 7 in the channel width direction DW).

As can be seen from FIG. 9, when the ratio of the electrode width f to the channel width W becomes smaller, the on-current tends to decrease.

However, in the sample TFT having a symmetric structure, when the ratio of the electrode width f to the channel width W is 0.7 or more, an on-current of 0.95 or more of the on-current of the sample TFT of the reference example can be secured. As shown by an arrow 51 in FIG. 8B, this is because the portion 9a of the side surface of the drain electrode 9 that faces the source electrode 8 and the portion of the side surface of the source electrode 8 that faces the drain electrode 9 are separated. In addition to the current flowing between them, as indicated by an arrow 52, a portion 9b extending in the channel length direction DL on the side surface of the drain electrode 9 and a portion 8b extending in the channel length direction DL on the side surface of the source electrode 8 This is probably because current can flow between them. Therefore, the effective channel width W ′ is larger than the electrode width f by the width ΔW1 of the region where current can flow along the arrow 52 (f <W ′ <W). As a result, even if the ratio of the electrode width f is 0.7, it is possible to ensure an on-current substantially equal to that of the sample TFT of the reference example.

On the other hand, in the sample TFT having an asymmetric structure, when the ratio of the electrode width f of the drain electrode 9 to the channel width W is 0.6 or more, an on-current of 0.95 or more of the on-current of the sample TFT of the reference example is secured. it can. This is because, as shown by an arrow 51 in FIG. 8C, not only a current flows between a portion 9 a of the side surface of the drain electrode 9 facing the source electrode 8 and the source electrode 8 but also an arrow 53. Thus, it is considered that the current can also flow between the source electrode 8 and the portion 9b extending in the channel length direction DL on the side surface of the drain electrode 9. Therefore, the effective channel width W ′ is larger than the electrode width f by the width ΔW2 (ΔW2> ΔW1) of the region where current can flow along the arrow 53 (f <W ′ <W). As a result, even if the ratio of the electrode width f is 0.6, it is possible to ensure an on-current substantially equal to that of the sample TFT of the reference example.

From the above examination results, it can be seen that, in the TFT structure of this embodiment, by appropriately controlling the widths of the convex portions of the source electrode 8 and the drain electrode 9, it is possible to reduce the parasitic capacitance while ensuring a high on-current.

<Configuration and operation of demultiplexer circuit>
The thin film transistors 10A to 10C described in the first embodiment can be applied, for example, to a switching element (“DMX circuit TFT”) of a demultiplexer circuit provided in a peripheral region of a display device.

FIG. 10 is a diagram for explaining the configuration and operation of the demultiplexer circuit DMX in the active matrix substrate 1000 of the present embodiment.

A demultiplexer circuit DMX (in this case, an SSD circuit) is arranged between the source driver SD and the display area DR. The demultiplexer circuit DMX includes a plurality of SSD unit circuits 100 (1) to 100 (i) (i is an integer of 2 or more) (sometimes collectively referred to as “SSD unit circuit 100”), and control signal trunk lines SW1 to SWn. (N is an integer of 2 or more, here n = 3). The demultiplexer circuit DMX and the source driver SD are controlled by the control circuit 150 provided in the non-display area FR. The control signal trunk lines SW1 to SWn are connected to the control circuit 150.

Each of the output terminals V (1) to V (i) (hereinafter sometimes collectively referred to as “V terminal”) of the source driver SD has a plurality of video signal lines DO (1) to DO (i) (“ Any of the video signal lines DO may be collectively referred to. A group of n source bus lines SL is associated with one video signal line DO. An SSD unit circuit 100 is provided for each video signal line between the video signal line DO and the grouped source bus lines SL. The SSD unit circuit 100 distributes video data from one video signal line DO to n source bus lines SL.

In this embodiment, among the plurality of video signal lines DO (1) to DO (i), the Nth video signal line is DO (N) (N is an integer from 1 to i), and the video signal line DO (N). Assume that the SSD unit circuit 100 and the source bus line SL that are associated with are 100 (N), SL (N−1) to SL (Nn), respectively. The source bus lines SL (N−1) to SL (Nn) may be associated with, for example, R, G, and B pixels (that is, n = 3).

Each SSD unit circuit 100 (N) includes n branch wirings B1 to Bn connected to the video signal line DO (N) and at least n (here, 3) TFTs 10 (1) to 10 for DMX circuits. 10 (n) (sometimes collectively referred to as “DMX circuit TFT 10”).

The DMX circuit TFT 10 functions as a selection switch. The gate electrode of the DMX circuit TFT 10 is electrically connected to a corresponding one of the n control signal trunk lines SW1 to SWn. The source electrode of the DMX circuit TFT 10 is electrically connected to a corresponding one of the branch lines B1 to Bn. The drain electrode of the DMX circuit TFT 10 is connected to one corresponding source bus line among the source bus lines SL (N−1) to SL (N−3).

A selection signal (control signal) is supplied from one of the control signal trunk lines SW1 to SW3 to the gate electrode of the TFT 10 for DMX circuit. The control signal defines the ON period of the selection switch in the same group and is synchronized with the time-series signal output from the source driver SD. The SSD unit circuit 100 (N) converts the data potential obtained by time-sharing the output of the video signal line DO (N) to a plurality of source bus lines SL (N−1) to source bus lines SL (Nn). Are written in time series (time division drive). Thereby, since the number of V terminals of the source driver SD can be reduced, the area of the non-display area FR can be further reduced (narrow frame).

The operation of the display device using the demultiplexer circuit DMX, the timing chart of time-division driving, etc. are disclosed in, for example, Japanese Patent Application Laid-Open No. 2008-225036, Japanese Patent Application Laid-Open No. 2006-119404, International Publication No. 2011/118079 (Patent Document 1). ) And the like. In this specification, for the purpose of reference, the entire disclosures of JP 2008-225036 A, JP 2006-119404 A, and International Publication 2011/118079 are incorporated herein by reference.

FIG. 11 is a plan view illustrating the SSD unit circuit 100 according to this embodiment. Here, the SSD unit circuit 100 is arranged with respect to the source bus lines SL (1) to SL (3) associated with the R, G, and B pixels (that is, n = 3).

The SSD unit circuit 100 includes three DMX circuit TFTs 10 (1) to (3) supported on the substrate 1 (hereinafter may be collectively referred to as “DMX circuit TFTs 10”), and extends from the display region DR. Source bus lines SL1 to SL3 (hereinafter sometimes collectively referred to as “source bus lines SL”), one video signal line DO, and branch wirings B1 to B3 (hereinafter collectively referred to as “branch wiring B”). And control signal trunk lines SW1 to SW3 (hereinafter sometimes collectively referred to as “control signal trunk line SW”). The video signal line DO is electrically connected to the branch lines B1 to B3. In this example, the source bus line SL extends in the y direction, and the control signal trunk line SW extends in the x direction intersecting the y direction. The branch wiring B and the video signal line DO are formed in the source metal layer. The gate electrode 3 and the control signal trunk line SW are formed in the gate metal layer.

In the DMX circuit TFT 10, the source electrode 8 extends in the channel width direction DW so as to overlap the first edge 3 e 1 of the gate electrode 3 and the drain electrode 9 overlaps the second edge 3 e 2 of the gate electrode 3. The DMX circuit TFT 10 may be any of the above-described thin film transistors 10A to 10C.

In the present embodiment, each of the DMX circuit TFTs 10 is disposed between two adjacent source bus lines SL (overlapping one source bus line). In this example, the DMX circuit TFT 10 is arranged such that its channel length direction DL is substantially parallel to the x direction and its channel width direction DW is substantially parallel to the y direction.

The source bus line SL may extend in the y direction from the display region toward the source driver SD, and may be in contact with the upper surface of one end p2 of the corresponding oxide semiconductor layer 7 extending in the channel width direction DW. A portion of the source bus line SL in contact with the oxide semiconductor layer 7 functions as the drain electrode 9 of the DMX circuit TFT 10.

Each branch wiring B extends in the y direction from the video signal line DO toward the display region, and is in contact with the upper surface of the other end p1 of the corresponding oxide semiconductor layer 7 extending in the channel width direction DW. A portion of the branch wiring B that contacts the oxide semiconductor layer 7 functions as the source electrode 8 of the DMX circuit TFT 10.

The gate electrode 3 of the DMX circuit TFT 10 is electrically connected to the corresponding control signal trunk line SW. In this example, the gate electrode 3 extends in the y direction toward the control signal main line SW. The extended portion (extended portion) 23 is electrically connected to the corresponding control signal trunk line SW via a connection wiring 25 formed in the source metal layer. For example, the connection wiring 25 is in contact with the extending portion 23 in the first opening 5p provided in the gate insulating layer 5 and in the second opening 5q provided in the gate insulating layer 5. May be in contact with. The extending portion 23 and the connection wiring 25 that connect the gate electrode 3 and the corresponding control signal trunk line SW may be collectively referred to as “control signal branch line”.

The DMX circuit TFT 10 and the demultiplexer circuit DMX may be covered with an inorganic insulating layer (passivation film) 11 (see FIG. 2). On the inorganic insulating layer 11, a planarizing film such as an organic insulating film may or may not be provided. For example, the display region DR of the active matrix substrate 1000 may be covered with the organic insulating film, and the non-display region FR may not be covered with the organic insulating film.

<Configuration of Pixel Area PIX>
Next, the configuration of each pixel region PIX in the active matrix substrate 1000 will be described. Here, an active matrix substrate applied to an FFS mode LCD panel will be described as an example.

FIGS. 12A and 12B are a plan view and a cross-sectional view taken along line IV-IV ′ of one pixel region PIX in the active matrix substrate 1000, respectively.

The pixel area PIX is an area surrounded by a source bus line SL extending in the y direction and a gate bus line GL extending in the x direction intersecting the source bus line SL. The pixel region PIX includes a substrate 1, a TFT (hereinafter “pixel TFT”) 130 supported on the substrate 1, a lower transparent electrode 15, and an upper transparent electrode 19. Although not shown, the upper transparent electrode 19 has a slit or notch for each pixel. In this example, the lower transparent electrode 15 is a common electrode CE, and the upper transparent electrode 19 is a pixel electrode PE. The pixel TFT 10 is, for example, an oxide semiconductor TFT having a bottom gate structure.

Next, the structure of the pixel TFT 130 will be described in more detail.

The pixel TFT 130 is in contact with the gate electrode 103 supported on the substrate 1, the gate insulating layer 5 covering the gate electrode 103, the oxide semiconductor layer 107 formed on the gate insulating layer 5, and the oxide semiconductor layer 107. This is a TFT having a bottom gate structure having a source electrode 108 and a drain electrode 109 arranged in the bottom. The source electrode 108 and the drain electrode 109 are in contact with the upper surface of the oxide semiconductor layer 107.

The gate electrode 103 is connected to the corresponding gate bus line GL, and the source electrode 108 is connected to the corresponding source bus line SL. The drain electrode 109 is electrically connected to the pixel electrode PE. The gate electrode 103 and the gate bus line GL may be integrally formed in the gate metal layer. The source electrode 108 and the source bus line SL may be integrally formed in the source metal layer.

The interlayer insulating layer 13 is not particularly limited, and may include, for example, an inorganic insulating layer (passivation film) 11 and an organic insulating layer 12 disposed on the inorganic insulating layer 11. Note that the interlayer insulating layer 13 may not include the organic insulating layer 12.

The pixel electrode PE and the common electrode CE are arranged so as to partially overlap with each other via the dielectric layer 17. The pixel electrode PE is separated for each pixel. The common electrode CE may not be separated for each pixel. In this example, the common electrode CE is formed on the interlayer insulating layer 13. The common electrode CE may have an opening in a region where the pixel TFT 10 is formed, and may be formed over the entire pixel region PIX excluding this region. The pixel electrode PE is formed on the dielectric layer 17 and is electrically connected to the drain electrode 109 in the opening CH1 provided in the interlayer insulating layer 13 and the dielectric layer 17.

Such an active matrix substrate 1000 can be applied to an FFS mode display device, for example. The FFS mode is a transverse electric field mode in which a pair of electrodes is provided on one substrate and an electric field is applied to liquid crystal molecules in a direction parallel to the substrate surface (lateral direction). In this example, an electric field expressed by electric lines of force that exit from the pixel electrode PE, pass through a liquid crystal layer (not shown), and further pass through the slit-like opening of the pixel electrode PE to the common electrode CE is generated. This electric field has a component transverse to the liquid crystal layer. As a result, a horizontal electric field can be applied to the liquid crystal layer. The horizontal electric field method has an advantage that a wider viewing angle can be realized than the vertical electric field method because liquid crystal molecules do not rise from the substrate.

An electrode structure in which the pixel electrode PE is disposed on the common electrode CE via the dielectric layer 17 is described in, for example, International Publication No. 2012/0886513. Note that the common electrode CE may be disposed on the pixel electrode PE via the dielectric layer 17. That is, the lower transparent electrode 15 formed on the lower transparent conductive layer may be the pixel electrode PE, and the upper transparent electrode 19 formed on the upper transparent conductive layer may be the common electrode CE. Such electrode structures are described in, for example, Japanese Patent Application Laid-Open Nos. 2008-032899 and 2010-008758. For reference, the entire disclosures of International Publication No. 2012/086513, Japanese Patent Application Laid-Open No. 2008-032899, and Japanese Patent Application Laid-Open No. 2010-008758 are incorporated herein by reference.

<Material and thickness of each layer in active matrix substrate 1000>
The substrate 1 can be, for example, a glass substrate, a silicon substrate, a heat-resistant plastic substrate (resin substrate), or the like.

The gate metal layer including the gate electrode 3 and the gate bus line GL (thickness: for example, not less than 50 nm and not more than 500 nm) is, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr ), Titanium (Ti), copper (Cu), or a metal thereof, or an alloy thereof, or a metal nitride thereof. Moreover, you may form from the laminated film of these several films | membranes. The gate metal layer can be formed by forming a metal film on the substrate 1 by sputtering or the like and patterning it by a known photolithography process (photoresist application, exposure, development, etching, resist stripping). Etching is performed by wet etching, for example.

The gate insulating layer (thickness: for example, 200 nm to 500 nm or less) 5 includes, for example, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy; x> y) layer, a silicon nitride oxide (SiNxOy; x> y) layer and the like. The gate insulating layer 5 may have a stacked structure. In that case, oxygen vacancies in the oxide semiconductor layer 7 can be effectively reduced by disposing the SiO 2 film on the side of the gate insulating layer 5 in contact with the oxide semiconductor layer 7.

The oxide semiconductor layer 7 is formed of an oxide semiconductor film (thickness: for example, 15 nm to 200 nm) such as an In—Ga—Zn—O-based semiconductor.

The source metal layer (thickness: for example, 50 nm or more and 500 nm or less) including the source electrode 8, the drain electrode 9, and the source bus line SL is, for example, aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta). , Chromium (Cr), titanium (Ti), copper (Cu) and other metals or alloys thereof, or a film containing a metal nitride thereof. Moreover, you may form from the laminated film of these several films | membranes. The source metal layer has a laminated structure in which a Ti film (thickness: 30 nm), an Al or Cu film (thickness: 300 nm), and a Ti film (thickness 50 nm) are stacked in this order from the oxide semiconductor layer side. It may be.

The inorganic insulating layer (thickness: for example, 100 to 500 nm, preferably 200 to 500 nm) 11 includes, for example, a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, a silicon oxynitride (SiOxNy; x> y) film, and a nitride It is formed from an inorganic insulating film (passivation film) such as a silicon oxide (SiNxOy; x> y) film. The inorganic insulating layer 11 may have a laminated structure. When the SiO 2 film is disposed on the side of the inorganic insulating layer 11 in contact with the oxide semiconductor layer 7, oxygen vacancies in the oxide semiconductor layer 7 can be effectively reduced.

The organic insulating layer (thickness; for example, 1 to 3 μm, preferably 2 to 3 μm) 12 is formed of, for example, an organic insulating film containing a photosensitive resin material.

The lower transparent electrode 15 and the upper transparent electrode 19 (thickness: for example, 50 nm or more and 200 nm or less) are, for example, an ITO (indium / tin oxide) film or an In—Zn—O-based oxide (indium / zinc oxide) film, respectively. , ZnO film (zinc oxide film) or the like. The second inorganic insulating layer (thickness: for example, 70 nm to 300 nm) 17 includes a silicon nitride (SiNx) film, a silicon oxide (SiOx) film, a silicon oxynitride (SiOxNy; x> y) film, and a silicon nitride oxide (SiNxOy; x> y) It may be formed from a film or the like.

(About TFT structure)
The above-described thin film transistors 10A to 10C and the pixel TFT 130 are channel etch TFTs. In the channel etch TFT, an etch stop layer is not formed on the channel region, and the lower surface of the end of the source and drain electrodes on the channel side is disposed so as to be in contact with the upper surface of the oxide semiconductor layer. A channel etch type TFT is formed, for example, by forming a conductive film for a source / drain electrode on an oxide semiconductor layer and performing source / drain separation. In the source / drain separation step, the surface portion of the channel region may be etched.

The circuit TFTs (thin film transistors 10A to 10C) in the present embodiment have other gate electrodes (hereinafter referred to as “upper gate electrodes”) above the oxide semiconductor layer 7, that is, on the opposite side of the oxide semiconductor layer 7 from the substrate 1. May be further provided. Such a TFT structure is called a double gate structure.

FIGS. 13A and 13B are a plan view and a cross-sectional view showing a thin film transistor 10D having a double gate structure, respectively.

The thin film transistor 10D is different from the thin film transistor 10A (FIG. 2) described above in that it has an upper gate electrode BG.

The upper gate electrode BG is disposed on the oxide semiconductor layer 7 via an insulating film. When viewed from the normal direction of the substrate 1, the upper gate electrode BG at least partially overlaps the oxide semiconductor layer 7. When viewed from the normal direction of the substrate 1, the upper gate electrode BG has two edges BGe1 and BGe2 that face each other and extend in the channel width direction WD. The source electrode 8 may overlap with the edge BGe1, and the drain electrode 9 may overlap with the edge BGe2. Thereby, the overlapping area of the upper gate electrode BG, the source electrode 8 and the drain electrode 9 can be reduced.

In this example, the thin film transistor 10D is covered with an inorganic insulating layer 11 (passivation film), and the upper gate electrode BG is disposed on the inorganic insulating layer 11. That is, the inorganic insulating layer 11 is located between the upper gate electrode BG and the oxide semiconductor layer 7 and functions as a gate insulating film. The upper gate electrode BG may be, for example, a transparent electrode formed using the same transparent conductive film as a transparent electrode (for example, the pixel electrode PE) disposed in the display area.

In the active matrix substrate applied to the horizontal electric field mode display device, the lower transparent electrode 15 and the upper transparent electrode 19 are disposed in the display region via the dielectric layer 17 (see FIG. 12). One of the lower transparent electrode 15 and the upper transparent electrode 19 is a pixel electrode PE, and the other is a common electrode CE. In this case, the upper gate electrode BG can be formed using the same transparent conductive film as the lower transparent electrode 15 or the upper transparent electrode 19. When the upper gate electrode BG is formed using the same transparent conductive film as the lower transparent electrode 15, the inorganic insulating layer 11 that is a passivation film can function as a gate insulating film. When the upper gate electrode BG is formed using the same transparent conductive film as the upper transparent electrode 19, the inorganic insulating layer 11 and the dielectric layer 17 can function as a gate insulating film.

Although the upper gate electrode BG is provided in the thin film transistor 10A in FIG. 13, the upper gate electrode BG may be provided in the other thin film transistors 10B and 10C.

(About oxide semiconductors)
The oxide semiconductor included in the oxide semiconductor layer may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.

The oxide semiconductor layer may have a stacked structure of two or more layers. In the case where the oxide semiconductor layer has a stacked structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, a plurality of crystalline oxide semiconductor layers having different crystal structures may be included. In addition, a plurality of amorphous oxide semiconductor layers may be included. In the case where the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the upper layer is preferably larger than the energy gap of the oxide semiconductor included in the lower layer. However, when the difference in energy gap between these layers is relatively small, the energy gap of the lower oxide semiconductor may be larger than the energy gap of the upper oxide semiconductor.

The material, structure, film forming method, and structure of an oxide semiconductor layer having a stacked structure of the amorphous oxide semiconductor and each crystalline oxide semiconductor described above are described in, for example, Japanese Patent Application Laid-Open No. 2014-007399. . For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2014-007399 is incorporated herein by reference.

The oxide semiconductor layer may contain at least one metal element of In, Ga, and Zn, for example. In this embodiment, the oxide semiconductor layer includes, for example, an In—Ga—Zn—O-based semiconductor (eg, indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and a ratio (composition ratio) of In, Ga, and Zn. Is not particularly limited, and includes, for example, In: Ga: Zn = 2: 2: 1, In: Ga: Zn = 1: 1: 1, In: Ga: Zn = 1: 1: 2, and the like. Such an oxide semiconductor layer can be formed using an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline. As the crystalline In—Ga—Zn—O-based semiconductor, a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.

Note that the crystal structure of a crystalline In—Ga—Zn—O-based semiconductor is disclosed in, for example, the above-described Japanese Patent Application Laid-Open Nos. 2014-007399, 2012-134475, and 2014-209727. ing. For reference, the entire contents disclosed in Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-209727 are incorporated herein by reference. A TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT). The TFT is suitably used as a driving TFT (for example, a TFT included in a driving circuit provided on the same substrate as the display area around a display area including a plurality of pixels) and a pixel TFT (a TFT provided in the pixel).

The oxide semiconductor layer may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor. For example, an In—Sn—Zn—O-based semiconductor (eg, In 2 O 3 —SnO 2 —ZnO; InSnZnO) may be included. The In—Sn—Zn—O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer includes an In—Al—Zn—O based semiconductor, an In—Al—Sn—Zn—O based semiconductor, a Zn—O based semiconductor, an In—Zn—O based semiconductor, and a Zn—Ti—O based semiconductor. Semiconductor, Cd—Ge—O based semiconductor, Cd—Pb—O based semiconductor, CdO (cadmium oxide), Mg—Zn—O based semiconductor, In—Ga—Sn—O based semiconductor, In—Ga—O based semiconductor, A Zr—In—Zn—O based semiconductor, an Hf—In—Zn—O based semiconductor, an Al—Ga—Zn—O based semiconductor, a Ga—Zn—O based semiconductor, or the like may be included.

(Second Embodiment)
The active matrix substrate of the second embodiment includes a demultiplexer circuit (for example, an SSD circuit) DMX formed monolithically. This embodiment is different from the above-described embodiment (FIG. 11) in the configuration and arrangement of the demultiplexer circuit. Hereinafter, differences from the above-described embodiment will be mainly described, and description of similar configurations will be omitted.

The demultiplexer circuit of the present embodiment includes a plurality (at least n) of control signal trunk lines SW and a plurality of sub-circuits. Each sub-circuit includes at least two unit circuits (hereinafter referred to as “first unit circuit” and “second unit circuit”). From the control signal trunk line SW, n control signal branch lines C are provided for each sub-circuit. Each of the n control signal branch lines C is connected to one of the control signal trunk lines SW. That is, in each sub-circuit, the first and second unit circuits use a common control signal branch line C. The number of control signal branch lines C is n × number of sub-circuits. Therefore, the number of control signal branch lines C when the control signal branch line C is provided for each unit circuit (n × number of unit circuits) can be reduced to ½ or less.

<Configuration and Operation of Demultiplexer Circuit DMX>
In the following, an example in which each unit circuit includes two unit circuits will be described, but one unit circuit may include three or more unit circuits.

FIG. 14A is a diagram for explaining the configuration of the demultiplexer circuit DMX in the present embodiment, and shows one sub-circuit 200 in the demultiplexer circuit DMX.

The sub-circuit 200 has a first unit circuit and a second unit circuit. Here, each unit circuit is associated with two source bus lines (n = 2), and distributes one video signal to two source bus lines SL.

In the display area DR, a plurality of source bus lines SL extending in the y direction are arranged in the x direction. In this specification, a plurality of source bus lines SL included in one sub-circuit 200 are arranged in order from one end (here, the left end), respectively, the first source bus line SL1, the second source bus line SL2, These are referred to as a 3 source bus line SL3 and a fourth source bus line SL4.

In this example, the first unit circuit is associated with the first source bus line SL1 and the third source bus line SL3. The video signal V1 from the corresponding video signal line DO1 is distributed to the first source bus line SL1 and the third source bus line SL3 via the first unit circuit. The second unit circuit is associated with the second source bus line SL2 and the fourth source bus line SL4. The video signal V2 from the video signal line DO2 different from the first unit circuit is distributed to the second source bus line SL2 and the fourth source bus line SL4 via the second unit circuit. The first unit circuit and the second unit circuit also have common control signal branch lines C1 and C2. The control signal branch lines C1 and C2 (which may be collectively referred to as “control signal branch line C”) are electrically connected to the control signal trunk lines SW1 and SW2, respectively. The control signal branch line C is provided for each sub circuit.

The configuration of each unit circuit will be described more specifically. The first unit circuit includes two thin film transistors (DMX circuit TFTs) T1a and T1b, two branch lines B1a and B1b, and two control signal branch lines C1 and C2. The second unit circuit includes two thin film transistors (DMX circuit TFTs) T2a and T2b, two branch lines B2a and B2b, and control signal branch lines C1 and C2 common to the first unit circuit. The branch lines B1a and B1b of the first unit circuit are electrically connected to the video signal line DO1, and the branch lines B2a and B2b of the second unit circuit are electrically connected to the video signal line DO2. The drain electrodes of the thin film transistors T1a and T1b of the first unit circuit are connected to the first source bus line SL1 and the third source bus line SL3, respectively, and the source electrodes are connected to the branch lines B1a and B1b, respectively. The drain electrodes of the thin film transistors T2a and T2b of the second unit circuit are connected to the second source bus line SL2 and the fourth source bus line SL4, respectively, and the source electrodes are connected to the branch wirings B2a and B2b, respectively. The gate electrodes of the thin film transistors T1a and T2a are electrically connected to the control signal trunk line SW1 via the control signal branch line C1, respectively. The gate electrodes of the thin film transistors T1b and T2b are each electrically connected to the control signal trunk line SW2 via the control signal branch line C2.

N (here, two) source bus lines SL1, SL3 associated with the first unit circuit, and n (here, two) source bus lines SL2, SL4 associated with the second unit circuit. May be arranged alternately one by one in the x direction (row direction) in the display area.

As shown in the figure, each of the DMX circuit TFTs may have a back gate electrode on the opposite side across the gate electrode and the oxide semiconductor layer (double gate structure). The back gate electrode may be connected to the corresponding branch wiring B.

Next, the operation of the sub circuit 200 will be described.

FIG. 14B shows an example of signal waveforms of the gate bus line GL, the control signal branch lines C1 and C2, the video signals V1 and V2, the first source bus line SL1, and the second source bus line SL2 (timing chart). ). Here, only the write operation portion to the Mth gate bus line GL (M) and the (M + 1) th gate bus line GL (M + 1) will be described. The horizontal axis represents time, the period t1 to t4 is the writing time to the gate bus line GL (M) (one horizontal scanning period (1H period)), and the period t5 to t8 is the time to the gate bus line GL (M + 1). Write time (1H period).

First, in the period t1, the control signal of the control signal branch line C1 becomes a high level (high), and one of the two DMX circuit TFTs in each unit circuit is selected. In this example, the thin film transistors T1a and T2a are selected, and the video signal V1 is connected to the first source bus line SL1 via the thin film transistor T1a, and the video signal V2 is connected to the second source bus line SL2 via the thin film transistor T2a. . At this timing, the video signals V1 and V2 are each driven to a desired potential to charge the first source bus line SL1 and the second source bus line SL2.

In the period t2, the control signal of the control signal branch line C1 becomes low level (low), and the gates of the thin film transistors T1a and T2a are turned off, so that the potentials of the first source bus line SL1 and the second source bus line SL2 are determined. .

In the period t3, the control signal of the control signal branch line C2 becomes high level, and the other DMX circuit TFT of each unit circuit is selected. In this example, the thin film transistor T1b and the thin film transistor T2b are selected, and the video signal V1 is connected to the third source bus line SL3 via the thin film transistor T1b, and the video signal V2 is connected to the fourth source bus line SL4 via the thin film transistor T2b. The At this timing, the video signals V1 and V2 are each driven to a desired potential, and the third source bus line SL3 and the fourth source bus line SL4 are charged.

Next, in period t4, the control signal of the control signal branch line C2 becomes low level, and the gates of the thin film transistors T1b and T2b are turned off, so that the potentials of the third source bus line SL3 and the fourth source bus line SL4 are determined. At this timing, the voltage of the scanning signal of the gate bus line GL (M) becomes low level, and writing of the pixel potential is completed.

The operation during the period t5 to t8 is the same as the operation during the period t1 to t4 described above.

<Demultiplexer circuit layout>
FIG. 15 is a plan view showing an example of the layout of the demultiplexer circuit DMX.

As shown in FIG. 15, the demultiplexer circuit DMX is disposed below the display region DR when viewed from the normal direction of the substrate 1. In this example, the demultiplexer circuit DMX has a plurality of sub-circuits 200 arranged in the x direction. Each sub-circuit 200 has a shape extending in the y direction.

When each sub-circuit 200 is viewed from the normal direction of the substrate 1, the DMX circuit TFT of the second unit circuit is disposed in the first unit circuit formation region u1 in which the DMX circuit TFT of the first unit circuit is disposed. The second unit circuit formation region u2 is located on the display region side. That is, the first unit circuit is located between the second unit circuit and the display area. In this specification, such a configuration is referred to as a “two-stage configuration”.

Between the demultiplexer circuit DMX and the periphery of the non-display area FR, n (here, two) control signal main lines SW1 and SW2 are arranged. Control signal branch lines C1 and C2 of each sub-circuit 200 extend from the control signal trunk lines SW1 and SW2 into the demultiplexer circuit DMX, respectively. Although not shown, between the demultiplexer circuit DMX and the periphery of the non-display area FR, a drive circuit and a video signal line mounted with COG are also provided. The branch lines B1a, B2a, B1b, and B2b of each sub circuit 200 extend from the video signal line into the demultiplexer circuit DMX.

FIG. 16 is an enlarged plan view illustrating one sub circuit 200A in the demultiplexer circuit DMX.

In the sub circuit 200A, the branch wirings B1a, B2a, B1b, B2b, the control signal branch lines C1, C2, and the source bus lines SL1 to SL4 of the first unit circuit and the second unit circuit all extend in the y direction. Yes.

The control signal branch lines C1 and C2 each include a portion that functions as a gate electrode of the corresponding DMX circuit TFT. For example, the control signal branch line C1 is located between the branch wiring B1a and the branch wiring B2a when viewed from the normal direction of the substrate 1. The control signal branch line C1 protrudes in the x direction on the branch wiring B2a side and functions as a gate electrode of the thin film transistor T2a, and protrudes in the x direction on the branch wiring B2a side and functions as a gate electrode of the thin film transistor T1a. have. The oxide semiconductor layers 7 of the thin film transistors T1a and T2a are respectively disposed on these convex portions of the control signal branch line C1. As described above, one of the DMX circuit TFTs in the first unit circuit and one of the DMX circuit TFTs in the second unit circuit have gate electrodes integrally formed on the same control signal branch line C. Are arranged on the same control signal branch line C with a gap (two-stage configuration).

Each of the source bus lines SL1 to SL4 is in contact with the corresponding oxide semiconductor layer 7 of the DMX circuit TFT and includes a portion that functions as a drain electrode. For example, the first source bus line SL1 extends in the y direction from the display region DR and is in contact with the upper surface of the oxide semiconductor layer 7 of the thin film transistor T1a. The second source bus line SL2 extends from the display region DR between the thin film transistors T1a and T1b in the y direction and is in contact with the upper surface of the oxide semiconductor layer 7 of the thin film transistor T2a.

Branch wirings B1a, B2a, B1b, and B2b each include a portion that is in contact with the corresponding oxide semiconductor layer 7 of the DMX circuit TFT and functions as a source electrode. For example, the branch wiring B2a extends in the y direction from the COG side and is in contact with the upper surface of the oxide semiconductor layer 7 of the thin film transistor T2a. The branch wiring B1b extends from the COG side between the thin film transistors T2a and T2b in the y direction and is in contact with the upper surface of the oxide semiconductor layer 7 of the thin film transistor T1b.

When viewed from the normal direction of the substrate 1, the DMX circuit TFT of the first unit circuit is arranged between the Nth and (N + 2) th source bus lines SL associated with the second unit circuit. . For example, the thin film transistor T1b is disposed between the second source bus line SL2 and the fourth source bus line SL4. The DMX circuit TFT of the second unit circuit is disposed between two adjacent branch lines B in the first unit circuit. For example, the thin film transistor T2a is disposed between the branch lines B1a and B1b of the first unit circuit.

In this embodiment, the drain electrode of each DMX circuit TFT is a part of the source bus line SL, the source electrode is a part of the branch wiring B, and the gate electrode is a part of the control signal branch line C. Further, a common control signal branch line C is provided for two or more unit circuits. Thereby, the area required for the demultiplexer circuit DMX can be more effectively reduced. In addition, since the channel width W can be increased in the y direction, the current driving force can be ensured.

Furthermore, in this embodiment, since the plurality of unit circuits are arranged in a two-stage configuration, a DMX circuit TFT having a desired size can be formed even if the arrangement pitch of the source bus lines SL is narrowed. For example, in the above-described embodiment, it is necessary to dispose a DMX circuit TFT between two adjacent source bus lines SL. On the other hand, in the present embodiment, for example, a DMX circuit TFT may be disposed between the Nth source bus line SL and the (N + 2) th source bus line SL. Thus, a highly reliable DMX circuit TFT can be formed. Therefore, the present embodiment can be suitably applied to an ultra-high definition active matrix substrate exceeding 1000 ppi, for example. By forming the demultiplexer circuit DMX using an oxide semiconductor monolithically, the area of the wiring / terminal region in the non-display region can be reduced, so that a narrow frame can be realized.

Although an example of a two-stage configuration is shown here, a configuration of three or more stages can also be adopted. In this case as well, each sub-circuit may include three or more unit circuits, and the DMX circuit TFTs of these unit circuits may be arranged on the common control signal branch line with an interval.

In FIG. 16, a TFT having the same structure as that in FIG. 7A is used as the DMX circuit TFT, but the structure of the DMX circuit TFT is not limited to this.

17 and 18 are plan views showing parts of other sub-circuits 200B and 200C in the present embodiment, respectively.

In the sub circuit 200B shown in FIG. 17, thin film transistors T1a, T1b, T2a, and T2b having the same structure as the thin film transistor 10A shown in FIG. 2 are used as the DMX circuit TFTs.

Further, in the sub-circuit 200C shown in FIG. 18, thin film transistors T1a, T1b, T2a, and T2b having the same structure as the thin film transistor 10B having a symmetric structure (FIG. 3) are used as the DMX circuit TFTs. Although not shown, a TFT having the same structure as the thin film transistor 10C having an asymmetric structure (FIG. 4) may be used as the TFT for the DMX circuit.

<TFT parallel connection structure>
FIG. 19 is a plan view showing a part of a sub-circuit 200D in another demultiplexer circuit DMX in the present embodiment.

The sub circuit 200D is different from the sub circuit 200B shown in FIG. 17 in that a plurality of thin film transistors connected in parallel to one source bus line SL are provided.

In this example, a plurality of thin film transistors T1a connected in parallel to each other are connected to the first source bus line SL1, for example. The thin film transistors T1a are arranged in the y direction on the control signal branch line C1, and a part of the control signal branch line C1 is a gate electrode, a part of the branch wiring B1a is a source electrode, and the first source bus line SL1 A part is provided as a drain electrode. Similarly, a plurality of thin film transistors T2a, T1b, and T2b connected in parallel are connected to the other source bus lines SL1 to SL4, respectively. With such a configuration, the current driving capability can be further increased while suppressing an increase in circuit area.

Here, each thin film transistor has the same structure as the thin film transistor 10A, but may have another structure. For example, the thin film transistors 10B, 10C, and 10D may have the same structure as that shown in FIG.

The number of TFTs connected in parallel is not particularly limited, but can be set as appropriate so that the total channel width W of these TFTs becomes a predetermined value WTotal. However, the channel width W of each TFT (the length of the oxide semiconductor layer 7 in the channel width direction DW) is preferably 6 μm or more and 100 μm or less, for example. If the channel width W is 6 μm or less, desired characteristics may not be obtained. If the channel width W is larger than 100 μm, the TFT characteristics may not be stable. For example, when WTotal is 300 μm, three or more TFTs with W ≦ 100 μm may be connected in parallel. If Wt is 100 μm or less, one TFT having a large channel width W (W = WTotal) may be formed instead of connecting a plurality of TFTs in parallel.

<Double gate structure TFT>
Each DMX circuit TFT may have a gate electrode on the substrate side and the opposite side of the substrate of the oxide semiconductor layer (double gate structure).

20 to 22 are enlarged plan views showing parts of other sub-circuits 200E, 200F, and 200G in the demultiplexer circuit DMX of the present embodiment, respectively.

The sub-circuits 200E, 200F, and 200G are different from the sub-circuits 200A, 200B, and 200C illustrated in FIGS. 16 to 18 in that the thin film transistors T1a, T1b, T2a, and T2b further include the upper gate electrode BG (double gate structure). The detailed description of the double gate structure has been described above with reference to FIG.

As shown in the figure, when a plurality of thin film transistors arranged in parallel are arranged in the y direction, a common upper gate electrode BG may be provided for these thin film transistors. The common upper gate electrode BG may extend in the y direction.

The upper gate electrode BG of each thin film transistor may be connected to the video signal line DO (or V terminal) via the branch wiring B (that is, V terminal). Thereby, since the potential (back gate potential) Vbg of the upper gate electrode BG with respect to the source electrode 8 can be stabilized (Vbg = 0 V), the reliability can be improved. Further, the potential of the source bus line SL is changed to a high potential (for example, a potential for displaying the highest gradation) from the low potential (for example, a potential for displaying the lowest gradation) to the source bus line SL through the thin film transistor. When writing is performed, a positive bias is applied to the back gate electrode BG of the thin film transistor only in the initial charging stage of the source bus line SL. As a result, the threshold voltage of the DMX circuit TFT is effectively lowered, so that the driving force can be increased.

The contact portion 70 that connects the upper gate electrode BG to the branch wiring B is in a region us (hereinafter referred to as “connection region”) located between the first unit circuit formation region u1 and the second unit circuit formation region u2. It may be arranged. Thereby, an increase in the circuit area of the demultiplexer circuit DMX can be suppressed. In the contact portion 70, the upper gate electrode BG may be in direct contact with the branch wiring B in the opening formed in the inorganic insulating layer 11. Here, the contact portion 70 that connects the upper gate electrode BG and the branch wiring B in the thin film transistors T1a and T1b of the first unit circuit is disposed in the connection region us. Although not shown, a contact portion for connecting the upper gate electrode BG and the branch wiring B in the thin film transistors T2a and T2b of the second unit circuit is disposed between the second unit circuit formation region u2 and the control signal trunk line SW. May be. Alternatively, a contact portion that connects the upper gate electrode BG and the branch wiring B in the thin film transistors T2a and T2b of the second unit circuit is arranged in the connection region us, and branches from the upper gate electrode BG in the thin film transistors T1a and T1b of the first unit circuit. A contact portion for connecting the wiring B may be disposed between the first unit circuit formation region u1 and the display region DR.

<Other variations>
In the above description, the demultiplexer circuit DMX (n = 2) in which each unit circuit is associated with two source bus lines has been described as an example. However, the unit circuit of the demultiplexer circuit of this embodiment has three or more sources. It may be associated with a bus line.

FIG. 23 is a diagram showing a configuration of the sub-circuit 300 in another demultiplexer circuit of the present embodiment. In FIG. 23, the same components as those in FIG. 16 are denoted by the same reference numerals.

The sub circuit 300 includes a first unit circuit and a second unit circuit, similar to the sub circuit 200 described above. However, each unit circuit is different from the sub-circuit 200 shown in FIG. 16 in that each unit circuit distributes the video signal V1 from the video signal line DO (N) to the three source bus lines SL arranged every other line. .

The first unit circuit is associated with the first, third, and fifth source bus lines SL1, SL3, SL5 arranged every other line, and the second unit circuit is arranged every other line. The second, fourth, and sixth source bus lines SL2, SL4, and SL6 are associated with each other. The first unit circuit and the second unit circuit use common control signal branch lines C1, C2, and C3.

The first unit circuit includes three thin film transistors (DMX circuit TFTs) T1a, T1b, and Tc and three branch wirings B1a, B1b, and B1c. The second unit circuit includes three thin film transistors (DMX circuit TFTs) T2a, T2b, T2c, and three branch lines B2a, B2b, B2c. The branch wirings B1a, B1b, B1c of the first unit circuit are electrically connected to the video signal line DO1, and the branch wirings B2a, B2b, B2c of the second unit circuit are electrically connected to the video signal line DO2. Yes. The drain electrodes of the thin film transistors T1a, T1b, and T1c of the first unit circuit are connected to the first source bus line SL1, the third source bus line SL3, and the fifth source bus line SL5, respectively, and the source electrodes are respectively branched wirings. It is connected to B1a, B1b, B1c. The drain electrodes of the thin film transistors T2a, T2b, and T2c of the second unit circuit are connected to the second source bus line SL2, the fourth source bus line SL4, and the sixth source bus line SL6, respectively, and the source electrodes are respectively branched wirings. It is connected to B2a, B2b, B2c. The gate electrodes of the thin film transistors T1a and T2a are connected to the control signal trunk line SW1 via the control signal branch line C1, respectively. The gate electrodes of the thin film transistors T1b and T2b are respectively connected to the control signal trunk line SW2 via the control signal branch line C2. The gate electrodes of the thin film transistors T1c and T2c are connected to the control signal trunk line SW3 via the control signal branch line C3, respectively.

FIG. 24 is an enlarged plan view showing an example of the sub-circuit 300. Also in the sub circuit 300, the first unit circuit formation region u1 in which the thin film transistors T1a, T1b, and T1c of the first unit circuit are arranged is the thin film transistors T2a, T2b, It is located closer to the display area than the second unit circuit formation area u2 where T2c is arranged. The thin film transistor of the first unit circuit is disposed between the Nth and (N + 2) th source bus lines SL associated with the second unit circuit (N is a natural number). For example, the thin film transistor T1b is disposed between the second source bus line SL2 and the fourth source bus line SL4, and the thin film transistor T1c is disposed between the fourth source bus line SL4 and the sixth source bus line SL6. The thin film transistor of the second unit circuit is disposed between the branch wirings B of the first unit circuit. For example, the thin film transistor T2a is disposed between the branch line B1a and the branch line B1b, and the thin film transistor T2b is disposed between the branch line B1b and the branch line B1c.

Note that the structure of each thin film transistor is not limited to the structure shown in the drawings, and may have a structure similar to that of the thin film transistors 10B, 10C, and 10D.

<Phase development>
The control signal supplied by the control signal trunk line SW may be phase-expanded. Although the demultiplexer circuit DMX described above has n control signal trunk lines SW, K × n (K is an integer of 2 or more) control signal trunk lines SW may be provided.

FIG. 25 is a diagram illustrating a configuration of two sub-circuits 400 (1) and 400 (2) in the demultiplexer circuit DMX in which the control signal is phase-expanded. Each unit circuit is associated with two source bus lines SL (n = 2).

The sub-circuit 400 (1) includes a first unit circuit and a second unit circuit, and control signal branch lines C1 (1) and C2 (1). The sub-circuit 400 (2) includes a first unit circuit and a second unit circuit, and control signal branch lines C1 (2) and C2 (2).

In this example, the demultiplexer circuit DMX has four control signal trunk lines SW1-1, SW1-2, SW2-1, SW2-2 (K = 2). The same control signal is supplied to the control signal trunk lines SW1-1 and SW1-2, and the same control signal is supplied to the control signal trunk lines SW2-1 and SW2-2. Control signal branch lines C1 (1) and C2 (1) of some subcircuits (including subcircuit 400 (1)) of demultiplexer circuit DMX are control signal trunk line SW1-1 and control signal trunk line SW2-1 ( Control signal branch lines C1 (2) and C2 of some other subcircuits (including subcircuit 400 (2)) of the demultiplexer circuit DMX. (2) is connected to the control signal main line SW1-2 and the control signal main line SW2-2 (sometimes referred to as “second control signal main line”).

Thus, by performing phase expansion of the control signal of the control signal main line SW, the number of unit circuits connected to one control signal main line SW can be reduced, so that the load on each control signal main line SW can be reduced. As a result, since the transition time (rise and fall) of the control signal can be reduced, a higher speed operation is possible.

<Circuit TFT of Reference Example 2>
In the demultiplexer circuit DMX described above, a TFT having a top gate structure (top gate structure TFT) can also be used as a switching element. In the top gate structure TFT, a gate electrode is provided above the oxide semiconductor layer (on the side opposite to the substrate) through an insulating film.

FIGS. 26A and 26B are a plan view and a cross-sectional view illustrating the TFT (thin film transistor 90) of Reference Example 2 used in the demultiplexer circuit DMX, respectively.

The thin film transistor 90 is a top gate structure TFT. The thin film transistor 90 overlaps at least part of the oxide semiconductor layer 7 over the oxide semiconductor layer 7 provided over the substrate 1, the gate insulating layer 5 covering the oxide semiconductor layer 7, and the gate insulating layer 5. And a gate electrode 33 disposed on the surface.

Further, the inorganic insulating layer 11 is provided on the gate electrode 33 as an interlayer insulating layer. Furthermore, a source electrode 8 and a drain electrode 9 are provided on the inorganic insulating layer 11. The source electrode 8 and the drain electrode 9 are respectively connected to the source contact region 7s and the drain contact region 7d of the oxide semiconductor layer 7 in the opening provided so as to penetrate the inorganic insulating layer 11 and the gate insulating layer 5, respectively. Has been. Further, the source electrode 8 and the drain electrode 9 are provided away from the gate electrode 33 when viewed from the substrate normal direction.

The oxide semiconductor layer 7 includes a channel region 7 c that is a region overlapping with the gate electrode 33 when viewed from the normal direction of the substrate 1, a source contact region 7 s in contact with the source electrode 8, and a drain contact region in contact with the drain electrode 9. 7d. In the oxide semiconductor layer 7, a source-side offset region 7os located between the source contact region 7s and the channel region 7c, and a drain-side offset region 7od located between the drain contact region 7d and the channel region 7c. And are provided. The offset regions 7 os and 7 od are regions that do not overlap any of the gate electrode 33, the source electrode 8, and the drain electrode 9.

In the demultiplexer circuit DMX, the channel length direction DL of the thin film transistor 90 may be the same as the x direction and the channel width direction DW may be the same as the y direction. The drain electrode 9 of the thin film transistor 90 is a part of the corresponding source bus line SL, the source electrode 8 is a part of the corresponding branch wiring B, and the gate electrode 33 is one of the corresponding control signal branch lines C. Part. Although not shown, another gate electrode (lower gate electrode) may be further provided on the substrate 1 side of the oxide semiconductor layer 7. The lower gate electrode may be connected to the V terminal side via the branch wiring B.

(Third embodiment)
The active matrix substrate of the third embodiment has a gate driver formed monolithically.

The gate driver has one of the thin film transistors 10A to 10D described in the first embodiment. For example, among the plurality of circuit TFTs constituting the gate driver, the thin film transistors 10A to 10C are used as output transistors that require a large current to flow.

<Configuration and operation of monolithic gate driver>
-Circuit configuration of the gate driver First, the circuit configuration and operation of the gate driver GD formed monolithically on the active matrix substrate will be described. The gate driver GD includes a shift register. The shift register includes a plurality of unit shift register circuits connected in multiple stages.

FIG. 27 is a diagram illustrating a shift register circuit.

The shift register circuit has a plurality of unit shift register circuits SR1 to SRz (z: integer of 2 or more) (hereinafter collectively referred to as “unit shift register circuit SR”). The unit shift register SR of each stage includes a set terminal S that receives a set signal, an output terminal Z that outputs an output signal, a reset terminal R that receives a reset signal, and clock input terminals CK1 and CK2 that receive clock signals GCK1 and GCK2. It has. In the unit shift register circuit SRα (α ≧ 2), the output signal of the previous unit shift register circuit SR is input to the set terminal S. The gate start pulse signal GSP is input to the set terminal S of the first stage unit shift register circuit SR1. The unit shift register circuit SR at each stage also outputs an output signal to the corresponding gate bus line GL arranged in the display area. The reset terminal R receives an output signal of the next unit shift register circuit. A clear signal is input to the reset terminal R of the unit shift register circuit SRz at the final stage.

GCK1 and GCK2 which are two-phase clock signals are given to the two clock input terminals. The clock signal GCK1 is input to one of the clock input terminals, and the clock signal GCK2 is input to the other clock input terminal. The clock signal input to the clock input terminal is configured to be alternately switched between adjacent stages.

FIG. 28 is a diagram illustrating an example of the unit shift register circuit SR.

In this example, the unit shift register circuit SR includes four TFTs 31 to 34 and a capacitor part Cap.

TFT 31 is an input transistor. The gate and drain of the TFT 31 are connected to the set terminal, and the source of the TFT 31 is connected to the gate of the TFT 34. The TFT 34 is an output transistor. The drain of the TFT 34 is connected to the clock input terminal CK1, and the source is connected to the output terminal Z. In other words, the TFT 34 functions as a transmission gate to pass and block the clock signal input to the clock input terminal CK1.

The capacitor part Cap is connected between the gate and the source of the TFT 34 which is an output transistor. In this specification, the capacitor part Cap may be referred to as a “bootstrap capacitor part”. A node connected to the gate of the TFT 34 is referred to as “node netA”, and a node connected to the output terminal Z is referred to as “node Z”. One electrode of the capacitor part Cap is connected to the gate of the TFT 34 and the node netA, and the other electrode is connected to the source of the TFT 34 and the node Z.

The TFT 32 is disposed between the low power input terminal and the node netA. The TFT 32 is a pull-down transistor for reducing the potential of the node netA. The gate of the TFT 32 is connected to the reset terminal, the drain is connected to the node netA, and the source is connected to the low power input terminal.

A TFT 33 is connected to the node Z. The TFT 33 has a gate connected to the clock signal input terminal CK2, a drain connected to the node Z, and a source connected to the low power input terminal.

As described above, the unit shift register SR includes a pull-up unit 501 including the TFT 34 serving as an output transistor and a capacitor unit Cap, a pull-down unit 502 including the TFT 33, a pull-up driving unit 503 including the TFT 31 serving as an input transistor, And a pull-down driver 504 including the TFT 32.

In the present embodiment, among the TFTs 31 to 34, the above-described thin film transistors 10A to 10D are used as at least the TFTs 34 that are output transistors.

Usually, a TFT having a larger size than other TFTs is used as an output transistor for charging and discharging the gate bus line GL. For this reason, there is a problem that the load of the wiring that supplies the gate clock signals GCK1 and GCK2 to which the plurality of output transistors are connected increases, and the driving power increases. In contrast, in the present embodiment, since the thin film transistor having a structure with reduced parasitic capacitance is used as the output transistor, the load on the wiring can be reduced.

Note that the present embodiment is not limited to the shift register described above, and can be applied to various known shift registers.

The embodiment of the present invention can be suitably applied to an active matrix substrate having a peripheral circuit formed monolithically. Such active matrix substrates include liquid crystal display devices, display devices such as organic electroluminescence (EL) display devices and inorganic electroluminescence display devices, imaging devices such as image sensor devices, image input devices, fingerprint readers, and semiconductors. It is applied to various electronic devices such as a memory.

1: substrate 3: gate electrodes 3e1, 3e2: gate electrode edge 5: gate insulating layer 7: oxide semiconductor layer 7c: channel region 7d: drain contact region 7s: source contact region 7off: offset region 8: source electrode 8e1 8e2: Source edges 9e1, 9e2: Drain electrodes 10A to 10D: Thin film transistors (circuit TFTs)
11: Inorganic insulating layer BG: Upper gate electrode BGe1, BGe2: Upper gate electrode edge 70: Contact portion 82: Source electrode protrusion 84: Source electrode recess 86: Source electrode notch 92: Drain electrode Convex part 94: Concave part 96 of drain electrode: Notch part 100 of drain electrode: SSD unit circuit 200, 200A to 200G, 300, 400: Sub circuit 1000: Active matrix substrate DL: Channel length direction DW: Channel width direction DR: Display area FR: Non-display area GD: Gate driver SD: Source driver PIX: Pixel area PE: Pixel electrode GL: Gate bus line SL: Source bus lines B, B B3: Branch wiring C, C1-C3: Control signal branch line DO: Video signal line SW, SW1 to SW3: Control signal trunk line SR: Unit shift register circuit T1a, T1b, T1c, T2a, T2b, T2c: Thin film transistor V: Output terminal u1: First unit circuit formation region u2: Second unit circuit formation region us: Connection region

Claims (21)

1. A display area including a plurality of pixels and a non-display area provided around the display area;
   An active matrix substrate comprising a substrate, at least one TFT supported by the substrate and disposed in the non-display area, and a peripheral circuit including the at least one TFT,
   The at least one TFT comprises:
   A gate electrode;
   A gate insulating layer covering the gate electrode;
   An oxide semiconductor layer disposed on the gate insulating layer so as to at least partially overlap the gate electrode with the gate insulating layer interposed therebetween;
   A source electrode disposed on the oxide semiconductor layer so as to be in contact with a part of the oxide semiconductor layer;
   A drain electrode disposed on the oxide semiconductor layer so as to be in contact with another part of the oxide semiconductor layer;
   When viewed from the normal direction of the substrate, the gate electrode has a first edge and a second edge facing each other, and the first edge and the second edge are the at least one TFT. Extending across the oxide semiconductor layer in the channel width direction of
   When viewed from the normal direction of the substrate, the source electrode extends across the oxide semiconductor layer in the channel width direction so as to overlap the first edge of the gate electrode, and the drain electrode Is an active matrix substrate extending across the oxide semiconductor layer in the channel width direction so as to overlap the second edge of the gate electrode.
2. When viewed from the normal direction of the substrate, the source edge of the source electrode facing the drain electrode and / or the drain edge of the drain electrode facing the source electrode are formed with the oxide semiconductor layer. In the overlapping region, it has at least one protrusion protruding in the channel length direction of the at least one TFT, and a recess or notch adjacent to the at least one protrusion in the channel width direction,
   2. The active matrix substrate according to claim 1, wherein a length of the at least one convex portion in the channel length direction is less than 1/3 of a width of the gate electrode in the channel length direction.
3. The total width in the channel width direction of the at least one protrusion disposed at the source edge or the drain edge is not less than 70% and not more than 90% of the channel width W of the at least one TFT. Item 3. The active matrix substrate according to Item 2.
4. Each of the source edge and the drain edge has the at least one protrusion and the recess or the notch,
   At least one protrusion of the source edge is opposed to at least one protrusion of the drain edge in the channel length direction;
   4. The active matrix substrate according to claim 2, wherein the recess or the notch of the source edge is opposed to the recess or the notch of the drain edge in the channel length direction. 5.
5. Each of the source edge and the drain edge has the at least one protrusion and the recess or the notch,
   At least one protrusion of the source edge is opposed to the recess or notch of the drain edge in the channel length direction;
   4. The active matrix substrate according to claim 2, wherein the concave portion or the notch portion of the source edge portion opposes at least one convex portion of the drain edge portion in the channel length direction. 5.
6. In the display region, further comprising a plurality of source bus lines extending in the channel width direction and a plurality of gate bus lines extending in the channel length direction of the at least one TFT,
   The peripheral circuit is a demultiplexer circuit including a plurality of unit circuits, and each of the plurality of unit circuits is connected to one of the plurality of source signal lines from one video signal line. distributing video signals to n source bus lines (n is an integer of 2 or more);
   6. Each of the plurality of unit circuits includes at least n DMX circuit TFTs, and the at least one TFT includes the at least n DMX circuit TFTs. Active matrix substrate.
7. The demultiplexer circuit further comprises a plurality of control signal trunks,
   Each of the plurality of unit circuits further includes n branch wirings connected to the one video signal line, the n source bus lines, and n control signal branch lines.
   Each of the plurality of control signal branch lines is electrically connected to one of the plurality of control signal trunk lines,
   In each of the plurality of unit circuits, the drain electrode of each DMX circuit TFT is a part of one of the n source bus lines, and the source electrode is a part of one of the n branch lines, A gate electrode is a part of the n control signal branches;
   In each of the plurality of unit circuits, the n branch wirings, the n control signal branch lines, and the n source bus lines all extend in the channel width direction. The active matrix substrate as described.
8. The demultiplexer circuit includes a plurality of sub-circuits,
   Each sub-circuit includes at least a first unit circuit and a second unit circuit among the plurality of unit circuits,
   The active matrix substrate according to claim 7, wherein in each of the sub-circuits, the n control signal branch lines in the first unit circuit and the second unit circuit are common.
9. In each of the sub-circuits, the first unit circuit formation region in which the at least n DMX circuit TFTs of the first unit circuit are formed includes the at least n DMX circuit TFTs of the second unit circuit. The active matrix substrate according to claim 8, wherein the active matrix substrate is located between the second unit circuit forming region and the display region.
10. In each of the sub-circuits, one of the at least n DMX circuit TFTs in the first unit circuit and one of the at least n DMX circuit TFTs in the second unit circuit are the same control signal branch line. 10. The active matrix substrate according to claim 8, wherein the active matrix substrate is connected to the same control signal branch line and spaced apart from each other.
11. The plurality of source bus lines are arranged in the channel length direction from one end, and each of the sub-circuits is Nth (N is a natural number), (N + 1) th, (N + 2) th from the one end. And a (N + 3) th array of a first source bus line, a second source bus line, a third source bus line, and a fourth source bus line,
    The first source bus line and the third source bus line are electrically connected to one of the plurality of video signal lines through the first unit circuit,
    11. The device according to claim 8, wherein the second source bus line and the fourth source bus line are electrically connected to the other one of the plurality of video signal lines through the second unit circuit. An active matrix substrate according to any one of the above.
12. In each of the sub-circuits, when viewed from the normal direction of the substrate, one of the at least n DMX circuit TFTs of the first unit circuit includes the second source bus line and the fourth source bus line. The active matrix substrate according to claim 11, which is disposed between the two.
13. 13. The active matrix substrate according to claim 7, wherein the at least n DMX circuit TFTs include a plurality of TFTs arranged in the channel width direction and connected in parallel to each other.
14. The plurality of control signal trunk lines include n first control signal trunk lines and n second control signal trunk lines, and each of the n first control signal trunk lines includes the n second control signal trunk lines. The same control signal as one of the control signal trunks is supplied,
    The n control signal branch lines in some unit circuits among the plurality of unit circuits are electrically connected to the n first control signal trunk lines, and the other unit circuit includes the unit control circuit branch lines. 14. The active matrix substrate according to claim 7, wherein n control signal branch lines are electrically connected to the n second control signal trunk lines.
15. The peripheral circuit includes a gate driver,
    The gate driver has a plurality of shift registers,
    The active matrix substrate according to claim 1, wherein the at least one TFT includes an output transistor in each of the plurality of shift registers.
16. A display area including a plurality of pixels and a non-display area provided around the display area;
    A substrate,
    A demultiplexer circuit disposed in the non-display area and supported by the substrate;
    A plurality of source bus lines extending in a first direction in the display region;
    A plurality of gate bus lines extending in a second direction intersecting the first direction,
    The demultiplexer circuit includes a plurality of unit circuits and a plurality of control signal trunk lines.
    Each of the plurality of unit circuits transmits a video signal from one video signal line of the plurality of video signal lines to n (n is an integer of 2 or more) source bus lines of the plurality of source bus lines. Distribute
    Each of the plurality of unit circuits includes at least n DMX circuit TFTs, n branch wirings connected to the one video signal line, the n source bus lines, and n control signals. Each of the n control signal branch lines is electrically connected to one of the plurality of control signal trunk lines,
    In each of the plurality of unit circuits, the n branch wirings, the n control signal branch lines, and the n source bus lines all extend in the first direction,
    Each TFT for DMX circuit is in contact with a part of the oxide semiconductor layer on the gate electrode, the oxide semiconductor layer disposed on the gate electrode through a gate insulating layer, and the oxide semiconductor layer A source electrode disposed on the oxide semiconductor layer, and a drain electrode disposed on the oxide semiconductor layer so as to be in contact with another part of the oxide semiconductor layer,
    The drain electrode is a part of one of the n source bus lines, the source electrode is a part of one of the n branch lines, and the gate electrode is a part of the n control signal branch lines. Part of one,
    When viewed from the normal direction of the substrate, the gate electrode has a first edge and a second edge facing each other, and the first edge and the second edge are formed of the oxide semiconductor layer. Extending across the first direction,
    When viewed from the normal direction of the substrate, the source electrode extends in the first direction so as to overlap the first edge, and the drain electrode overlaps the second edge. An active matrix substrate extending in one direction.
17. The plurality of unit circuits include a first unit circuit and a second unit circuit,
    In the display area, the plurality of source bus lines are arranged in the second direction from one end, and are Nth (N is a natural number), (N + 1) th, (N + 2) th from the one end, and A first source bus line, a second source bus line, a third source bus line, and a fourth source bus line arranged in the (N + 3) th,
    The first source bus line and the third source bus line are electrically connected to one of the plurality of video signal lines through the first unit circuit,
    The second source bus line and the fourth source bus line are electrically connected to the other one of the plurality of video signal lines through the second unit circuit,
    When viewed from the normal direction of the substrate, one of the at least n DMX circuit TFTs of the first unit circuit is disposed between the second source bus line and the fourth source bus line. The active matrix substrate according to claim 16.
18. The n control signal branch lines in the first unit circuit and the second unit circuit are common,
    One of the at least n DMX circuit TFTs in the first unit circuit and one of the at least n DMX circuit TFTs in the second unit circuit are connected to the same control signal line, and The active matrix substrate according to claim 17, wherein the active matrix substrate is disposed on the same control signal line with a space therebetween.
19. In each of the DMX circuit TFTs, when viewed from the normal direction of the substrate, the source edge of the source electrode facing the drain electrode and / or the drain edge of the drain electrode facing the source electrode Has at least one protrusion protruding in the second direction in a region overlapping with the oxide semiconductor layer, and a recess or notch adjacent to the at least one protrusion in the first direction,
    19. The active matrix substrate according to claim 17, wherein a length of the at least one protrusion in the second direction is less than 1/3 of a width of the gate electrode in the second direction.
20. The active matrix substrate according to claim 1, wherein the oxide semiconductor layer includes an In—Ga—Zn—O-based semiconductor.
21. 21. The active matrix substrate according to claim 20, wherein the In—Ga—Zn—O based semiconductor includes a crystalline portion.

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