KR102309846B1 - Display Device - Google Patents

Abstract

The present invention provides a display device including a display panel and a driving unit. The display panel includes sub-pixels having thin film transistors formed at intersections of data lines and gate lines. The driving unit drives the display panel. In the sub-pixels, the data metal constituting the data line and the first region of the oxide semiconductor layer constituting the thin film transistor are indirectly contacted by the lower electrode.

Description

Display Device

The present invention relates to a display device.

As information technology develops, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

In general, a display panel used in a liquid crystal display device or an organic light emitting display device is implemented as a thin film transistor having a silicon-based, organic semiconductor-based, or oxide-based semiconductor layer. A thin film transistor used to implement a display panel is largely classified into a coplanar structure and a staggered structure according to materials and process methods (position and shape of electrodes, etc.). The reverse staggered structure, which is one of the staggered structures, includes a Back Channel Etched (BCE) structure and an Etch Stopper (ES) structure.

However, in the case of the conventionally proposed back-channel etch transistor structure, as ions of the source-drain electrode material are diffused into the oxide semiconductor layer, there is a problem in that the characteristics of the device are deteriorated or deteriorated, so improvement thereof is required.

SUMMARY OF THE INVENTION The present invention for solving the problems of the above-described background technology is to provide a display device implemented with a transistor capable of improving the problem of deterioration or deterioration of device characteristics.

As a means for solving the above problems, the present invention provides a display device including a display panel and a driving unit. The display panel includes sub-pixels having thin film transistors formed at intersections of data lines and gate lines. The driving unit drives the display panel. In the sub-pixels, the data metal constituting the data line and the first region of the oxide semiconductor layer constituting the thin film transistor are indirectly contacted by the lower electrode.

The data metal and the oxide semiconductor layer may be formed on the same insulating layer, and the lower electrode may be formed on the insulating layer covering the data metal and the oxide semiconductor layer.

The lower electrode may include a first lower electrode electrically connecting the data metal and the first region of the oxide semiconductor layer, and a second lower electrode electrically connecting the second region of the oxide semiconductor layer and the upper electrode. can

A first region of the oxide semiconductor layer may be connected to the lower electrode, and a second region of the oxide semiconductor layer may be connected to an upper electrode formed on an insulating layer covering the lower electrode.

The upper electrode may be connected to the second region of the oxide semiconductor layer and extend into the opening region of the sub-pixel.

The sub-pixels include a gate metal formed on a lower substrate, a first insulating layer formed on the lower substrate and covering the gate metal, and the oxide semiconductor formed on the first insulating layer and formed in a region overlapping the gate metal. a layer; the data metal formed on the first insulating layer and spaced apart from the oxide semiconductor layer by a predetermined distance; a second insulating layer formed on the first insulating layer and covering the oxide semiconductor layer and the data metal; a third insulating layer formed on the second insulating layer and having first and second contact holes exposing the data metal and the first and second regions of the oxide semiconductor layer; Each of the first lower electrodes electrically connecting the first region of the oxide semiconductor layer may be included.

Each of the sub-pixels may further include a second lower electrode formed on the third insulating layer and connected to the second region of the oxide semiconductor layer.

The sub-pixels are formed on the third insulating layer and include a fourth insulating layer covering the first lower electrode and having a third contact hole exposing a second region of the oxide semiconductor layer; Each of the upper electrodes connected to the second region of the oxide semiconductor layer may be further included.

In another aspect, the present invention provides a display device including a display panel and a driving unit. The display panel includes sub-pixels having thin film transistors formed at intersections of data lines and gate lines. The driving unit drives the display panel. In the sub-pixels, the metallized semiconductor layer positioned on the data metal constituting the data line and the first region of the oxide semiconductor layer constituting the thin film transistor are indirectly contacted by the lower electrode.

The oxide semiconductor layer may have a shape in which the source region and the drain region are larger than the channel region.

The sub-pixels include a gate metal formed on the lower substrate, a first insulating film formed on the lower substrate and covering the gate metal, a data metal formed on the first insulating film, and a region formed on the first insulating film and overlapping the gate metal. an oxide semiconductor layer formed in a first direction, a metallized semiconductor layer formed on the data metal and spaced apart from the oxide semiconductor layer in a second direction intersecting the first direction, and an oxide semiconductor layer formed on the first insulating film , a second insulating layer covering the metallized semiconductor layer and the data metal, a first contact hole formed on the second insulating layer and exposing the metallized semiconductor layer, and a second contact hole exposing a first region of the oxide semiconductor layer and a first lower electrode formed on the third insulating layer and electrically connecting the metallized semiconductor layer and the first region of the oxide semiconductor layer.

The sub-pixels include a second lower electrode formed on the third insulating film and connected to the common voltage line, and a third contact formed on the third insulating film and covering the first and second lower electrodes and exposing the second region of the oxide semiconductor layer. It may further include a fourth insulating layer having a hole, and an upper electrode formed on the fourth insulating layer and connected to the second region of the oxide semiconductor layer, respectively.

The present invention has the effect of providing a display device implemented with a transistor capable of improving the problem of deterioration or deterioration of device characteristics. In addition, the present invention has the effect of improving the aperture ratio of the display panel by changing the structure of the electrodes constituting the transistor.

1 is a block diagram schematically showing a display device;
FIG. 2 is a configuration diagram schematically illustrating a sub-pixel shown in FIG. 1;
FIG. 3 is a diagram schematically illustrating a plan view of the display panel shown in FIG. 1 ;
4 is a cross-sectional view of a structure of a conventionally proposed back-channel etched transistor;
FIG. 5 is a view for explaining a problem caused when a contact between an oxide semiconductor layer and a source-drain electrode in the structure of FIG. 4;
6 to 11 are plan views illustrating a process flow diagram of a display device according to a first embodiment of the present invention.
12 is a cross-sectional view illustrating areas A1-A2 of FIG. 11;
13 to 18 are plan views illustrating a process flow diagram of a display device according to a second exemplary embodiment of the present invention.
19 is a cross-sectional view illustrating a region B1-B2 of FIG. 18;
20 is a cross-sectional view of a display device according to a third embodiment of the present invention;
21 is a cross-sectional view of a display device according to a fourth embodiment of the present invention;
22 to 29 are plan views illustrating a process flow diagram of a display device according to a fifth embodiment of the present invention.
30 is a cross-sectional view illustrating a region B1-B2 of FIG. 29;
31 is a view for explaining the advantages of a dumbbell-shaped semiconductor layer.
32 is another exemplary view of a semiconductor layer in the form of a dumbbell.

Hereinafter, specific details for carrying out the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically illustrating a display device, FIG. 2 is a configuration diagram schematically illustrating a sub-pixel illustrated in FIG. 1 , and FIG. 3 is a diagram schematically illustrating a plan view of the display panel illustrated in FIG. 1 .

As shown in FIG. 1 , the display device includes an image supply unit 110 , a timing control unit 120 , a gate driving unit 130 , a data driving unit 140 , and a display panel 150 .

The image supply unit 110 image-processes the data signal and outputs it together with a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The image supply unit 110 supplies a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, and a data signal to the timing control unit 120 .

The timing control unit 120 receives a data signal from the image supply unit 110 , and controls the gate timing control signal GDC for controlling the operation timing of the gate driver 130 and the operation timing of the data driver 140 . A data timing control signal DDC for The timing controller 120 supplies the data signal DATA together with the data timing control signal DDC to the data driver 140 .

The gate driver 130 outputs a gate signal (or a scan signal) while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 120 . The gate driver 130 includes a level shifter and a shift register. The gate driver 130 supplies a gate signal to the sub-pixels SP included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 is formed in the form of an integrated circuit (IC) or is formed in the display panel 150 in the form of a gate in panel. A portion of the gate driver 130 formed in a gate-in-panel method is a shift register.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 , and converts the analog signal into a digital signal in response to the gamma reference voltage and outputs it . The data driver 140 supplies the data signal DATA to the sub-pixels SP included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 is formed in the form of an integrated circuit (IC).

The display panel 150 displays an image corresponding to the gate signal supplied from the gate driver 130 and the data signal DATA supplied from the data driver 140 . The display panel 150 includes sub-pixels SP that emit light by itself or control external light to display an image.

As shown in FIG. 2 , one sub-pixel is supplied through the switching thin film transistor SW and the switching thin film transistor SW connected to (or formed at the intersection of) the gate line GL1 and the data line DL1. A pixel circuit PC operating in response to the data signal DATA is included. The sub-pixels SP are composed of a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 150 is configured as a liquid crystal display panel, it is a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS (Fringe Field Switching) mode, or ECB (Electrically Controlled Birefringence) mode. implemented in mode. When the display panel 150 is configured as an organic light emitting display panel, it is implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

As shown in FIG. 3 , a display area AA, gate drivers 130a and 130b, data driver 140 , and signal pads 180 are formed in the display panel 150 . Since the image supply unit 110 and the timing control unit 120 described with reference to FIG. 1 are formed on an external substrate, they are not shown.

The display area AA includes sub-pixels SP. In addition, a bezel area that becomes the non-display areas NAx, NAy1, and NAy2 is defined in an external area except for the display area AA. The first and second non-display areas NAy1 and NAy2 are defined as side bezel areas, and the third non-display area NAx is defined as a lower bezel area (this is sometimes defined as an upper bezel area depending on the viewing direction, but in the present invention, the lower bezel area). bezel area).

The gate drivers 130a and 130b are formed in a side bezel area of the display panel 150 or on an external substrate. When the gate drivers 130a and 130b are formed in a gate-in-panel method, they are formed in the first and second non-display areas NAy1 and NAy2 that are left and right of the display area AA as shown in the drawing. is formed In this case, the gate drivers 130a and 130b are formed in the first and second non-display areas NAy1 and NAy2 or only in one of the non-display areas NAy1 or NAy2 according to the resolution or size of the display panel 150 . can be formed.

The signal pads 180 are formed at the outermost portion of the display panel 150 . The signal pads 180 are composed of a plurality of pads, which are formed in an outermost part located in the third non-display area NAx or the first and second pads according to the resolution or size of the display panel 150 . The second non-display area NAy1 and NAy2 may be formed in one of the outermost portions.

In general, the timing control unit 120 as well as the power supply unit are mounted on an external board (eg, a printed circuit board) in the form of an integrated circuit. Accordingly, the signal pads 180 become parts connected to the external substrate on which the timing controller 120 is formed, and serve to transmit and supply various signals or power output from the external substrate to the display panel 150 . .

The data driver 140 may be formed in the third non-display area NAx positioned between the signal pads 180 formed on the display panel 150 and the display area AA. In this case, the data driver 140 is configured in the form of an integrated circuit and is mounted on bump pads formed on the display panel 150 . However, when the resolution or size of the display panel 150 is large, the data driver 140 is not formed in the third non-display area NAx but is mounted on the external substrate.

Meanwhile, the display panel 150 used in a liquid crystal display device or an organic light emitting display device is implemented as a thin film transistor having a silicon-based, organic semiconductor-based, or oxide-based semiconductor layer.

The thin film transistor used to implement the display panel 150 is largely classified into a coplanar structure and a staggered structure according to a material and a process method (position and shape of an electrode, etc.). The reverse staggered structure, which is one of the staggered structures, includes a Back Channel Etched (BCE) structure and an Etch Stopper (ES) structure. A thin film transistor having a coplanar structure and a staggered structure is used in at least one of the display panel 150 and the gate drivers 130a and 130b.

However, in the case of the conventionally proposed back-channel etch transistor structure, as ions of the source-drain electrode material are diffused into the oxide semiconductor layer, there is a problem in that the characteristics of the device are deteriorated or deteriorated, so improvement thereof is required.

In the present invention, the contact structure between the oxide semiconductor layer and the source and drain electrodes is changed in order to solve the above-mentioned problem. Hereinafter, the conventional structure and the embodiment of the present invention will be compared and described for better understanding.

-Conventional structure-

FIG. 4 is a cross-sectional view of a conventionally proposed structure of a back channel etched transistor, and FIG. 5 is a view for explaining a problem caused when the oxide semiconductor layer and the source and drain electrodes contact each other in the structure of FIG. 4 .

4 and 5, on the lower substrate 150a, the gate electrode 151, the first insulating layer 152, the semiconductor layer 153, the source electrode 154a, the drain electrode 154b, and the second An insulating layer 155 , a third insulating layer 156 , a common electrode 157 , a fourth insulating layer 158 , and a pixel electrode 159 are stacked.

The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO). In addition, the source and drain electrodes 154a and 154b in direct contact with the semiconductor layer 153 are made of a heterogeneous multilayer metal such as Cu/MoTi. For example, the first layer 154a1 of the source electrode 154a is made of molybdenum titanium (MoTi), and the second layer 154a2 is made of copper (Cu).

The conventionally proposed structure of the back-channel etched transistor has an advantage in that copper (Cu) is included in the material of the source and drain electrodes 154a and 154b, so that the RC delay caused by the resistor and the capacitor is reduced.

However, in the conventionally proposed back-channel etch transistor structure, as copper ions contained in the material of the source and drain electrodes 154a and 154b diffuse into the oxide semiconductor layer, the characteristics of the device are deteriorated or deteriorated. there was a problem with

Hereinafter, an embodiment of a structure capable of improving the problems of the conventionally proposed back-channel etched transistor structure will be described, but an example in which the improved structure is applied to a liquid crystal display device will be described.

<First embodiment>

6 to 11 are plan views illustrating a process flow diagram of a display device according to a first embodiment of the present invention, and FIG. 12 is a cross-sectional view illustrating areas A1 - A2 of FIG. 11 .

As shown in FIG. 6 , a gate metal (or gate electrode) 151 is formed on the lower substrate (not shown due to the characteristics of the planar structure). The gate metal 151 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The gate metal 151 is formed in the first direction (horizontal direction in the drawing). The gate metal 151 is defined as a gate wiring or a gate electrode depending on the region.

A first insulating layer 152 is formed on the gate metal 151 . The first insulating layer 152 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 152 may be defined as a gate insulating layer.

A semiconductor layer 153 is formed on the first insulating layer 152 . The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO), TiO2, ZnO, WO3, SnO2, or the like. The semiconductor layer 153 is formed to overlap the gate electrode 151 .

As shown in FIG. 7 , a data metal 160 is formed on the first insulating layer 152 . The data metal 160 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof and may be formed of a single layer or multiple layers. The data metal 160 is formed in the second direction (vertical direction in the drawing). The data metal 160 is formed on the first insulating layer 152 in the same manner as the semiconductor layer 153 , and is formed to be spaced apart from the semiconductor layer 153 by a predetermined interval. The data metal 160 is defined as a data line.

As shown in FIG. 8 , a second insulating layer 155 is formed on the semiconductor layer 153 and the data metal 160 . The second insulating layer 155 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The second insulating layer 155 may be defined as a first passivation layer.

A third insulating layer 156 is formed on the second insulating layer 155 . The third insulating layer 156 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The third insulating layer 156 may be defined as a planarization layer for planarizing a surface.

The second insulating layer 155 and the third insulating layer 156 include a first contact hole CH1 exposing the data metal 160 . In addition, the third insulating layer 156 includes a second contact hole CH2 exposing the first region and the second region (hereinafter referred to as a source region and a drain region) of the semiconductor layer 153 . Meanwhile, the source region and the drain region of the semiconductor layer 153 exposed through the second contact hole CH2 of the third insulating layer 156 are metallized by dry etching or a heat treatment method. The resistance of the source region and the drain region of the semiconductor layer 153 metallized by dry etching or the like is reduced (a contact resistance with other metals may be reduced).

As shown in FIG. 9 , lower electrodes 157a , 157b , and 157c (hereinafter referred to as lower transparent electrodes) are formed on the third insulating layer 156 . The lower transparent electrodes 157a, 157b, and 157c may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The lower transparent electrodes 157a, 157b, and 157c are connected to (or in contact with) the source region of the data metal 160 and the semiconductor layer 153 , and are formed in the drain region of the semiconductor layer 153 . It is divided (or separated) into a second lower transparent electrode 157b connected to and a third lower transparent electrode 157c connected to the common voltage line. The first lower transparent electrode 157a is defined as a source electrode, the second lower transparent electrode 157b is defined as a drain electrode, and the third lower transparent electrode 157c is defined as a common electrode.

As shown in FIG. 10 , a fourth insulating layer 158 is formed on the lower transparent electrodes 157a, 157b, and 157c. The fourth insulating layer 158 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The fourth insulating layer 158 may be defined as a second passivation layer. The fourth insulating layer 158 includes a third contact hole CH3 exposing the second lower transparent electrode 157b connected to the drain region of the semiconductor layer 153 .

11 , an upper electrode 159 (hereinafter referred to as an upper transparent electrode) is formed on the fourth insulating layer 158 . The upper transparent electrode 159 may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper transparent electrode 159 is connected to the drain region of the semiconductor layer 153 through the second lower transparent electrode 157b. The upper transparent electrode 159 is defined as a pixel electrode.

The upper transparent electrode 159 may have a finger shape separated into a plurality of openings (or transmission regions) formed at the intersection of the gate metal 151 and the data metal 160 . The upper transparent electrode 159 may have a shape of an inequality sign (<) inclined with respect to the central region of the opening region (or the transmissive region), but is not limited thereto. When the upper transparent electrode 159 has an inequality sign (<) shape, the data metal 160 may also include a region having an inequality sign (<) shape like the shape of the upper transparent electrode 159 .

Through the above process, a plurality of sub-pixels including a switching thin film transistor, a storage capacitor, a common electrode, and a pixel electrode are formed on the lower substrate. Although not shown, thereafter, a lower alignment layer, a liquid crystal layer, an upper alignment layer, and an upper substrate are positioned on the upper transparent electrode 159 .

12, on the lower substrate 150a, the gate electrode 151, the first insulating layer 152, the semiconductor layer 153, the second insulating layer 155, the third insulating layer 156, and the lower transparent electrode (157a to 157c), a fourth insulating layer 158 and an upper transparent electrode 159 are stacked.

The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO). In addition, the data metal 160 spaced apart from the semiconductor layer 153 is made of a heterogeneous multi-layer metal such as Cu/MoTi. For example, the first layer of the data metal 160 is made of molybdenum titanium (MoTi), and the second layer is made of copper (Cu).

For this reason, in the structure of the back channel etched transistor according to the first embodiment of the present invention, copper (Cu) is included in the material of the data metal 160, so that the RC delay caused by the resistor and the capacitor is reduced.

On the other hand, as mentioned above, the conventionally proposed back channel etch transistor structure has a problem in that the characteristics of the device are deteriorated or deteriorated as copper ions contained in the material of the source and drain electrodes diffuse into the oxide semiconductor layer.

However, in the structure of the back channel etched transistor according to the first embodiment of the present invention, the data metal 160 and the semiconductor layer 153 do not directly contact, but indirectly contact by the first lower transparent electrode 157a. In addition, the data metal 160 including copper (Cu) and the semiconductor layer 153 of IGZO are isolated from each other by the second insulating layer 155 covering them. As a result, since the diffusion (diffusion) of copper ions of the data metal 160 into the oxide semiconductor layer is prevented (or suppressed), the problem of deterioration or degradation of device characteristics is solved.

<Second embodiment>

13 to 18 are plan views illustrating a process flow diagram of a display device according to a second exemplary embodiment of the present invention, and FIG. 19 is a cross-sectional view illustrating a region B1-B2 of FIG. 18 .

As shown in FIG. 13 , a gate metal (or gate electrode) 151 is formed on the lower substrate (not shown due to the characteristics of the planar structure). The gate metal 151 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The gate metal 151 is formed in the first direction (horizontal direction in the drawing). The gate metal 151 is defined as a gate wiring or a gate electrode depending on the region.

A first insulating layer 152 is formed on the gate metal 151 . The first insulating layer 152 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 152 may be defined as a gate insulating layer.

A semiconductor layer 153 is formed on the first insulating layer 152 . The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO), TiO2, ZnO, WO3, SnO2, or the like. The semiconductor layer 153 is formed to overlap the gate electrode 151 .

As shown in FIG. 14 , a data metal 160 is formed on the first insulating layer 152 . The data metal 160 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof and may be formed of a single layer or multiple layers. The data metal 160 is formed in the second direction (vertical direction in the drawing). The data metal 160 is formed on the first insulating layer 152 in the same manner as the semiconductor layer 153 , and is formed to be spaced apart from the semiconductor layer 153 by a predetermined interval. The data metal 160 is defined as a data line.

15 , a second insulating layer 155 is formed on the semiconductor layer 153 and the data metal 160 . The second insulating layer 155 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The second insulating layer 155 may be defined as a first passivation layer.

A third insulating layer 156 is formed on the second insulating layer 155 . The third insulating layer 156 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The third insulating layer 156 may be defined as a planarization layer for planarizing a surface.

The second insulating layer 155 and the third insulating layer 156 include a first contact hole CH1 exposing the data metal 160 . In addition, the third insulating layer 156 includes a second contact hole CH2 exposing the source region and the drain region of the semiconductor layer 153 . Meanwhile, the source region and the drain region of the semiconductor layer 153 exposed through the second contact hole CH2 of the third insulating layer 156 are metallized by dry etching or a heat treatment method. The resistance of the source region and the drain region of the semiconductor layer 153 metallized by dry etching or the like is reduced (a contact resistance with other metals may be reduced).

As shown in FIG. 16 , lower transparent electrodes 157a and 157c are formed on the third insulating layer 156 . The lower transparent electrodes 157a and 157c may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The lower transparent electrodes 157a and 157c are the first lower transparent electrode 157a connected to (or in contact with) the source region of the data metal 160 and the semiconductor layer 153 and the third lower transparent electrode connected to the common voltage line. (157c) is distinguished (or separated). The first lower transparent electrode 157a is defined as a source electrode, and the third lower transparent electrode 157c is defined as a common electrode.

17 , a fourth insulating layer 158 is formed on the lower transparent electrodes 157a and 157c. The fourth insulating layer 158 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The fourth insulating layer 158 may be defined as a second passivation layer. The fourth insulating layer 158 includes a third contact hole CH3 exposing the drain region of the semiconductor layer 153 . The third contact hole CH3 is located in a region overlapping the gate metal 151 .

18 , an upper transparent electrode 159 is formed on the fourth insulating layer 158 . The upper transparent electrode 159 may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper transparent electrode 159 is connected to the drain region of the semiconductor layer 153 through the fourth insulating layer 158 . The upper transparent electrode 159 serves as a drain electrode and is also defined as a pixel electrode. That is, the first embodiment has a structure in which the drain electrode and the pixel electrode are separated, but the second embodiment has a structure in which the drain electrode and the pixel electrode are integrated into one.

The upper transparent electrode 159 may have a finger shape separated into a plurality of openings (or transmission regions) formed at the intersection of the gate metal 151 and the data metal 160 . The upper transparent electrode 159 may have a shape of an inequality sign (<) inclined with respect to the central region of the opening region (or the transmissive region), but is not limited thereto. When the upper transparent electrode 159 has an inequality sign (<) shape, the data metal 160 may also include a region having an inequality sign (<) shape like the shape of the upper transparent electrode 159 .

Through the above process, a plurality of sub-pixels including a switching thin film transistor, a storage capacitor, a common electrode, and a pixel electrode are formed on the lower substrate. Although not shown, thereafter, a lower alignment layer, a liquid crystal layer, an upper alignment layer, and an upper substrate are positioned on the upper transparent electrode 159 .

19, on the lower substrate 150a, the gate electrode 151, the first insulating layer 152, the semiconductor layer 153, the second insulating layer 155, the third insulating layer 156, the lower transparent electrode 157a and 157c, a fourth insulating layer 158 and an upper transparent electrode 159 are stacked.

The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO). In addition, the data metal 160 spaced apart from the semiconductor layer 153 is made of a heterogeneous multi-layer metal such as Cu/MoTi. For example, the first layer of the data metal 160 is made of molybdenum titanium (MoTi), and the second layer is made of copper (Cu).

For this reason, in the structure of the back channel etched transistor according to the second embodiment of the present invention, copper (Cu) is included in the material of the data metal 160, so that the RC delay caused by the resistor and the capacitor is reduced.

On the other hand, as mentioned above, the conventionally proposed back channel etch transistor structure has a problem in that the characteristics of the device are deteriorated or deteriorated as copper ions contained in the material of the source and drain electrodes diffuse into the oxide semiconductor layer.

However, in the structure of the back channel etched transistor according to the second embodiment of the present invention, the data metal 160 and the semiconductor layer 153 do not directly contact but indirectly contact by the first lower transparent electrode 157a. In addition, the data metal 160 including copper (Cu) and the semiconductor layer 153 of IGZO are isolated from each other by the second insulating layer 155 covering them. As a result, since the diffusion (diffusion) of copper ions of the data metal 160 into the oxide semiconductor layer is prevented (or suppressed), the problem of deterioration or degradation of device characteristics is solved. In addition, since the back channel etch transistor structure according to the second embodiment of the present invention has a structure in which the drain electrode and the pixel electrode are integrated into one, the aperture ratio can be improved.

As described above, if the back channel etched transistor structure according to the first and second embodiments of the present invention is used, a liquid crystal display device can be manufactured through a total of eight mask processes.

A detailed description of an example in which a total of eight mask processes are used is as follows. A first mask is a process of forming a gate metal, a second mask is a process of forming a semiconductor layer, a third mask is a process of forming a contact hole of the gate pad part, a fourth mask is a process of forming a data metal, and a fifth mask is a process of forming a third insulating film and forming a contact hole, a sixth mask is a process of forming a lower transparent electrode, a seventh mask is a process of forming a fourth insulating film and forming a contact hole, and an eighth mask is an upper transparent electrode used in the process of forming

Meanwhile, since the structure of the back-channel etch transistor proposed in the present invention can be applied not only to the liquid crystal display but also to the organic light emitting display, the application of the improved structure to the organic light emitting display will also be briefly described.

<Third embodiment>

20 is a cross-sectional view of a display device according to a third embodiment of the present invention.

As shown in FIG. 20 , a gate metal (or gate electrode) 151 is formed on the lower substrate (not shown due to the characteristics of the planar structure). The gate metal 151 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The gate metal 151 is formed in the first direction (horizontal direction in the drawing). The gate metal 151 is defined as a gate wiring or a gate electrode depending on the region.

A first insulating layer 152 is formed on the gate metal 151 . The first insulating layer 152 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 152 may be defined as a gate insulating layer.

A semiconductor layer 153 is formed on the first insulating layer 152 . The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO), TiO2, ZnO, WO3, SnO2, or the like. The semiconductor layer 153 is formed to overlap the gate electrode 151 .

A data metal 160 is formed on the first insulating layer 152 . The data metal 160 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof and may be formed of a single layer or multiple layers. The data metal 160 is formed in the second direction (vertical direction in the drawing). The data metal 160 is formed on the first insulating layer 152 in the same manner as the semiconductor layer 153 , and is formed to be spaced apart from the first insulating layer 152 by a predetermined interval. The data metal 160 is defined as a data line.

A second insulating layer 155 is formed on the semiconductor layer 153 and the data metal 160 . The second insulating layer 155 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The second insulating layer 155 may be defined as a first passivation layer.

A third insulating layer 156 is formed on the second insulating layer 155 . The third insulating layer 156 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The third insulating layer 156 may be defined as a planarization layer for planarizing a surface.

The second insulating layer 155 and the third insulating layer 156 include a first contact hole CH1 exposing the data metal 160 . In addition, the third insulating layer 156 includes a second contact hole CH2 exposing the source region and the drain region of the semiconductor layer 153 . Meanwhile, the source region and the drain region of the semiconductor layer 153 exposed through the second contact hole CH2 of the third insulating layer 156 are metallized by dry etching or a heat treatment method. The resistance of the source region and the drain region of the semiconductor layer 153 metallized by dry etching or the like is reduced (a contact resistance with other metals may be reduced).

Lower transparent electrodes 157a and 157b are formed on the third insulating layer 156 . The lower transparent electrodes 157a and 157b may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The lower transparent electrodes 157a and 157b are connected to the first lower transparent electrode 157a connected to (or in contact with) the source region of the data metal 160 and the semiconductor layer 153 and the drain region of the semiconductor layer 153 . It is divided (or separated) by the second lower transparent electrode 157b. The first lower transparent electrode 157a is defined as a source electrode, and the second lower transparent electrode 157b is defined as a drain electrode.

A fourth insulating layer 158 is formed on the lower transparent electrodes 157a and 157b. The fourth insulating layer 158 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The fourth insulating layer 158 may be defined as a second passivation layer. The fourth insulating layer 158 includes a third contact hole CH3 exposing the second lower transparent electrode 157b connected to the drain region of the semiconductor layer 153 .

An upper transparent electrode 159 is formed on the fourth insulating layer 158 . The upper transparent electrode 159 may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper transparent electrode 159 is connected to the drain region of the semiconductor layer 153 through the second lower transparent electrode 157b.

The upper transparent electrode 159 may be changed to an opaque electrode instead of a transparent electrode depending on the light emission direction and the structure of the organic light emitting diode. For example, when the organic light emitting diode emits light in the direction of the lower substrate, the upper transparent electrode 159 is defined as the anode electrode of the organic light emitting diode and is formed as a transparent electrode. On the other hand, when the organic light emitting diode emits light in the direction of the upper substrate, the upper transparent electrode 159 is changed to an opaque electrode, which is defined as a cathode electrode of the organic light emitting diode.

A bank layer 161 is formed on the fourth insulating layer 158 . The bank layer 161 may be made of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The bank layer 161 covers a portion of the upper transparent electrode 159 and exposes the remaining portion, and serves to define an opening region.

A light emitting layer 162 is formed on the upper transparent electrode 159 . The light emitting layer 162 may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. However, the light emitting layer 162 is not limited thereto, and at least one of them may be omitted or other functional layers may be further included.

An upper common electrode 163 is formed on the emission layer 162 . The upper common electrode 163 may be formed of an opaque metal electrode such as aluminum (Al), silver (Ag), or magnesium-silver alloy (MgAg). The upper common electrode 163 is formed to cover the entire area of the sub-pixel (or the entire area of the display area).

The upper common electrode 163 may be changed to a transparent electrode instead of an opaque electrode depending on the light emitting direction and the structure of the organic light emitting diode. For example, when the organic light emitting diode emits light in the direction of the lower substrate, the upper common electrode 163 is defined as a cathode of the organic light emitting diode and is formed as an opaque electrode. On the other hand, when the organic light emitting diode emits light in the direction of the upper substrate, the upper common electrode 163 is changed to a transparent electrode, which is defined as the anode electrode of the organic light emitting diode.

Through the above process, a plurality of sub-pixels including a switching thin film transistor, a driving thin film transistor, a storage capacitor, and an organic light emitting diode are formed on the lower substrate. Although not shown, an upper substrate, etc. is then positioned on the upper common electrode 163 .

The semiconductor layer 153 of the back-channel etch transistor structure according to the third embodiment of the present invention is made of an oxide such as indium gallium zinc oxide (IGZO). In addition, the data metal 160 spaced apart from the semiconductor layer 153 is made of a heterogeneous multi-layer metal such as Cu/MoTi. For example, the first layer of the data metal 160 is made of molybdenum titanium (MoTi), and the second layer is made of copper (Cu).

For this reason, in the structure of the back channel etched transistor according to the third embodiment of the present invention, copper (Cu) is included in the material of the data metal 160, so that the RC delay caused by the resistor and the capacitor is reduced.

On the other hand, as mentioned above, the conventionally proposed back channel etch transistor structure has a problem in that the characteristics of the device are deteriorated or deteriorated as copper ions contained in the material of the source and drain electrodes diffuse into the oxide semiconductor layer.

However, in the back channel etch transistor structure according to the third embodiment of the present invention, the data metal 160 and the semiconductor layer 153 do not directly contact, but indirectly contact by the first lower transparent electrode 157a. In addition, the data metal 160 including copper (Cu) and the semiconductor layer 153 of IGZO are isolated from each other by the second insulating layer 155 covering them. As a result, since the diffusion (diffusion) of copper ions of the data metal 160 into the oxide semiconductor layer is prevented (or suppressed), the problem of deterioration or degradation of device characteristics is solved.

<Fourth embodiment>

21 is a cross-sectional view of a display device according to a fourth embodiment of the present invention.

As shown in FIG. 21 , a gate metal (or gate electrode) 151 is formed on the lower substrate (not shown due to the characteristics of the planar structure). The gate metal 151 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The gate metal 151 is formed in the first direction (horizontal direction in the drawing). The gate metal 151 is defined as a gate wiring or a gate electrode depending on the region.

A first insulating layer 152 is formed on the gate metal 151 . The first insulating layer 152 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 152 may be defined as a gate insulating layer.

A semiconductor layer 153 is formed on the first insulating layer 152 . The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO), TiO2, ZnO, WO3, SnO2, or the like. The semiconductor layer 153 is formed to overlap the gate electrode 151 .

A data metal 160 is formed on the first insulating layer 152 . The data metal 160 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof and may be formed of a single layer or multiple layers. The data metal 160 is formed in the second direction (vertical direction in the drawing). The data metal 160 is formed on the first insulating layer 152 in the same manner as the semiconductor layer 153 , and is formed to be spaced apart from the first insulating layer 152 by a predetermined interval. The data metal 160 is defined as a data line.

A second insulating layer 155 is formed on the semiconductor layer 153 and the data metal 160 . The second insulating layer 155 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The second insulating layer 155 may be defined as a first passivation layer.

A third insulating layer 156 is formed on the second insulating layer 155 . The third insulating layer 156 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The third insulating layer 156 may be defined as a planarization layer for planarizing a surface.

The second insulating layer 155 and the third insulating layer 156 include a first contact hole CH1 exposing the data metal 160 . In addition, the third insulating layer 156 includes a second contact hole CH2 exposing the source region and the drain region of the semiconductor layer 153 . Meanwhile, the source region and the drain region of the semiconductor layer 153 exposed through the second contact hole CH2 of the third insulating layer 156 are metallized by dry etching or a heat treatment method. The resistance of the source region and the drain region of the semiconductor layer 153 metallized by dry etching or the like is reduced (a contact resistance with other metals may be reduced).

A lower transparent electrode 157a is formed on the third insulating layer 156 . The lower transparent electrode 157a may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The lower transparent electrode 157a is connected to (or in contact with) the source region of the data metal 160 and the semiconductor layer 153 . The lower transparent electrode 157a is defined as a source electrode.

A fourth insulating layer 158 is formed on the lower transparent electrode 157a. The fourth insulating layer 158 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The fourth insulating layer 158 may be defined as a second passivation layer. The fourth insulating layer 158 includes a third contact hole CH3 exposing the drain region of the semiconductor layer 153 . The third contact hole CH3 is located in a region overlapping the gate metal 151 .

An upper transparent electrode 159 is formed on the fourth insulating layer 158 . The upper transparent electrode 159 may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper transparent electrode 159 is connected to the drain region of the semiconductor layer 153 through the fourth insulating layer 158 . The upper transparent electrode 159 serves as a drain electrode and is also defined as an anode electrode of an organic light emitting diode. That is, the third embodiment has a structure in which the drain electrode and the anode electrode are separated, but the fourth embodiment has a structure in which the drain electrode and the anode electrode are integrated into one.

The upper transparent electrode 159 may be changed to an opaque electrode instead of a transparent electrode depending on the light emission direction and the structure of the organic light emitting diode. For example, when the organic light emitting diode emits light in the direction of the lower substrate, the upper transparent electrode 159 is defined as the anode electrode of the organic light emitting diode and is formed as a transparent electrode. On the other hand, when the organic light emitting diode emits light in the direction of the upper substrate, the upper transparent electrode 159 is changed to an opaque electrode, which is defined as a cathode electrode of the organic light emitting diode.

A bank layer 161 is formed on the fourth insulating layer 158 . The bank layer 161 may be made of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The bank layer 161 covers a portion of the upper transparent electrode 159 and exposes the remaining portion, and serves to define an opening region.

A light emitting layer 162 is formed on the upper transparent electrode 159 . The light emitting layer 162 may include a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer. However, the light emitting layer 162 is not limited thereto, and at least one of them may be omitted or other functional layers may be further included.

An upper common electrode 163 is formed on the emission layer 162 . The upper common electrode 163 may be formed of an opaque metal electrode such as aluminum (Al), silver (Ag), or magnesium-silver alloy (MgAg). The upper common electrode 163 is formed to cover the entire area of the sub-pixel (or the entire area of the display area).

The upper common electrode 163 may be changed to a transparent electrode instead of an opaque electrode depending on the light emitting direction and the structure of the organic light emitting diode. For example, when the organic light emitting diode emits light in the direction of the lower substrate, the upper common electrode 163 is defined as a cathode of the organic light emitting diode and is formed as an opaque electrode. On the other hand, when the organic light emitting diode emits light in the direction of the upper substrate, the upper common electrode 163 is changed to a transparent electrode, which is defined as the anode electrode of the organic light emitting diode.

Through the above process, a plurality of sub-pixels including a switching thin film transistor, a driving thin film transistor, a storage capacitor, and an organic light emitting diode are formed on the lower substrate. Although not shown, an upper substrate, etc. is then positioned on the upper common electrode 163 .

The semiconductor layer 153 of the back-channel etch transistor structure according to the fourth embodiment of the present invention is made of an oxide such as indium gallium zinc oxide (IGZO). In addition, the data metal 160 spaced apart from the semiconductor layer 153 is made of a heterogeneous multi-layer metal such as Cu/MoTi. For example, the first layer of the data metal 160 is made of molybdenum titanium (MoTi), and the second layer is made of copper (Cu).

For this reason, in the structure of the back channel etched transistor according to the fourth embodiment of the present invention, copper (Cu) is included in the material of the data metal 160, so that the RC delay caused by the resistor and the capacitor is reduced.

On the other hand, as mentioned above, the conventionally proposed back channel etch transistor structure has a problem in that the characteristics of the device are deteriorated or deteriorated as copper ions contained in the material of the source and drain electrodes diffuse into the oxide semiconductor layer.

However, in the back channel etched transistor structure according to the fourth embodiment of the present invention, the data metal 160 and the semiconductor layer 153 do not directly contact, but indirectly contact by the first lower transparent electrode 157a. In addition, the data metal 160 including copper (Cu) and the semiconductor layer 153 of IGZO are isolated from each other by the second insulating layer 155 covering them. As a result, since the diffusion (diffusion) of copper ions of the data metal 160 into the oxide semiconductor layer is prevented (or suppressed), the problem of deterioration or degradation of device characteristics is solved. In addition, since the back channel etch transistor structure according to the fourth embodiment of the present invention has a structure in which the drain electrode and the pixel electrode are integrated into one, the aperture ratio can be improved.

<Fifth embodiment>

22 to 29 are plan views illustrating a process flow diagram of a display device according to a fifth embodiment of the present invention, FIG. 30 is a cross-sectional view illustrating region B1-B2 of FIG. 29, and FIG. 31 is an advantage of a dumbbell-shaped semiconductor layer. is a view for explaining the, and FIG. 32 is another exemplary diagram of a dumbbell-shaped semiconductor layer.

As shown in FIG. 22 , a gate metal (or gate electrode) 151 is formed on the lower substrate (not shown due to the characteristics of the planar structure). The gate metal 151 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof. and may be formed of a single layer or multiple layers. The gate metal 151 is formed in the first direction (horizontal direction in the drawing). The gate metal 151 is defined as a gate wiring or a gate electrode depending on the region.

23 , a first insulating layer 152 is formed on the gate metal 151 . The first insulating layer 152 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The first insulating layer 152 may be defined as a gate insulating layer.

A data metal 160 is formed on the first insulating layer 152 . The data metal 160 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and copper (Cu) or an alloy thereof and may be formed of a single layer or multiple layers. The data metal 160 is formed in the second direction (vertical direction in the drawing). The data metal 160 is defined as a data line.

24 , a semiconductor layer 153 is formed on the first insulating layer 152 . The semiconductor layer 153 is made of an oxide such as indium gallium zinc oxide (IGZO), TiO2, ZnO, WO3, SnO2, or the like. The semiconductor layer 153 is formed to overlap the gate electrode 151 in the first direction (horizontal direction in the drawing), and the data metal 160 is formed on the first insulating layer 152 in the same manner as the semiconductor layer 153 . However, it is formed to be spaced apart from the first insulating layer 152 by a predetermined interval. The data metal 160 is defined as a data line.

The semiconductor layer 153 may have a shape in which the source region and the drain region are larger than the channel region. In the semiconductor layer 153 , an area occupied by the source region and the drain region may be larger than an area occupied by the channel region. In the semiconductor layer 153 , the vertical length occupied by the source region and the drain region may be greater than the vertical length occupied by the channel region. For example, the semiconductor layer 153 may have a dumbbell shape in which the source region and the drain region are larger than that of the channel region.

25 , a second insulating layer 155 is formed on the semiconductor layer 153 and the data metal 160 . The second insulating layer 155 covers the semiconductor layer 153 and the data metal 160 . The second insulating layer 155 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The second insulating layer 155 may be defined as a first passivation layer. Although not shown, the second insulating layer 155 has a contact hole exposing a gate pad connected to the gate wiring of the gate metal 151 .

26 , a third insulating layer 156 is formed on the second insulating layer 155 . The third insulating layer 156 may be formed of an organic material such as polyimide, benzocyclobutene series resin, acrylate, or photoacrylate. The third insulating layer 156 may be defined as a planarization layer for planarizing a surface.

The second insulating layer 155 and the third insulating layer 156 include a first contact hole CH1 exposing the data metal 160 . In addition, the third insulating layer 156 includes a second contact hole CH2 exposing a first region (hereinafter, referred to as a source region) of the semiconductor layer 153 . Meanwhile, the source region of the semiconductor layer 153 exposed through the second contact hole CH2 of the third insulating layer 156 is metallized by dry etching or a heat treatment method. The resistance of the drain region of the semiconductor layer 153 metallized by dry etching or the like is reduced (it may reduce contact resistance with other metals).

27 , lower electrodes 157a and 157b (hereinafter referred to as lower transparent electrodes) are formed on the third insulating layer 156 . The lower transparent electrodes 157a and 157b may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The lower transparent electrodes 157a and 157b are the first lower transparent electrode 157a connected to (or in contact with) the source region of the data metal 160 and the semiconductor layer 153 and the second lower transparent electrode connected to the common voltage line. (157b) is distinguished (or separated). The first lower transparent electrode 157a is defined as a source electrode, and the second lower transparent electrode 157b is defined as a common electrode.

28 , a fourth insulating layer 158 is formed on the lower transparent electrodes 157a and 157b. The fourth insulating layer 158 may be formed of a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a double layer thereof. The fourth insulating layer 158 may be defined as a second passivation layer. A third contact hole CH3 exposing a drain region of the semiconductor layer 153 is included in the fourth insulating layer 158 , the third insulating layer 156 , and the second insulating layer 155 .

29 , an upper electrode 159 (hereinafter referred to as an upper transparent electrode) is formed on the fourth insulating layer 158 . The upper transparent electrode 159 may be formed of a transparent oxide electrode such as indium tin oxide (ITO) or indium zinc oxide (IZO). The upper transparent electrode 159 is connected to the drain region of the semiconductor layer 153 through the third contact hole CH3. The upper transparent electrode 159 is defined as a pixel electrode.

The upper transparent electrode 159 may have a finger shape separated into a plurality of openings (or transmission regions) formed at the intersection of the gate metal 151 and the data metal 160 . The upper transparent electrode 159 may have a shape of an inequality sign (<) inclined with respect to the central region of the opening region (or the transmissive region), but is not limited thereto. When the upper transparent electrode 159 has an inequality sign (<) shape, the data metal 160 may also include a region having an inequality sign (<) shape like the shape of the upper transparent electrode 159 .

Through the above process, a plurality of sub-pixels including a switching thin film transistor, a storage capacitor, a common electrode, and a pixel electrode are formed on the lower substrate. Although not shown, thereafter, a lower alignment layer, a liquid crystal layer, an upper alignment layer, and an upper substrate are positioned on the upper transparent electrode 159 .

30, on the lower substrate 150a, the gate electrode 151, the first insulating film 152, the semiconductor layers 153a and 153b, the second insulating film 155, the third insulating film 156, the lower part Transparent electrodes 157a and 157b, a fourth insulating layer 158 and an upper transparent electrode 159 are stacked.

The semiconductor layers 153a and 153b are made of an oxide such as indium gallium zinc oxide (IGZO). In addition, the data metal 160 positioned under the metallized semiconductor layer 153a is made of a heterogeneous multilayer metal such as Cu/MoTi. For example, the first layer of the data metal 160 is made of molybdenum titanium (MoTi), and the second layer is made of copper (Cu).

For this reason, in the structure of the back channel etched transistor according to the fifth embodiment of the present invention, copper (Cu) is included in the material of the data metal 160, so that the RC delay caused by the resistor and the capacitor is reduced.

31, in the back channel etch transistor structure according to the fifth embodiment of the present invention, the source and drain regions 153b1 and 153b2 are larger than the channel region 153b of the semiconductor layer. can

As shown in FIG. 31A , the semiconductor layer may be formed such that the channel region 153b, the source region, and the drain region all have the same size. 31A shows that when the second and third contact holes CH2 and CH3 are formed by the dry etching method, a short occurs between the gate metal 151 and the data metal when the size of the holes increases as CH2' and CH3'. Very likely.

On the other hand, as shown in FIG. 31B , the semiconductor layer may be formed so that the source and drain regions 153b1 and 153b2 have a larger dumbbell shape than the channel region 153b. 31B shows that when the second and third contact holes CH2 and CH3 are formed by the dry etching method, the source and drain regions 153b1 and 153b2 are sufficient even when the size of the holes increases as CH2' and CH3'. Since it has a size, it is possible to prevent the possibility of a short circuit between the gate metal 151 and the data metal. In addition, the contact resistance may be improved due to an increase in the area of the second and third contact holes CH2 and CH3, and as a result, the device characteristics (increased current mobility) may be improved.

32, the back channel etch transistor structure according to the fifth embodiment of the present invention has a dumbbell shape in which the source and drain regions 153b1 and 153b2 are larger than the channel region 153b of the semiconductor layer. , the source and drain regions 153b1 and 153b2 may have a polygonal shape ((a) of FIG. 32) or an elliptical shape with a long length in the vertical direction ((b) of FIG. 32).

Meanwhile, the structure of the back-channel etched transistor proposed in the present invention can be applied not only to a liquid crystal display but also to an organic light emitting display. A description thereof will be made clear with reference to FIGS. 20 or 21 and 30 .

As described above, the present invention has an effect of providing a display device implemented with a transistor capable of improving the problem of deterioration or deterioration of device characteristics. In addition, the present invention has the effect of improving the aperture ratio of the display panel by changing the structure of the electrodes constituting the transistor.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

110: image supply unit 120: timing control unit
130: gate driving unit 140: data driving unit
150: display panel 150a: lower substrate
151: gate electrode 152: first insulating film
153: semiconductor layer 155: second insulating film
156: third insulating layer 157a to 157c: lower transparent electrode
158: fourth insulating layer 159: upper transparent electrode
160: data metal

Claims (15)

delete delete delete delete delete delete delete delete a thin film transistor formed at the intersection of the data line and the gate line;
a display panel including sub-pixels having the thin film transistor; and
a driving unit for driving the display panel;
In the sub-pixels, a metallized semiconductor layer positioned on the data metal constituting the data line and a first region of the oxide semiconductor layer constituting the thin film transistor indirectly contact by a lower electrode. . 10. The method of claim 9,
The oxide semiconductor layer is
A display device having a shape in which the source region and the drain region are larger than the channel region. 10. The method of claim 9,
The sub-pixels are
a gate metal formed on the lower substrate;
a first insulating film formed on the lower substrate and covering the gate metal;
the data metal formed on the first insulating layer;
The oxide semiconductor layer formed on the first insulating layer and formed in a first direction in a region overlapping the gate metal and the oxide semiconductor layer formed in a second direction spaced apart from the oxide semiconductor layer and intersecting the first direction and formed on the data metal the formed metallized semiconductor layer;
a second insulating layer formed on the first insulating layer and covering the oxide semiconductor layer, the metalized semiconductor layer, and the data metal;
a third insulating layer formed on the second insulating layer and having a first contact hole exposing the metallized semiconductor layer and a second contact hole exposing the first region of the oxide semiconductor layer;
and a first lower electrode formed on the third insulating layer and electrically connecting the metallized semiconductor layer and a first region of the oxide semiconductor layer. 12. The method of claim 11,
The sub-pixels are
a second lower electrode formed on the third insulating film and connected to a common voltage line;
a fourth insulating layer formed on the third insulating layer, covering the first and second lower electrodes, and having a third contact hole exposing a second region of the oxide semiconductor layer;
and an upper electrode formed on the fourth insulating layer and connected to the second region of the oxide semiconductor layer, respectively. 10. The method of claim 9,
The lower electrode is
A display device selected with a transparent oxide electrode. delete delete

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